1 //-----------------------------------------------------------------------------
2 // Gerhard de Koning Gans - May 2008
3 // Hagen Fritsch - June 2010
4 // Gerhard de Koning Gans - May 2011
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
9 //-----------------------------------------------------------------------------
10 // Routines to support iClass.
11 //-----------------------------------------------------------------------------
12 // Based on ISO14443a implementation. Still in experimental phase.
13 // Contribution made during a security research at Radboud University Nijmegen
15 // Please feel free to contribute and extend iClass support!!
16 //-----------------------------------------------------------------------------
25 // We still have sometimes a demodulation error when snooping iClass communication.
26 // The resulting trace of a read-block-03 command may look something like this:
28 // + 22279: : 0c 03 e8 01
30 // ...with an incorrect answer...
32 // + 85: 0: TAG ff! ff! ff! ff! ff! ff! ff! ff! bb 33 bb 00 01! 0e! 04! bb !crc
34 // We still left the error signalling bytes in the traces like 0xbb
36 // A correct trace should look like this:
38 // + 21112: : 0c 03 e8 01
39 // + 85: 0: TAG ff ff ff ff ff ff ff ff ea f5
41 //-----------------------------------------------------------------------------
43 #include "proxmark3.h"
49 static uint8_t *trace
= (uint8_t *) BigBuf
;
50 static int traceLen
= 0;
51 static int rsamples
= 0;
54 // Sequence D: 11110000 modulation with subcarrier during first half
55 // Sequence E: 00001111 modulation with subcarrier during second half
56 // Sequence F: 00000000 no modulation with subcarrier
58 // Sequence X: 00001100 drop after half a period
59 // Sequence Y: 00000000 no drop
60 // Sequence Z: 11000000 drop at start
68 static const uint8_t OddByteParity
[256] = {
69 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
70 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
71 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
72 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
73 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
74 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
75 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
76 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
77 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
78 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
79 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
80 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
81 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
82 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
83 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
84 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1
87 //static const uint8_t MajorityNibble[16] = { 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1 };
88 //static const uint8_t MajorityNibble[16] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
90 // BIG CHANGE - UNDERSTAND THIS BEFORE WE COMMIT
91 #define RECV_CMD_OFFSET 3032
92 #define RECV_RES_OFFSET 3096
93 #define DMA_BUFFER_OFFSET 3160
94 #define DMA_BUFFER_SIZE 4096
95 #define TRACE_LENGTH 3000
98 //-----------------------------------------------------------------------------
99 // The software UART that receives commands from the reader, and its state
101 //-----------------------------------------------------------------------------
105 STATE_START_OF_COMMUNICATION
,
126 static RAMFUNC
int MillerDecoding(int bit
)
131 if(!Uart
.bitBuffer
) {
132 Uart
.bitBuffer
= bit
^ 0xFF0;
136 Uart
.bitBuffer
<<= 4;
137 Uart
.bitBuffer
^= bit
;
141 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
144 if(Uart.byteCnt > 15) { return TRUE; }
150 if(Uart
.state
!= STATE_UNSYNCD
) {
153 if((Uart
.bitBuffer
& Uart
.syncBit
) ^ Uart
.syncBit
) {
159 if(((Uart
.bitBuffer
<< 1) & Uart
.syncBit
) ^ Uart
.syncBit
) {
165 if(bit
!= bitright
) { bit
= bitright
; }
168 // So, now we only have to deal with *bit*, lets see...
169 if(Uart
.posCnt
== 1) {
170 // measurement first half bitperiod
172 // Drop in first half means that we are either seeing
175 if(Uart
.nOutOfCnt
== 1) {
176 // End of Communication
177 Uart
.state
= STATE_UNSYNCD
;
179 if(Uart
.byteCnt
== 0) {
180 // Its not straightforward to show single EOFs
181 // So just leave it and do not return TRUE
182 Uart
.output
[Uart
.byteCnt
] = 0xf0;
185 // Calculate the parity bit for the client...
192 else if(Uart
.state
!= STATE_START_OF_COMMUNICATION
) {
193 // When not part of SOF or EOF, it is an error
194 Uart
.state
= STATE_UNSYNCD
;
201 // measurement second half bitperiod
202 // Count the bitslot we are in... (ISO 15693)
206 if(Uart
.dropPosition
) {
207 if(Uart
.state
== STATE_START_OF_COMMUNICATION
) {
213 // It is an error if we already have seen a drop in current frame
214 Uart
.state
= STATE_UNSYNCD
;
218 Uart
.dropPosition
= Uart
.nOutOfCnt
;
225 if(Uart
.nOutOfCnt
== Uart
.OutOfCnt
&& Uart
.OutOfCnt
== 4) {
228 if(Uart
.state
== STATE_START_OF_COMMUNICATION
) {
229 if(Uart
.dropPosition
== 4) {
230 Uart
.state
= STATE_RECEIVING
;
233 else if(Uart
.dropPosition
== 3) {
234 Uart
.state
= STATE_RECEIVING
;
236 //Uart.output[Uart.byteCnt] = 0xdd;
240 Uart
.state
= STATE_UNSYNCD
;
243 Uart
.dropPosition
= 0;
248 if(!Uart
.dropPosition
) {
249 Uart
.state
= STATE_UNSYNCD
;
258 //if(Uart.dropPosition == 1) { Uart.dropPosition = 2; }
259 //else if(Uart.dropPosition == 2) { Uart.dropPosition = 1; }
261 Uart
.shiftReg
^= ((Uart
.dropPosition
& 0x03) << 6);
263 Uart
.dropPosition
= 0;
265 if(Uart
.bitCnt
== 8) {
266 Uart
.output
[Uart
.byteCnt
] = (Uart
.shiftReg
& 0xff);
269 // Calculate the parity bit for the client...
270 Uart
.parityBits
<<= 1;
271 Uart
.parityBits
^= OddByteParity
[(Uart
.shiftReg
& 0xff)];
279 else if(Uart
.nOutOfCnt
== Uart
.OutOfCnt
) {
282 if(!Uart
.dropPosition
) {
283 Uart
.state
= STATE_UNSYNCD
;
289 Uart
.output
[Uart
.byteCnt
] = (Uart
.dropPosition
& 0xff);
292 // Calculate the parity bit for the client...
293 Uart
.parityBits
<<= 1;
294 Uart
.parityBits
^= OddByteParity
[(Uart
.dropPosition
& 0xff)];
299 Uart
.dropPosition
= 0;
304 Uart.output[Uart.byteCnt] = 0xAA;
306 Uart.output[Uart.byteCnt] = error & 0xFF;
308 Uart.output[Uart.byteCnt] = 0xAA;
310 Uart.output[Uart.byteCnt] = (Uart.bitBuffer >> 8) & 0xFF;
312 Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
314 Uart.output[Uart.byteCnt] = (Uart.syncBit >> 3) & 0xFF;
316 Uart.output[Uart.byteCnt] = 0xAA;
324 bit
= Uart
.bitBuffer
& 0xf0;
326 bit
^= 0x0F; // drops become 1s ;-)
328 // should have been high or at least (4 * 128) / fc
329 // according to ISO this should be at least (9 * 128 + 20) / fc
330 if(Uart
.highCnt
== 8) {
331 // we went low, so this could be start of communication
332 // it turns out to be safer to choose a less significant
333 // syncbit... so we check whether the neighbour also represents the drop
334 Uart
.posCnt
= 1; // apparently we are busy with our first half bit period
335 Uart
.syncBit
= bit
& 8;
337 if(!Uart
.syncBit
) { Uart
.syncBit
= bit
& 4; Uart
.samples
= 2; }
338 else if(bit
& 4) { Uart
.syncBit
= bit
& 4; Uart
.samples
= 2; bit
<<= 2; }
339 if(!Uart
.syncBit
) { Uart
.syncBit
= bit
& 2; Uart
.samples
= 1; }
340 else if(bit
& 2) { Uart
.syncBit
= bit
& 2; Uart
.samples
= 1; bit
<<= 1; }
341 if(!Uart
.syncBit
) { Uart
.syncBit
= bit
& 1; Uart
.samples
= 0;
342 if(Uart
.syncBit
&& (Uart
.bitBuffer
& 8)) {
345 // the first half bit period is expected in next sample
350 else if(bit
& 1) { Uart
.syncBit
= bit
& 1; Uart
.samples
= 0; }
353 Uart
.state
= STATE_START_OF_COMMUNICATION
;
358 Uart
.OutOfCnt
= 4; // Start at 1/4, could switch to 1/256
359 Uart
.dropPosition
= 0;
368 if(Uart
.highCnt
< 8) {
377 //=============================================================================
378 // ISO 14443 Type A - Manchester
379 //=============================================================================
384 DEMOD_START_OF_COMMUNICATION
,
385 DEMOD_START_OF_COMMUNICATION2
,
386 DEMOD_START_OF_COMMUNICATION3
,
390 DEMOD_END_OF_COMMUNICATION
,
391 DEMOD_END_OF_COMMUNICATION2
,
415 static RAMFUNC
int ManchesterDecoding(int v
)
422 Demod
.buffer
= Demod
.buffer2
;
423 Demod
.buffer2
= Demod
.buffer3
;
431 if(Demod
.state
==DEMOD_UNSYNCD
) {
432 Demod
.output
[Demod
.len
] = 0xfa;
435 Demod
.posCount
= 1; // This is the first half bit period, so after syncing handle the second part
436 /* if(bit & 0x08) { Demod.syncBit = 0x08; }
438 if(bit & 0x04) { Demod.syncBit = 0x04; }
440 else if(bit & 0x04) { Demod.syncBit = 0x04; bit <<= 4; }
442 if(bit & 0x02) { Demod.syncBit = 0x02; }
444 else if(bit & 0x02) { Demod.syncBit = 0x02; bit <<= 4; }
446 if(bit & 0x01) { Demod.syncBit = 0x01; }
448 if(Demod.syncBit && (Demod.buffer & 0x08)) {
449 Demod.syncBit = 0x08;
451 // The first half bitperiod is expected in next sample
453 Demod.output[Demod.len] = 0xfb;
456 else if(bit & 0x01) { Demod.syncBit = 0x01; }
460 Demod
.syncBit
= 0x08;
467 Demod
.syncBit
= 0x04;
474 Demod
.syncBit
= 0x02;
477 if(bit
& 0x01 && Demod
.syncBit
) {
478 Demod
.syncBit
= 0x01;
483 Demod
.state
= DEMOD_START_OF_COMMUNICATION
;
484 Demod
.sub
= SUB_FIRST_HALF
;
487 Demod
.parityBits
= 0;
490 //if(trigger) LED_A_OFF(); // Not useful in this case...
491 switch(Demod
.syncBit
) {
492 case 0x08: Demod
.samples
= 3; break;
493 case 0x04: Demod
.samples
= 2; break;
494 case 0x02: Demod
.samples
= 1; break;
495 case 0x01: Demod
.samples
= 0; break;
497 // SOF must be long burst... otherwise stay unsynced!!!
498 if(!(Demod
.buffer
& Demod
.syncBit
) || !(Demod
.buffer2
& Demod
.syncBit
)) {
499 Demod
.state
= DEMOD_UNSYNCD
;
503 // SOF must be long burst... otherwise stay unsynced!!!
504 if(!(Demod
.buffer2
& Demod
.syncBit
) || !(Demod
.buffer3
& Demod
.syncBit
)) {
505 Demod
.state
= DEMOD_UNSYNCD
;
515 modulation
= bit
& Demod
.syncBit
;
516 modulation
|= ((bit
<< 1) ^ ((Demod
.buffer
& 0x08) >> 3)) & Demod
.syncBit
;
517 //modulation = ((bit << 1) ^ ((Demod.buffer & 0x08) >> 3)) & Demod.syncBit;
521 if(Demod
.posCount
==0) {
524 Demod
.sub
= SUB_FIRST_HALF
;
527 Demod
.sub
= SUB_NONE
;
532 /*(modulation && (Demod.sub == SUB_FIRST_HALF)) {
533 if(Demod.state!=DEMOD_ERROR_WAIT) {
534 Demod.state = DEMOD_ERROR_WAIT;
535 Demod.output[Demod.len] = 0xaa;
539 //else if(modulation) {
541 if(Demod
.sub
== SUB_FIRST_HALF
) {
542 Demod
.sub
= SUB_BOTH
;
545 Demod
.sub
= SUB_SECOND_HALF
;
548 else if(Demod
.sub
== SUB_NONE
) {
549 if(Demod
.state
== DEMOD_SOF_COMPLETE
) {
550 Demod
.output
[Demod
.len
] = 0x0f;
552 Demod
.parityBits
<<= 1;
553 Demod
.parityBits
^= OddByteParity
[0x0f];
554 Demod
.state
= DEMOD_UNSYNCD
;
559 Demod
.state
= DEMOD_ERROR_WAIT
;
562 /*if(Demod.state!=DEMOD_ERROR_WAIT) {
563 Demod.state = DEMOD_ERROR_WAIT;
564 Demod.output[Demod.len] = 0xaa;
569 switch(Demod
.state
) {
570 case DEMOD_START_OF_COMMUNICATION
:
571 if(Demod
.sub
== SUB_BOTH
) {
572 //Demod.state = DEMOD_MANCHESTER_D;
573 Demod
.state
= DEMOD_START_OF_COMMUNICATION2
;
575 Demod
.sub
= SUB_NONE
;
578 Demod
.output
[Demod
.len
] = 0xab;
579 Demod
.state
= DEMOD_ERROR_WAIT
;
583 case DEMOD_START_OF_COMMUNICATION2
:
584 if(Demod
.sub
== SUB_SECOND_HALF
) {
585 Demod
.state
= DEMOD_START_OF_COMMUNICATION3
;
588 Demod
.output
[Demod
.len
] = 0xab;
589 Demod
.state
= DEMOD_ERROR_WAIT
;
593 case DEMOD_START_OF_COMMUNICATION3
:
594 if(Demod
.sub
== SUB_SECOND_HALF
) {
595 // Demod.state = DEMOD_MANCHESTER_D;
596 Demod
.state
= DEMOD_SOF_COMPLETE
;
597 //Demod.output[Demod.len] = Demod.syncBit & 0xFF;
601 Demod
.output
[Demod
.len
] = 0xab;
602 Demod
.state
= DEMOD_ERROR_WAIT
;
606 case DEMOD_SOF_COMPLETE
:
607 case DEMOD_MANCHESTER_D
:
608 case DEMOD_MANCHESTER_E
:
609 // OPPOSITE FROM ISO14443 - 11110000 = 0 (1 in 14443)
610 // 00001111 = 1 (0 in 14443)
611 if(Demod
.sub
== SUB_SECOND_HALF
) { // SUB_FIRST_HALF
613 Demod
.shiftReg
= (Demod
.shiftReg
>> 1) ^ 0x100;
614 Demod
.state
= DEMOD_MANCHESTER_D
;
616 else if(Demod
.sub
== SUB_FIRST_HALF
) { // SUB_SECOND_HALF
618 Demod
.shiftReg
>>= 1;
619 Demod
.state
= DEMOD_MANCHESTER_E
;
621 else if(Demod
.sub
== SUB_BOTH
) {
622 Demod
.state
= DEMOD_MANCHESTER_F
;
625 Demod
.state
= DEMOD_ERROR_WAIT
;
630 case DEMOD_MANCHESTER_F
:
631 // Tag response does not need to be a complete byte!
632 if(Demod
.len
> 0 || Demod
.bitCount
> 0) {
633 if(Demod
.bitCount
> 1) { // was > 0, do not interpret last closing bit, is part of EOF
634 Demod
.shiftReg
>>= (9 - Demod
.bitCount
);
635 Demod
.output
[Demod
.len
] = Demod
.shiftReg
& 0xff;
637 // No parity bit, so just shift a 0
638 Demod
.parityBits
<<= 1;
641 Demod
.state
= DEMOD_UNSYNCD
;
645 Demod
.output
[Demod
.len
] = 0xad;
646 Demod
.state
= DEMOD_ERROR_WAIT
;
651 case DEMOD_ERROR_WAIT
:
652 Demod
.state
= DEMOD_UNSYNCD
;
656 Demod
.output
[Demod
.len
] = 0xdd;
657 Demod
.state
= DEMOD_UNSYNCD
;
661 /*if(Demod.bitCount>=9) {
662 Demod.output[Demod.len] = Demod.shiftReg & 0xff;
665 Demod.parityBits <<= 1;
666 Demod.parityBits ^= ((Demod.shiftReg >> 8) & 0x01);
671 if(Demod
.bitCount
>=8) {
672 Demod
.shiftReg
>>= 1;
673 Demod
.output
[Demod
.len
] = (Demod
.shiftReg
& 0xff);
676 // FOR ISO15639 PARITY NOT SEND OTA, JUST CALCULATE IT FOR THE CLIENT
677 Demod
.parityBits
<<= 1;
678 Demod
.parityBits
^= OddByteParity
[(Demod
.shiftReg
& 0xff)];
685 Demod
.output
[Demod
.len
] = 0xBB;
687 Demod
.output
[Demod
.len
] = error
& 0xFF;
689 Demod
.output
[Demod
.len
] = 0xBB;
691 Demod
.output
[Demod
.len
] = bit
& 0xFF;
693 Demod
.output
[Demod
.len
] = Demod
.buffer
& 0xFF;
696 Demod
.output
[Demod
.len
] = Demod
.buffer2
& 0xFF;
698 Demod
.output
[Demod
.len
] = Demod
.syncBit
& 0xFF;
700 Demod
.output
[Demod
.len
] = 0xBB;
707 } // end (state != UNSYNCED)
712 //=============================================================================
713 // Finally, a `sniffer' for ISO 14443 Type A
714 // Both sides of communication!
715 //=============================================================================
717 //-----------------------------------------------------------------------------
718 // Record the sequence of commands sent by the reader to the tag, with
719 // triggering so that we start recording at the point that the tag is moved
721 //-----------------------------------------------------------------------------
722 void RAMFUNC
SnoopIClass(void)
724 // #define RECV_CMD_OFFSET 2032 // original (working as of 21/2/09) values
725 // #define RECV_RES_OFFSET 2096 // original (working as of 21/2/09) values
726 // #define DMA_BUFFER_OFFSET 2160 // original (working as of 21/2/09) values
727 // #define DMA_BUFFER_SIZE 4096 // original (working as of 21/2/09) values
728 // #define TRACE_LENGTH 2000 // original (working as of 21/2/09) values
730 // We won't start recording the frames that we acquire until we trigger;
731 // a good trigger condition to get started is probably when we see a
732 // response from the tag.
733 //int triggered = FALSE; // FALSE to wait first for card
735 // The command (reader -> tag) that we're receiving.
736 // The length of a received command will in most cases be no more than 18 bytes.
737 // So 32 should be enough!
738 uint8_t *receivedCmd
= (((uint8_t *)BigBuf
) + RECV_CMD_OFFSET
);
739 // The response (tag -> reader) that we're receiving.
740 uint8_t *receivedResponse
= (((uint8_t *)BigBuf
) + RECV_RES_OFFSET
);
742 // As we receive stuff, we copy it from receivedCmd or receivedResponse
743 // into trace, along with its length and other annotations.
744 //uint8_t *trace = (uint8_t *)BigBuf;
746 traceLen
= 0; // uncommented to fix ISSUE 15 - gerhard - jan2011
748 // The DMA buffer, used to stream samples from the FPGA
749 int8_t *dmaBuf
= ((int8_t *)BigBuf
) + DMA_BUFFER_OFFSET
;
755 // Count of samples received so far, so that we can include timing
756 // information in the trace buffer.
760 memset(trace
, 0x44, RECV_CMD_OFFSET
);
762 // Set up the demodulator for tag -> reader responses.
763 Demod
.output
= receivedResponse
;
765 Demod
.state
= DEMOD_UNSYNCD
;
767 // Setup for the DMA.
770 lastRxCounter
= DMA_BUFFER_SIZE
;
771 FpgaSetupSscDma((uint8_t *)dmaBuf
, DMA_BUFFER_SIZE
);
773 // And the reader -> tag commands
774 memset(&Uart
, 0, sizeof(Uart
));
775 Uart
.output
= receivedCmd
;
776 Uart
.byteCntMax
= 32; // was 100 (greg)////////////////////////////////////////////////////////////////////////
777 Uart
.state
= STATE_UNSYNCD
;
779 // And put the FPGA in the appropriate mode
780 // Signal field is off with the appropriate LED
782 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A
| FPGA_HF_ISO14443A_SNIFFER
);
783 SetAdcMuxFor(GPIO_MUXSEL_HIPKD
);
790 // And now we loop, receiving samples.
794 int behindBy
= (lastRxCounter
- AT91C_BASE_PDC_SSC
->PDC_RCR
) &
796 if(behindBy
> maxBehindBy
) {
797 maxBehindBy
= behindBy
;
799 Dbprintf("blew circular buffer! behindBy=0x%x", behindBy
);
803 if(behindBy
< 1) continue;
809 if(upTo
- dmaBuf
> DMA_BUFFER_SIZE
) {
810 upTo
-= DMA_BUFFER_SIZE
;
811 lastRxCounter
+= DMA_BUFFER_SIZE
;
812 AT91C_BASE_PDC_SSC
->PDC_RNPR
= (uint32_t) upTo
;
813 AT91C_BASE_PDC_SSC
->PDC_RNCR
= DMA_BUFFER_SIZE
;
822 //decbyte ^= ((smpl & 0x01) << (3 - div));
823 //decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1)) << (3 - div)); // better already...
824 //decbyte ^= (((smpl & 0x01) | ((smpl & 0x02) >> 1) | ((smpl & 0x04) >> 2)) << (3 - div)); // even better...
826 decbyte
^= (1 << (3 - div
));
828 //decbyte ^= (MajorityNibble[(smpl & 0x0F)] << (3 - div));
830 // FOR READER SIDE COMMUMICATION...
831 //decbyte ^= ((smpl & 0x10) << (3 - div));
833 decbyter
^= (smpl
& 0x30);
837 if((div
+ 1) % 2 == 0) {
839 if(MillerDecoding((smpl
& 0xF0) >> 4)) {
840 rsamples
= samples
- Uart
.samples
;
843 trace
[traceLen
++] = ((rsamples
>> 0) & 0xff);
844 trace
[traceLen
++] = ((rsamples
>> 8) & 0xff);
845 trace
[traceLen
++] = ((rsamples
>> 16) & 0xff);
846 trace
[traceLen
++] = ((rsamples
>> 24) & 0xff);
847 trace
[traceLen
++] = ((Uart
.parityBits
>> 0) & 0xff);
848 trace
[traceLen
++] = ((Uart
.parityBits
>> 8) & 0xff);
849 trace
[traceLen
++] = ((Uart
.parityBits
>> 16) & 0xff);
850 trace
[traceLen
++] = ((Uart
.parityBits
>> 24) & 0xff);
851 trace
[traceLen
++] = Uart
.byteCnt
;
852 memcpy(trace
+traceLen
, receivedCmd
, Uart
.byteCnt
);
853 traceLen
+= Uart
.byteCnt
;
854 if(traceLen
> TRACE_LENGTH
) break;
856 /* And ready to receive another command. */
857 Uart
.state
= STATE_UNSYNCD
;
858 /* And also reset the demod code, which might have been */
859 /* false-triggered by the commands from the reader. */
860 Demod
.state
= DEMOD_UNSYNCD
;
869 if(ManchesterDecoding(smpl
& 0x0F)) {
870 rsamples
= samples
- Demod
.samples
;
873 // timestamp, as a count of samples
874 trace
[traceLen
++] = ((rsamples
>> 0) & 0xff);
875 trace
[traceLen
++] = ((rsamples
>> 8) & 0xff);
876 trace
[traceLen
++] = ((rsamples
>> 16) & 0xff);
877 trace
[traceLen
++] = 0x80 | ((rsamples
>> 24) & 0xff);
878 trace
[traceLen
++] = ((Demod
.parityBits
>> 0) & 0xff);
879 trace
[traceLen
++] = ((Demod
.parityBits
>> 8) & 0xff);
880 trace
[traceLen
++] = ((Demod
.parityBits
>> 16) & 0xff);
881 trace
[traceLen
++] = ((Demod
.parityBits
>> 24) & 0xff);
883 trace
[traceLen
++] = Demod
.len
;
884 memcpy(trace
+traceLen
, receivedResponse
, Demod
.len
);
885 traceLen
+= Demod
.len
;
886 if(traceLen
> TRACE_LENGTH
) break;
890 // And ready to receive another response.
891 memset(&Demod
, 0, sizeof(Demod
));
892 Demod
.output
= receivedResponse
;
893 Demod
.state
= DEMOD_UNSYNCD
;
903 DbpString("cancelled_a");
908 DbpString("COMMAND FINISHED");
910 Dbprintf("%x %x %x", maxBehindBy
, Uart
.state
, Uart
.byteCnt
);
911 Dbprintf("%x %x %x", Uart
.byteCntMax
, traceLen
, (int)Uart
.output
[0]);
914 AT91C_BASE_PDC_SSC
->PDC_PTCR
= AT91C_PDC_RXTDIS
;
915 Dbprintf("%x %x %x", maxBehindBy
, Uart
.state
, Uart
.byteCnt
);
916 Dbprintf("%x %x %x", Uart
.byteCntMax
, traceLen
, (int)Uart
.output
[0]);