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1 //-----------------------------------------------------------------------------
2 // Merlok - June 2011, 2012
3 // Gerhard de Koning Gans - May 2008
4 // Hagen Fritsch - June 2010
5 //
6 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
7 // at your option, any later version. See the LICENSE.txt file for the text of
8 // the license.
9 //-----------------------------------------------------------------------------
10 // Routines to support ISO 14443 type A.
11 //-----------------------------------------------------------------------------
12 #include "iso14443a.h"
13
14 static uint32_t iso14a_timeout;
15 int rsamples = 0;
16 uint8_t trigger = 0;
17 // the block number for the ISO14443-4 PCB
18 static uint8_t iso14_pcb_blocknum = 0;
19
20 static uint8_t* free_buffer_pointer;
21
22 //
23 // ISO14443 timing:
24 //
25 // minimum time between the start bits of consecutive transfers from reader to tag: 7000 carrier (13.56Mhz) cycles
26 #define REQUEST_GUARD_TIME (7000/16 + 1)
27 // minimum time between last modulation of tag and next start bit from reader to tag: 1172 carrier cycles
28 #define FRAME_DELAY_TIME_PICC_TO_PCD (1172/16 + 1)
29 // bool LastCommandWasRequest = FALSE;
30
31 //
32 // Total delays including SSC-Transfers between ARM and FPGA. These are in carrier clock cycles (1/13,56MHz)
33 //
34 // When the PM acts as reader and is receiving tag data, it takes
35 // 3 ticks delay in the AD converter
36 // 16 ticks until the modulation detector completes and sets curbit
37 // 8 ticks until bit_to_arm is assigned from curbit
38 // 8*16 ticks for the transfer from FPGA to ARM
39 // 4*16 ticks until we measure the time
40 // - 8*16 ticks because we measure the time of the previous transfer
41 #define DELAY_AIR2ARM_AS_READER (3 + 16 + 8 + 8*16 + 4*16 - 8*16)
42
43 // When the PM acts as a reader and is sending, it takes
44 // 4*16 ticks until we can write data to the sending hold register
45 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
46 // 8 ticks until the first transfer starts
47 // 8 ticks later the FPGA samples the data
48 // 1 tick to assign mod_sig_coil
49 #define DELAY_ARM2AIR_AS_READER (4*16 + 8*16 + 8 + 8 + 1)
50
51 // When the PM acts as tag and is receiving it takes
52 // 2 ticks delay in the RF part (for the first falling edge),
53 // 3 ticks for the A/D conversion,
54 // 8 ticks on average until the start of the SSC transfer,
55 // 8 ticks until the SSC samples the first data
56 // 7*16 ticks to complete the transfer from FPGA to ARM
57 // 8 ticks until the next ssp_clk rising edge
58 // 4*16 ticks until we measure the time
59 // - 8*16 ticks because we measure the time of the previous transfer
60 #define DELAY_AIR2ARM_AS_TAG (2 + 3 + 8 + 8 + 7*16 + 8 + 4*16 - 8*16)
61
62 // The FPGA will report its internal sending delay in
63 uint16_t FpgaSendQueueDelay;
64 // the 5 first bits are the number of bits buffered in mod_sig_buf
65 // the last three bits are the remaining ticks/2 after the mod_sig_buf shift
66 #define DELAY_FPGA_QUEUE (FpgaSendQueueDelay<<1)
67
68 // When the PM acts as tag and is sending, it takes
69 // 4*16 ticks until we can write data to the sending hold register
70 // 8*16 ticks until the SHR is transferred to the Sending Shift Register
71 // 8 ticks until the first transfer starts
72 // 8 ticks later the FPGA samples the data
73 // + a varying number of ticks in the FPGA Delay Queue (mod_sig_buf)
74 // + 1 tick to assign mod_sig_coil
75 #define DELAY_ARM2AIR_AS_TAG (4*16 + 8*16 + 8 + 8 + DELAY_FPGA_QUEUE + 1)
76
77 // When the PM acts as sniffer and is receiving tag data, it takes
78 // 3 ticks A/D conversion
79 // 14 ticks to complete the modulation detection
80 // 8 ticks (on average) until the result is stored in to_arm
81 // + the delays in transferring data - which is the same for
82 // sniffing reader and tag data and therefore not relevant
83 #define DELAY_TAG_AIR2ARM_AS_SNIFFER (3 + 14 + 8)
84
85 // When the PM acts as sniffer and is receiving reader data, it takes
86 // 2 ticks delay in analogue RF receiver (for the falling edge of the
87 // start bit, which marks the start of the communication)
88 // 3 ticks A/D conversion
89 // 8 ticks on average until the data is stored in to_arm.
90 // + the delays in transferring data - which is the same for
91 // sniffing reader and tag data and therefore not relevant
92 #define DELAY_READER_AIR2ARM_AS_SNIFFER (2 + 3 + 8)
93
94 //variables used for timing purposes:
95 //these are in ssp_clk cycles:
96 static uint32_t NextTransferTime;
97 static uint32_t LastTimeProxToAirStart;
98 static uint32_t LastProxToAirDuration;
99
100 // CARD TO READER - manchester
101 // Sequence D: 11110000 modulation with subcarrier during first half
102 // Sequence E: 00001111 modulation with subcarrier during second half
103 // Sequence F: 00000000 no modulation with subcarrier
104 // READER TO CARD - miller
105 // Sequence X: 00001100 drop after half a period
106 // Sequence Y: 00000000 no drop
107 // Sequence Z: 11000000 drop at start
108 #define SEC_D 0xf0
109 #define SEC_E 0x0f
110 #define SEC_F 0x00
111 #define SEC_X 0x0c
112 #define SEC_Y 0x00
113 #define SEC_Z 0xc0
114
115 void iso14a_set_trigger(bool enable) {
116 trigger = enable;
117 }
118
119 void iso14a_set_timeout(uint32_t timeout) {
120 iso14a_timeout = timeout;
121 if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443A Timeout set to %ld (%dms)", iso14a_timeout, iso14a_timeout / 106);
122 }
123
124 void iso14a_set_ATS_timeout(uint8_t *ats) {
125 uint8_t tb1;
126 uint8_t fwi;
127 uint32_t fwt;
128
129 if (ats[0] > 1) { // there is a format byte T0
130 if ((ats[1] & 0x20) == 0x20) { // there is an interface byte TB(1)
131
132 if ((ats[1] & 0x10) == 0x10) // there is an interface byte TA(1) preceding TB(1)
133 tb1 = ats[3];
134 else
135 tb1 = ats[2];
136
137 fwi = (tb1 & 0xf0) >> 4; // frame waiting indicator (FWI)
138 fwt = 256 * 16 * (1 << fwi); // frame waiting time (FWT) in 1/fc
139 //fwt = 4096 * (1 << fwi);
140
141 iso14a_set_timeout(fwt/(8*16));
142 //iso14a_set_timeout(fwt/128);
143 }
144 }
145 }
146
147 //-----------------------------------------------------------------------------
148 // Generate the parity value for a byte sequence
149 //
150 //-----------------------------------------------------------------------------
151 void GetParity(const uint8_t *pbtCmd, uint16_t iLen, uint8_t *par) {
152 uint16_t paritybit_cnt = 0;
153 uint16_t paritybyte_cnt = 0;
154 uint8_t parityBits = 0;
155
156 for (uint16_t i = 0; i < iLen; i++) {
157 // Generate the parity bits
158 parityBits |= ((oddparity8(pbtCmd[i])) << (7-paritybit_cnt));
159 if (paritybit_cnt == 7) {
160 par[paritybyte_cnt] = parityBits; // save 8 Bits parity
161 parityBits = 0; // and advance to next Parity Byte
162 paritybyte_cnt++;
163 paritybit_cnt = 0;
164 } else {
165 paritybit_cnt++;
166 }
167 }
168
169 // save remaining parity bits
170 par[paritybyte_cnt] = parityBits;
171 }
172
173 void AppendCrc14443a(uint8_t* data, int len) {
174 ComputeCrc14443(CRC_14443_A,data,len,data+len,data+len+1);
175 }
176
177 //=============================================================================
178 // ISO 14443 Type A - Miller decoder
179 //=============================================================================
180 // Basics:
181 // This decoder is used when the PM3 acts as a tag.
182 // The reader will generate "pauses" by temporarily switching of the field.
183 // At the PM3 antenna we will therefore measure a modulated antenna voltage.
184 // The FPGA does a comparison with a threshold and would deliver e.g.:
185 // ........ 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 .......
186 // The Miller decoder needs to identify the following sequences:
187 // 2 (or 3) ticks pause followed by 6 (or 5) ticks unmodulated: pause at beginning - Sequence Z ("start of communication" or a "0")
188 // 8 ticks without a modulation: no pause - Sequence Y (a "0" or "end of communication" or "no information")
189 // 4 ticks unmodulated followed by 2 (or 3) ticks pause: pause in second half - Sequence X (a "1")
190 // Note 1: the bitstream may start at any time. We therefore need to sync.
191 // Note 2: the interpretation of Sequence Y and Z depends on the preceding sequence.
192 //-----------------------------------------------------------------------------
193 static tUart Uart;
194
195 // Lookup-Table to decide if 4 raw bits are a modulation.
196 // We accept the following:
197 // 0001 - a 3 tick wide pause
198 // 0011 - a 2 tick wide pause, or a three tick wide pause shifted left
199 // 0111 - a 2 tick wide pause shifted left
200 // 1001 - a 2 tick wide pause shifted right
201 const bool Mod_Miller_LUT[] = {
202 FALSE, TRUE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE,
203 FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE
204 };
205 #define IsMillerModulationNibble1(b) (Mod_Miller_LUT[(b & 0x000000F0) >> 4])
206 #define IsMillerModulationNibble2(b) (Mod_Miller_LUT[(b & 0x0000000F)])
207
208 void UartReset() {
209 Uart.state = STATE_UNSYNCD;
210 Uart.bitCount = 0;
211 Uart.len = 0; // number of decoded data bytes
212 Uart.parityLen = 0; // number of decoded parity bytes
213 Uart.shiftReg = 0; // shiftreg to hold decoded data bits
214 Uart.parityBits = 0; // holds 8 parity bits
215 Uart.startTime = 0;
216 Uart.endTime = 0;
217
218 Uart.byteCntMax = 0;
219 Uart.posCnt = 0;
220 Uart.syncBit = 9999;
221 }
222
223 void UartInit(uint8_t *data, uint8_t *parity) {
224 Uart.output = data;
225 Uart.parity = parity;
226 Uart.fourBits = 0x00000000; // clear the buffer for 4 Bits
227 UartReset();
228 }
229
230 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
231 static RAMFUNC bool MillerDecoding(uint8_t bit, uint32_t non_real_time) {
232 Uart.fourBits = (Uart.fourBits << 8) | bit;
233
234 if (Uart.state == STATE_UNSYNCD) { // not yet synced
235 Uart.syncBit = 9999; // not set
236
237 // 00x11111 2|3 ticks pause followed by 6|5 ticks unmodulated Sequence Z (a "0" or "start of communication")
238 // 11111111 8 ticks unmodulation Sequence Y (a "0" or "end of communication" or "no information")
239 // 111100x1 4 ticks unmodulated followed by 2|3 ticks pause Sequence X (a "1")
240
241 // The start bit is one ore more Sequence Y followed by a Sequence Z (... 11111111 00x11111). We need to distinguish from
242 // Sequence X followed by Sequence Y followed by Sequence Z (111100x1 11111111 00x11111)
243 // we therefore look for a ...xx1111 11111111 00x11111xxxxxx... pattern
244 // (12 '1's followed by 2 '0's, eventually followed by another '0', followed by 5 '1's)
245 //
246 #define ISO14443A_STARTBIT_MASK 0x07FFEF80 // mask is 00001111 11111111 1110 1111 10000000
247 #define ISO14443A_STARTBIT_PATTERN 0x07FF8F80 // pattern is 00001111 11111111 1000 1111 10000000
248
249 if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 0)) == ISO14443A_STARTBIT_PATTERN >> 0) Uart.syncBit = 7;
250 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 1)) == ISO14443A_STARTBIT_PATTERN >> 1) Uart.syncBit = 6;
251 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 2)) == ISO14443A_STARTBIT_PATTERN >> 2) Uart.syncBit = 5;
252 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 3)) == ISO14443A_STARTBIT_PATTERN >> 3) Uart.syncBit = 4;
253 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 4)) == ISO14443A_STARTBIT_PATTERN >> 4) Uart.syncBit = 3;
254 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 5)) == ISO14443A_STARTBIT_PATTERN >> 5) Uart.syncBit = 2;
255 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 6)) == ISO14443A_STARTBIT_PATTERN >> 6) Uart.syncBit = 1;
256 else if ((Uart.fourBits & (ISO14443A_STARTBIT_MASK >> 7)) == ISO14443A_STARTBIT_PATTERN >> 7) Uart.syncBit = 0;
257
258 if (Uart.syncBit != 9999) { // found a sync bit
259 Uart.startTime = non_real_time ? non_real_time : (GetCountSspClk() & 0xfffffff8);
260 Uart.startTime -= Uart.syncBit;
261 Uart.endTime = Uart.startTime;
262 Uart.state = STATE_START_OF_COMMUNICATION;
263 }
264 } else {
265
266 if (IsMillerModulationNibble1(Uart.fourBits >> Uart.syncBit)) {
267 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation in both halves - error
268 UartReset();
269 } else { // Modulation in first half = Sequence Z = logic "0"
270 if (Uart.state == STATE_MILLER_X) { // error - must not follow after X
271 UartReset();
272 } else {
273 Uart.bitCount++;
274 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
275 Uart.state = STATE_MILLER_Z;
276 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 6;
277 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
278 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
279 Uart.parityBits <<= 1; // make room for the parity bit
280 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
281 Uart.bitCount = 0;
282 Uart.shiftReg = 0;
283 if((Uart.len&0x0007) == 0) { // every 8 data bytes
284 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
285 Uart.parityBits = 0;
286 }
287 }
288 }
289 }
290 } else {
291 if (IsMillerModulationNibble2(Uart.fourBits >> Uart.syncBit)) { // Modulation second half = Sequence X = logic "1"
292 Uart.bitCount++;
293 Uart.shiftReg = (Uart.shiftReg >> 1) | 0x100; // add a 1 to the shiftreg
294 Uart.state = STATE_MILLER_X;
295 Uart.endTime = Uart.startTime + 8*(9*Uart.len + Uart.bitCount + 1) - 2;
296 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
297 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
298 Uart.parityBits <<= 1; // make room for the new parity bit
299 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
300 Uart.bitCount = 0;
301 Uart.shiftReg = 0;
302 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
303 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
304 Uart.parityBits = 0;
305 }
306 }
307 } else { // no modulation in both halves - Sequence Y
308 if (Uart.state == STATE_MILLER_Z || Uart.state == STATE_MILLER_Y) { // Y after logic "0" - End of Communication
309 Uart.state = STATE_UNSYNCD;
310 Uart.bitCount--; // last "0" was part of EOC sequence
311 Uart.shiftReg <<= 1; // drop it
312 if(Uart.bitCount > 0) { // if we decoded some bits
313 Uart.shiftReg >>= (9 - Uart.bitCount); // right align them
314 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff); // add last byte to the output
315 Uart.parityBits <<= 1; // add a (void) parity bit
316 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align parity bits
317 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store it
318 return TRUE;
319 } else if (Uart.len & 0x0007) { // there are some parity bits to store
320 Uart.parityBits <<= (8 - (Uart.len&0x0007)); // left align remaining parity bits
321 Uart.parity[Uart.parityLen++] = Uart.parityBits; // and store them
322 }
323 if (Uart.len) {
324 return TRUE; // we are finished with decoding the raw data sequence
325 } else {
326 UartReset(); // Nothing received - start over
327 }
328 }
329 if (Uart.state == STATE_START_OF_COMMUNICATION) { // error - must not follow directly after SOC
330 UartReset();
331 } else { // a logic "0"
332 Uart.bitCount++;
333 Uart.shiftReg = (Uart.shiftReg >> 1); // add a 0 to the shiftreg
334 Uart.state = STATE_MILLER_Y;
335 if(Uart.bitCount >= 9) { // if we decoded a full byte (including parity)
336 Uart.output[Uart.len++] = (Uart.shiftReg & 0xff);
337 Uart.parityBits <<= 1; // make room for the parity bit
338 Uart.parityBits |= ((Uart.shiftReg >> 8) & 0x01); // store parity bit
339 Uart.bitCount = 0;
340 Uart.shiftReg = 0;
341 if ((Uart.len&0x0007) == 0) { // every 8 data bytes
342 Uart.parity[Uart.parityLen++] = Uart.parityBits; // store 8 parity bits
343 Uart.parityBits = 0;
344 }
345 }
346 }
347 }
348 }
349 }
350 return FALSE; // not finished yet, need more data
351 }
352
353 //=============================================================================
354 // ISO 14443 Type A - Manchester decoder
355 //=============================================================================
356 // Basics:
357 // This decoder is used when the PM3 acts as a reader.
358 // The tag will modulate the reader field by asserting different loads to it. As a consequence, the voltage
359 // at the reader antenna will be modulated as well. The FPGA detects the modulation for us and would deliver e.g. the following:
360 // ........ 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 .......
361 // The Manchester decoder needs to identify the following sequences:
362 // 4 ticks modulated followed by 4 ticks unmodulated: Sequence D = 1 (also used as "start of communication")
363 // 4 ticks unmodulated followed by 4 ticks modulated: Sequence E = 0
364 // 8 ticks unmodulated: Sequence F = end of communication
365 // 8 ticks modulated: A collision. Save the collision position and treat as Sequence D
366 // Note 1: the bitstream may start at any time. We therefore need to sync.
367 // Note 2: parameter offset is used to determine the position of the parity bits (required for the anticollision command only)
368 static tDemod Demod;
369
370 // Lookup-Table to decide if 4 raw bits are a modulation.
371 // We accept three or four "1" in any position
372 const bool Mod_Manchester_LUT[] = {
373 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE,
374 FALSE, FALSE, FALSE, TRUE, FALSE, TRUE, TRUE, TRUE
375 };
376
377 #define IsManchesterModulationNibble1(b) (Mod_Manchester_LUT[(b & 0x00F0) >> 4])
378 #define IsManchesterModulationNibble2(b) (Mod_Manchester_LUT[(b & 0x000F)])
379
380 void DemodReset() {
381 Demod.state = DEMOD_UNSYNCD;
382 Demod.len = 0; // number of decoded data bytes
383 Demod.parityLen = 0;
384 Demod.shiftReg = 0; // shiftreg to hold decoded data bits
385 Demod.parityBits = 0; //
386 Demod.collisionPos = 0; // Position of collision bit
387 Demod.twoBits = 0xffff; // buffer for 2 Bits
388 Demod.highCnt = 0;
389 Demod.startTime = 0;
390 Demod.endTime = 0;
391 Demod.bitCount = 0;
392 Demod.syncBit = 0xFFFF;
393 Demod.samples = 0;
394 }
395
396 void DemodInit(uint8_t *data, uint8_t *parity) {
397 Demod.output = data;
398 Demod.parity = parity;
399 DemodReset();
400 }
401
402 // use parameter non_real_time to provide a timestamp. Set to 0 if the decoder should measure real time
403 static RAMFUNC int ManchesterDecoding(uint8_t bit, uint16_t offset, uint32_t non_real_time) {
404 Demod.twoBits = (Demod.twoBits << 8) | bit;
405
406 if (Demod.state == DEMOD_UNSYNCD) {
407
408 if (Demod.highCnt < 2) { // wait for a stable unmodulated signal
409 if (Demod.twoBits == 0x0000) {
410 Demod.highCnt++;
411 } else {
412 Demod.highCnt = 0;
413 }
414 } else {
415 Demod.syncBit = 0xFFFF; // not set
416 if ((Demod.twoBits & 0x7700) == 0x7000) Demod.syncBit = 7;
417 else if ((Demod.twoBits & 0x3B80) == 0x3800) Demod.syncBit = 6;
418 else if ((Demod.twoBits & 0x1DC0) == 0x1C00) Demod.syncBit = 5;
419 else if ((Demod.twoBits & 0x0EE0) == 0x0E00) Demod.syncBit = 4;
420 else if ((Demod.twoBits & 0x0770) == 0x0700) Demod.syncBit = 3;
421 else if ((Demod.twoBits & 0x03B8) == 0x0380) Demod.syncBit = 2;
422 else if ((Demod.twoBits & 0x01DC) == 0x01C0) Demod.syncBit = 1;
423 else if ((Demod.twoBits & 0x00EE) == 0x00E0) Demod.syncBit = 0;
424 if (Demod.syncBit != 0xFFFF) {
425 Demod.startTime = non_real_time?non_real_time:(GetCountSspClk() & 0xfffffff8);
426 Demod.startTime -= Demod.syncBit;
427 Demod.bitCount = offset; // number of decoded data bits
428 Demod.state = DEMOD_MANCHESTER_DATA;
429 }
430 }
431 } else {
432
433 if (IsManchesterModulationNibble1(Demod.twoBits >> Demod.syncBit)) { // modulation in first half
434 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // ... and in second half = collision
435 if (!Demod.collisionPos) {
436 Demod.collisionPos = (Demod.len << 3) + Demod.bitCount;
437 }
438 } // modulation in first half only - Sequence D = 1
439 Demod.bitCount++;
440 Demod.shiftReg = (Demod.shiftReg >> 1) | 0x100; // in both cases, add a 1 to the shiftreg
441 if(Demod.bitCount == 9) { // if we decoded a full byte (including parity)
442 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
443 Demod.parityBits <<= 1; // make room for the parity bit
444 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
445 Demod.bitCount = 0;
446 Demod.shiftReg = 0;
447 if((Demod.len&0x0007) == 0) { // every 8 data bytes
448 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits
449 Demod.parityBits = 0;
450 }
451 }
452 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1) - 4;
453 } else { // no modulation in first half
454 if (IsManchesterModulationNibble2(Demod.twoBits >> Demod.syncBit)) { // and modulation in second half = Sequence E = 0
455 Demod.bitCount++;
456 Demod.shiftReg = (Demod.shiftReg >> 1); // add a 0 to the shiftreg
457 if(Demod.bitCount >= 9) { // if we decoded a full byte (including parity)
458 Demod.output[Demod.len++] = (Demod.shiftReg & 0xff);
459 Demod.parityBits <<= 1; // make room for the new parity bit
460 Demod.parityBits |= ((Demod.shiftReg >> 8) & 0x01); // store parity bit
461 Demod.bitCount = 0;
462 Demod.shiftReg = 0;
463 if ((Demod.len&0x0007) == 0) { // every 8 data bytes
464 Demod.parity[Demod.parityLen++] = Demod.parityBits; // store 8 parity bits1
465 Demod.parityBits = 0;
466 }
467 }
468 Demod.endTime = Demod.startTime + 8*(9*Demod.len + Demod.bitCount + 1);
469 } else { // no modulation in both halves - End of communication
470 if(Demod.bitCount > 0) { // there are some remaining data bits
471 Demod.shiftReg >>= (9 - Demod.bitCount); // right align the decoded bits
472 Demod.output[Demod.len++] = Demod.shiftReg & 0xff; // and add them to the output
473 Demod.parityBits <<= 1; // add a (void) parity bit
474 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
475 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
476 return TRUE;
477 } else if (Demod.len & 0x0007) { // there are some parity bits to store
478 Demod.parityBits <<= (8 - (Demod.len&0x0007)); // left align remaining parity bits
479 Demod.parity[Demod.parityLen++] = Demod.parityBits; // and store them
480 }
481 if (Demod.len) {
482 return TRUE; // we are finished with decoding the raw data sequence
483 } else { // nothing received. Start over
484 DemodReset();
485 }
486 }
487 }
488 }
489 return FALSE; // not finished yet, need more data
490 }
491
492 //=============================================================================
493 // Finally, a `sniffer' for ISO 14443 Type A
494 // Both sides of communication!
495 //=============================================================================
496
497 //-----------------------------------------------------------------------------
498 // Record the sequence of commands sent by the reader to the tag, with
499 // triggering so that we start recording at the point that the tag is moved
500 // near the reader.
501 // "hf 14a sniff"
502 //-----------------------------------------------------------------------------
503 void RAMFUNC SniffIso14443a(uint8_t param) {
504 // param:
505 // bit 0 - trigger from first card answer
506 // bit 1 - trigger from first reader 7-bit request
507 LEDsoff();
508
509 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
510
511 // Allocate memory from BigBuf for some buffers
512 // free all previous allocations first
513 BigBuf_free(); BigBuf_Clear_ext(false);
514 clear_trace();
515 set_tracing(TRUE);
516
517 // The command (reader -> tag) that we're receiving.
518 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
519 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
520
521 // The response (tag -> reader) that we're receiving.
522 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
523 uint8_t *receivedResponsePar = BigBuf_malloc(MAX_PARITY_SIZE);
524
525 // The DMA buffer, used to stream samples from the FPGA
526 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
527
528 uint8_t *data = dmaBuf;
529 uint8_t previous_data = 0;
530 int maxDataLen = 0;
531 int dataLen = 0;
532 bool TagIsActive = FALSE;
533 bool ReaderIsActive = FALSE;
534
535 // Set up the demodulator for tag -> reader responses.
536 DemodInit(receivedResponse, receivedResponsePar);
537
538 // Set up the demodulator for the reader -> tag commands
539 UartInit(receivedCmd, receivedCmdPar);
540
541 // Setup and start DMA.
542 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
543 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
544 return;
545 }
546
547 // We won't start recording the frames that we acquire until we trigger;
548 // a good trigger condition to get started is probably when we see a
549 // response from the tag.
550 // triggered == FALSE -- to wait first for card
551 bool triggered = !(param & 0x03);
552
553 // And now we loop, receiving samples.
554 for(uint32_t rsamples = 0; TRUE; ) {
555
556 if(BUTTON_PRESS()) {
557 DbpString("cancelled by button");
558 break;
559 }
560
561 LED_A_ON();
562 WDT_HIT();
563
564 int register readBufDataP = data - dmaBuf;
565 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR;
566 if (readBufDataP <= dmaBufDataP){
567 dataLen = dmaBufDataP - readBufDataP;
568 } else {
569 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP;
570 }
571 // test for length of buffer
572 if(dataLen > maxDataLen) {
573 maxDataLen = dataLen;
574 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
575 Dbprintf("blew circular buffer! dataLen=%d", dataLen);
576 break;
577 }
578 }
579 if(dataLen < 1) continue;
580
581 // primary buffer was stopped( <-- we lost data!
582 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
583 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
584 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
585 Dbprintf("RxEmpty ERROR!!! data length:%d", dataLen); // temporary
586 }
587 // secondary buffer sets as primary, secondary buffer was stopped
588 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
589 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
590 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
591 }
592
593 LED_A_OFF();
594
595 if (rsamples & 0x01) { // Need two samples to feed Miller and Manchester-Decoder
596
597 if(!TagIsActive) { // no need to try decoding reader data if the tag is sending
598 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
599 if (MillerDecoding(readerdata, (rsamples-1)*4)) {
600 LED_C_ON();
601
602 // check - if there is a short 7bit request from reader
603 if ((!triggered) && (param & 0x02) && (Uart.len == 1) && (Uart.bitCount == 7)) triggered = TRUE;
604
605 if(triggered) {
606 if (!LogTrace(receivedCmd,
607 Uart.len,
608 Uart.startTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
609 Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER,
610 Uart.parity,
611 TRUE)) break;
612 }
613 /* And ready to receive another command. */
614 UartReset();
615 /* And also reset the demod code, which might have been */
616 /* false-triggered by the commands from the reader. */
617 DemodReset();
618 LED_B_OFF();
619 }
620 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
621 }
622
623 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
624 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
625 if(ManchesterDecoding(tagdata, 0, (rsamples-1)*4)) {
626 LED_B_ON();
627
628 if (!LogTrace(receivedResponse,
629 Demod.len,
630 Demod.startTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
631 Demod.endTime*16 - DELAY_TAG_AIR2ARM_AS_SNIFFER,
632 Demod.parity,
633 FALSE)) break;
634
635 if ((!triggered) && (param & 0x01)) triggered = TRUE;
636
637 // And ready to receive another response.
638 DemodReset();
639 // And reset the Miller decoder including itS (now outdated) input buffer
640 UartInit(receivedCmd, receivedCmdPar);
641 LED_C_OFF();
642 }
643 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
644 }
645 }
646
647 previous_data = *data;
648 rsamples++;
649 data++;
650 if(data == dmaBuf + DMA_BUFFER_SIZE) {
651 data = dmaBuf;
652 }
653 } // main cycle
654
655 if (MF_DBGLEVEL >= 1) {
656 Dbprintf("maxDataLen=%d, Uart.state=%x, Uart.len=%d", maxDataLen, Uart.state, Uart.len);
657 Dbprintf("traceLen=%d, Uart.output[0]=%08x", BigBuf_get_traceLen(), (uint32_t)Uart.output[0]);
658 }
659 FpgaDisableSscDma();
660 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
661 LEDsoff();
662 set_tracing(FALSE);
663 }
664
665 //-----------------------------------------------------------------------------
666 // Prepare tag messages
667 //-----------------------------------------------------------------------------
668 static void CodeIso14443aAsTagPar(const uint8_t *cmd, uint16_t len, uint8_t *parity) {
669 ToSendReset();
670
671 // Correction bit, might be removed when not needed
672 ToSendStuffBit(0);
673 ToSendStuffBit(0);
674 ToSendStuffBit(0);
675 ToSendStuffBit(0);
676 ToSendStuffBit(1); // 1
677 ToSendStuffBit(0);
678 ToSendStuffBit(0);
679 ToSendStuffBit(0);
680
681 // Send startbit
682 ToSend[++ToSendMax] = SEC_D;
683 LastProxToAirDuration = 8 * ToSendMax - 4;
684
685 for(uint16_t i = 0; i < len; i++) {
686 uint8_t b = cmd[i];
687
688 // Data bits
689 for(uint16_t j = 0; j < 8; j++) {
690 if(b & 1) {
691 ToSend[++ToSendMax] = SEC_D;
692 } else {
693 ToSend[++ToSendMax] = SEC_E;
694 }
695 b >>= 1;
696 }
697
698 // Get the parity bit
699 if (parity[i>>3] & (0x80>>(i&0x0007))) {
700 ToSend[++ToSendMax] = SEC_D;
701 LastProxToAirDuration = 8 * ToSendMax - 4;
702 } else {
703 ToSend[++ToSendMax] = SEC_E;
704 LastProxToAirDuration = 8 * ToSendMax;
705 }
706 }
707
708 // Send stopbit
709 ToSend[++ToSendMax] = SEC_F;
710
711 // Convert from last byte pos to length
712 ++ToSendMax;
713 }
714
715 static void CodeIso14443aAsTag(const uint8_t *cmd, uint16_t len) {
716 uint8_t par[MAX_PARITY_SIZE] = {0};
717 GetParity(cmd, len, par);
718 CodeIso14443aAsTagPar(cmd, len, par);
719 }
720
721 static void Code4bitAnswerAsTag(uint8_t cmd) {
722 uint8_t b = cmd;
723
724 ToSendReset();
725
726 // Correction bit, might be removed when not needed
727 ToSendStuffBit(0);
728 ToSendStuffBit(0);
729 ToSendStuffBit(0);
730 ToSendStuffBit(0);
731 ToSendStuffBit(1); // 1
732 ToSendStuffBit(0);
733 ToSendStuffBit(0);
734 ToSendStuffBit(0);
735
736 // Send startbit
737 ToSend[++ToSendMax] = SEC_D;
738
739 for(uint8_t i = 0; i < 4; i++) {
740 if(b & 1) {
741 ToSend[++ToSendMax] = SEC_D;
742 LastProxToAirDuration = 8 * ToSendMax - 4;
743 } else {
744 ToSend[++ToSendMax] = SEC_E;
745 LastProxToAirDuration = 8 * ToSendMax;
746 }
747 b >>= 1;
748 }
749
750 // Send stopbit
751 ToSend[++ToSendMax] = SEC_F;
752
753 // Convert from last byte pos to length
754 ToSendMax++;
755 }
756
757 //-----------------------------------------------------------------------------
758 // Wait for commands from reader
759 // Stop when button is pressed
760 // Or return TRUE when command is captured
761 //-----------------------------------------------------------------------------
762 int GetIso14443aCommandFromReader(uint8_t *received, uint8_t *parity, int *len) {
763 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
764 // only, since we are receiving, not transmitting).
765 // Signal field is off with the appropriate LED
766 LED_D_OFF();
767 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
768
769 // Now run a `software UART` on the stream of incoming samples.
770 UartInit(received, parity);
771
772 // clear RXRDY:
773 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
774
775 for(;;) {
776 WDT_HIT();
777
778 if(BUTTON_PRESS()) return FALSE;
779
780 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
781 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
782 if(MillerDecoding(b, 0)) {
783 *len = Uart.len;
784 return TRUE;
785 }
786 }
787 }
788 }
789
790 bool prepare_tag_modulation(tag_response_info_t* response_info, size_t max_buffer_size) {
791 // Example response, answer to MIFARE Classic read block will be 16 bytes + 2 CRC = 18 bytes
792 // This will need the following byte array for a modulation sequence
793 // 144 data bits (18 * 8)
794 // 18 parity bits
795 // 2 Start and stop
796 // 1 Correction bit (Answer in 1172 or 1236 periods, see FPGA)
797 // 1 just for the case
798 // ----------- +
799 // 166 bytes, since every bit that needs to be send costs us a byte
800 //
801 // Prepare the tag modulation bits from the message
802 CodeIso14443aAsTag(response_info->response,response_info->response_n);
803
804 // Make sure we do not exceed the free buffer space
805 if (ToSendMax > max_buffer_size) {
806 Dbprintf("Out of memory, when modulating bits for tag answer:");
807 Dbhexdump(response_info->response_n,response_info->response,false);
808 return FALSE;
809 }
810
811 // Copy the byte array, used for this modulation to the buffer position
812 memcpy(response_info->modulation,ToSend,ToSendMax);
813
814 // Store the number of bytes that were used for encoding/modulation and the time needed to transfer them
815 response_info->modulation_n = ToSendMax;
816 response_info->ProxToAirDuration = LastProxToAirDuration;
817 return TRUE;
818 }
819
820 // "precompile" responses. There are 7 predefined responses with a total of 28 bytes data to transmit.
821 // Coded responses need one byte per bit to transfer (data, parity, start, stop, correction)
822 // 28 * 8 data bits, 28 * 1 parity bits, 7 start bits, 7 stop bits, 7 correction bits
823 // -> need 273 bytes buffer
824 // 44 * 8 data bits, 44 * 1 parity bits, 9 start bits, 9 stop bits, 9 correction bits --370
825 // 47 * 8 data bits, 47 * 1 parity bits, 10 start bits, 10 stop bits, 10 correction bits
826 #define ALLOCATED_TAG_MODULATION_BUFFER_SIZE 453
827
828 bool prepare_allocated_tag_modulation(tag_response_info_t* response_info) {
829 // Retrieve and store the current buffer index
830 response_info->modulation = free_buffer_pointer;
831
832 // Determine the maximum size we can use from our buffer
833 size_t max_buffer_size = ALLOCATED_TAG_MODULATION_BUFFER_SIZE;
834
835 // Forward the prepare tag modulation function to the inner function
836 if (prepare_tag_modulation(response_info, max_buffer_size)) {
837 // Update the free buffer offset
838 free_buffer_pointer += ToSendMax;
839 return true;
840 } else {
841 return false;
842 }
843 }
844
845 //-----------------------------------------------------------------------------
846 // Main loop of simulated tag: receive commands from reader, decide what
847 // response to send, and send it.
848 // 'hf 14a sim'
849 //-----------------------------------------------------------------------------
850 void SimulateIso14443aTag(int tagType, int flags, byte_t* data) {
851
852 #define ATTACK_KEY_COUNT 8 // keep same as define in cmdhfmf.c -> readerAttack()
853 // init pseudorand
854 fast_prand();
855
856 uint8_t sak = 0;
857 uint32_t cuid = 0;
858 uint32_t nonce = 0;
859
860 // PACK response to PWD AUTH for EV1/NTAG
861 uint8_t response8[4] = {0,0,0,0};
862 // Counter for EV1/NTAG
863 uint32_t counters[] = {0,0,0};
864
865 // The first response contains the ATQA (note: bytes are transmitted in reverse order).
866 uint8_t response1[] = {0,0};
867
868 // Here, we collect CUID, block1, keytype1, NT1, NR1, AR1, CUID, block2, keytyp2, NT2, NR2, AR2
869 // it should also collect block, keytype.
870 uint8_t cardAUTHSC = 0;
871 uint8_t cardAUTHKEY = 0xff; // no authentication
872 // allow collecting up to 8 sets of nonces to allow recovery of up to 8 keys
873
874 nonces_t ar_nr_nonces[ATTACK_KEY_COUNT]; // for attack types moebius
875 memset(ar_nr_nonces, 0x00, sizeof(ar_nr_nonces));
876 uint8_t moebius_count = 0;
877
878 switch (tagType) {
879 case 1: { // MIFARE Classic 1k
880 response1[0] = 0x04;
881 sak = 0x08;
882 } break;
883 case 2: { // MIFARE Ultralight
884 response1[0] = 0x44;
885 sak = 0x00;
886 } break;
887 case 3: { // MIFARE DESFire
888 response1[0] = 0x04;
889 response1[1] = 0x03;
890 sak = 0x20;
891 } break;
892 case 4: { // ISO/IEC 14443-4 - javacard (JCOP)
893 response1[0] = 0x04;
894 sak = 0x28;
895 } break;
896 case 5: { // MIFARE TNP3XXX
897 response1[0] = 0x01;
898 response1[1] = 0x0f;
899 sak = 0x01;
900 } break;
901 case 6: { // MIFARE Mini 320b
902 response1[0] = 0x44;
903 sak = 0x09;
904 } break;
905 case 7: { // NTAG
906 response1[0] = 0x44;
907 sak = 0x00;
908 // PACK
909 response8[0] = 0x80;
910 response8[1] = 0x80;
911 ComputeCrc14443(CRC_14443_A, response8, 2, &response8[2], &response8[3]);
912 // uid not supplied then get from emulator memory
913 if (data[0]==0) {
914 uint16_t start = 4 * (0+12);
915 uint8_t emdata[8];
916 emlGetMemBt( emdata, start, sizeof(emdata));
917 memcpy(data, emdata, 3); // uid bytes 0-2
918 memcpy(data+3, emdata+4, 4); // uid bytes 3-7
919 flags |= FLAG_7B_UID_IN_DATA;
920 }
921 } break;
922 case 8: { // MIFARE Classic 4k
923 response1[0] = 0x02;
924 sak = 0x18;
925 } break;
926 default: {
927 Dbprintf("Error: unkown tagtype (%d)",tagType);
928 return;
929 } break;
930 }
931
932 // The second response contains the (mandatory) first 24 bits of the UID
933 uint8_t response2[5] = {0x00};
934
935 // For UID size 7,
936 uint8_t response2a[5] = {0x00};
937
938 if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA ) {
939 response2[0] = 0x88; // Cascade Tag marker
940 response2[1] = data[0];
941 response2[2] = data[1];
942 response2[3] = data[2];
943
944 response2a[0] = data[3];
945 response2a[1] = data[4];
946 response2a[2] = data[5];
947 response2a[3] = data[6]; //??
948 response2a[4] = response2a[0] ^ response2a[1] ^ response2a[2] ^ response2a[3];
949
950 // Configure the ATQA and SAK accordingly
951 response1[0] |= 0x40;
952 sak |= 0x04;
953
954 cuid = bytes_to_num(data+3, 4);
955 } else {
956 memcpy(response2, data, 4);
957 // Configure the ATQA and SAK accordingly
958 response1[0] &= 0xBF;
959 sak &= 0xFB;
960 cuid = bytes_to_num(data, 4);
961 }
962
963 // Calculate the BitCountCheck (BCC) for the first 4 bytes of the UID.
964 response2[4] = response2[0] ^ response2[1] ^ response2[2] ^ response2[3];
965
966 // Prepare the mandatory SAK (for 4 and 7 byte UID)
967 uint8_t response3[3] = {sak, 0x00, 0x00};
968 ComputeCrc14443(CRC_14443_A, response3, 1, &response3[1], &response3[2]);
969
970 // Prepare the optional second SAK (for 7 byte UID), drop the cascade bit
971 uint8_t response3a[3] = {0x00};
972 response3a[0] = sak & 0xFB;
973 ComputeCrc14443(CRC_14443_A, response3a, 1, &response3a[1], &response3a[2]);
974
975 // Tag NONCE.
976 uint8_t response5[4];
977
978 uint8_t response6[] = { 0x04, 0x58, 0x80, 0x02, 0x00, 0x00 }; // dummy ATS (pseudo-ATR), answer to RATS:
979 // Format byte = 0x58: FSCI=0x08 (FSC=256), TA(1) and TC(1) present,
980 // TA(1) = 0x80: different divisors not supported, DR = 1, DS = 1
981 // TB(1) = not present. Defaults: FWI = 4 (FWT = 256 * 16 * 2^4 * 1/fc = 4833us), SFGI = 0 (SFG = 256 * 16 * 2^0 * 1/fc = 302us)
982 // TC(1) = 0x02: CID supported, NAD not supported
983 ComputeCrc14443(CRC_14443_A, response6, 4, &response6[4], &response6[5]);
984
985 // Prepare GET_VERSION (different for UL EV-1 / NTAG)
986 // uint8_t response7_EV1[] = {0x00, 0x04, 0x03, 0x01, 0x01, 0x00, 0x0b, 0x03, 0xfd, 0xf7}; //EV1 48bytes VERSION.
987 // uint8_t response7_NTAG[] = {0x00, 0x04, 0x04, 0x02, 0x01, 0x00, 0x11, 0x03, 0x01, 0x9e}; //NTAG 215
988 // Prepare CHK_TEARING
989 // uint8_t response9[] = {0xBD,0x90,0x3f};
990
991 #define TAG_RESPONSE_COUNT 10
992 tag_response_info_t responses[TAG_RESPONSE_COUNT] = {
993 { .response = response1, .response_n = sizeof(response1) }, // Answer to request - respond with card type
994 { .response = response2, .response_n = sizeof(response2) }, // Anticollision cascade1 - respond with uid
995 { .response = response2a, .response_n = sizeof(response2a) }, // Anticollision cascade2 - respond with 2nd half of uid if asked
996 { .response = response3, .response_n = sizeof(response3) }, // Acknowledge select - cascade 1
997 { .response = response3a, .response_n = sizeof(response3a) }, // Acknowledge select - cascade 2
998 { .response = response5, .response_n = sizeof(response5) }, // Authentication answer (random nonce)
999 { .response = response6, .response_n = sizeof(response6) }, // dummy ATS (pseudo-ATR), answer to RATS
1000
1001 { .response = response8, .response_n = sizeof(response8) } // EV1/NTAG PACK response
1002 };
1003 // { .response = response7_NTAG, .response_n = sizeof(response7_NTAG)}, // EV1/NTAG GET_VERSION response
1004 // { .response = response9, .response_n = sizeof(response9) } // EV1/NTAG CHK_TEAR response
1005
1006
1007 // Allocate 512 bytes for the dynamic modulation, created when the reader queries for it
1008 // Such a response is less time critical, so we can prepare them on the fly
1009 #define DYNAMIC_RESPONSE_BUFFER_SIZE 64
1010 #define DYNAMIC_MODULATION_BUFFER_SIZE 512
1011 uint8_t dynamic_response_buffer[DYNAMIC_RESPONSE_BUFFER_SIZE];
1012 uint8_t dynamic_modulation_buffer[DYNAMIC_MODULATION_BUFFER_SIZE];
1013 tag_response_info_t dynamic_response_info = {
1014 .response = dynamic_response_buffer,
1015 .response_n = 0,
1016 .modulation = dynamic_modulation_buffer,
1017 .modulation_n = 0
1018 };
1019
1020 // We need to listen to the high-frequency, peak-detected path.
1021 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1022
1023 BigBuf_free_keep_EM();
1024 clear_trace();
1025 set_tracing(TRUE);
1026
1027 // allocate buffers:
1028 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
1029 uint8_t *receivedCmdPar = BigBuf_malloc(MAX_PARITY_SIZE);
1030 free_buffer_pointer = BigBuf_malloc(ALLOCATED_TAG_MODULATION_BUFFER_SIZE);
1031
1032 // Prepare the responses of the anticollision phase
1033 // there will be not enough time to do this at the moment the reader sends it REQA
1034 for (size_t i=0; i<TAG_RESPONSE_COUNT; i++)
1035 prepare_allocated_tag_modulation(&responses[i]);
1036
1037 int len = 0;
1038
1039 // To control where we are in the protocol
1040 int order = 0;
1041 int lastorder;
1042
1043 // Just to allow some checks
1044 int happened = 0;
1045 int happened2 = 0;
1046 int cmdsRecvd = 0;
1047 tag_response_info_t* p_response;
1048
1049 LED_A_ON();
1050 for(;;) {
1051 WDT_HIT();
1052
1053 // Clean receive command buffer
1054 if(!GetIso14443aCommandFromReader(receivedCmd, receivedCmdPar, &len)) {
1055 Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
1056 break;
1057 }
1058 p_response = NULL;
1059
1060 // Okay, look at the command now.
1061 lastorder = order;
1062 if(receivedCmd[0] == ISO14443A_CMD_REQA) { // Received a REQUEST
1063 p_response = &responses[0]; order = 1;
1064 } else if(receivedCmd[0] == ISO14443A_CMD_WUPA) { // Received a WAKEUP
1065 p_response = &responses[0]; order = 6;
1066 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received request for UID (cascade 1)
1067 p_response = &responses[1]; order = 2;
1068 } else if(receivedCmd[1] == 0x20 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received request for UID (cascade 2)
1069 p_response = &responses[2]; order = 20;
1070 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT) { // Received a SELECT (cascade 1)
1071 p_response = &responses[3]; order = 3;
1072 } else if(receivedCmd[1] == 0x70 && receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2) { // Received a SELECT (cascade 2)
1073 p_response = &responses[4]; order = 30;
1074 } else if(receivedCmd[0] == ISO14443A_CMD_READBLOCK) { // Received a (plain) READ
1075 uint8_t block = receivedCmd[1];
1076 // if Ultralight or NTAG (4 byte blocks)
1077 if ( tagType == 7 || tagType == 2 ) {
1078 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1079 uint16_t start = 4 * (block+12);
1080 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1081 emlGetMemBt( emdata, start, 16);
1082 AppendCrc14443a(emdata, 16);
1083 EmSendCmdEx(emdata, sizeof(emdata), false);
1084 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1085 p_response = NULL;
1086 } else { // all other tags (16 byte block tags)
1087 uint8_t emdata[MAX_MIFARE_FRAME_SIZE];
1088 emlGetMemBt( emdata, block, 16);
1089 AppendCrc14443a(emdata, 16);
1090 EmSendCmdEx(emdata, sizeof(emdata), false);
1091 // EmSendCmdEx(data+(4*receivedCmd[1]),16,false);
1092 // Dbprintf("Read request from reader: %x %x",receivedCmd[0],receivedCmd[1]);
1093 // We already responded, do not send anything with the EmSendCmd14443aRaw() that is called below
1094 p_response = NULL;
1095 }
1096 } else if(receivedCmd[0] == MIFARE_ULEV1_FASTREAD) { // Received a FAST READ (ranged read)
1097 uint8_t emdata[MAX_FRAME_SIZE];
1098 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1099 int start = (receivedCmd[1]+12) * 4;
1100 int len = (receivedCmd[2] - receivedCmd[1] + 1) * 4;
1101 emlGetMemBt( emdata, start, len);
1102 AppendCrc14443a(emdata, len);
1103 EmSendCmdEx(emdata, len+2, false);
1104 p_response = NULL;
1105 } else if(receivedCmd[0] == MIFARE_ULEV1_READSIG && tagType == 7) { // Received a READ SIGNATURE --
1106 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1107 uint16_t start = 4 * 4;
1108 uint8_t emdata[34];
1109 emlGetMemBt( emdata, start, 32);
1110 AppendCrc14443a(emdata, 32);
1111 EmSendCmdEx(emdata, sizeof(emdata), false);
1112 p_response = NULL;
1113 } else if (receivedCmd[0] == MIFARE_ULEV1_READ_CNT && tagType == 7) { // Received a READ COUNTER --
1114 uint8_t index = receivedCmd[1];
1115 uint8_t cmd[] = {0x00,0x00,0x00,0x14,0xa5};
1116 if ( counters[index] > 0) {
1117 num_to_bytes(counters[index], 3, cmd);
1118 AppendCrc14443a(cmd, sizeof(cmd)-2);
1119 }
1120 EmSendCmdEx(cmd,sizeof(cmd),false);
1121 p_response = NULL;
1122 } else if (receivedCmd[0] == MIFARE_ULEV1_INCR_CNT && tagType == 7) { // Received a INC COUNTER --
1123 // number of counter
1124 uint8_t counter = receivedCmd[1];
1125 uint32_t val = bytes_to_num(receivedCmd+2,4);
1126 counters[counter] = val;
1127
1128 // send ACK
1129 uint8_t ack[] = {0x0a};
1130 EmSendCmdEx(ack,sizeof(ack),false);
1131 p_response = NULL;
1132 } else if(receivedCmd[0] == MIFARE_ULEV1_CHECKTEAR && tagType == 7) { // Received a CHECK_TEARING_EVENT --
1133 // first 12 blocks of emu are [getversion answer - check tearing - pack - 0x00 - signature]
1134 uint8_t emdata[3];
1135 uint8_t counter=0;
1136 if (receivedCmd[1]<3) counter = receivedCmd[1];
1137 emlGetMemBt( emdata, 10+counter, 1);
1138 AppendCrc14443a(emdata, sizeof(emdata)-2);
1139 EmSendCmdEx(emdata, sizeof(emdata), false);
1140 p_response = NULL;
1141 } else if(receivedCmd[0] == ISO14443A_CMD_HALT) { // Received a HALT
1142 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1143 p_response = NULL;
1144 } else if(receivedCmd[0] == MIFARE_AUTH_KEYA || receivedCmd[0] == MIFARE_AUTH_KEYB) { // Received an authentication request
1145 if ( tagType == 7 ) { // IF NTAG /EV1 0x60 == GET_VERSION, not a authentication request.
1146 uint8_t emdata[10];
1147 emlGetMemBt( emdata, 0, 8 );
1148 AppendCrc14443a(emdata, sizeof(emdata)-2);
1149 EmSendCmdEx(emdata, sizeof(emdata), false);
1150 p_response = NULL;
1151 } else {
1152
1153 cardAUTHKEY = receivedCmd[0] - 0x60;
1154 cardAUTHSC = receivedCmd[1] / 4; // received block num
1155
1156 // incease nonce at AUTH requests. this is time consuming.
1157 nonce = prand();
1158 //num_to_bytes(nonce, 4, response5);
1159 num_to_bytes(nonce, 4, dynamic_response_info.response);
1160 dynamic_response_info.response_n = 4;
1161
1162 //prepare_tag_modulation(&responses[5], DYNAMIC_MODULATION_BUFFER_SIZE);
1163 prepare_tag_modulation(&dynamic_response_info, DYNAMIC_MODULATION_BUFFER_SIZE);
1164 p_response = &dynamic_response_info;
1165 //p_response = &responses[5];
1166 order = 7;
1167 }
1168 } else if(receivedCmd[0] == ISO14443A_CMD_RATS) { // Received a RATS request
1169 if (tagType == 1 || tagType == 2) { // RATS not supported
1170 EmSend4bit(CARD_NACK_NA);
1171 p_response = NULL;
1172 } else {
1173 p_response = &responses[6]; order = 70;
1174 }
1175 } else if (order == 7 && len == 8) { // Received {nr] and {ar} (part of authentication)
1176 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1177 uint32_t nr = bytes_to_num(receivedCmd,4);
1178 uint32_t ar = bytes_to_num(receivedCmd+4,4);
1179
1180 // Collect AR/NR per keytype & sector
1181 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
1182
1183 int8_t index = -1;
1184 int8_t empty = -1;
1185 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
1186 // find which index to use
1187 if ( (cardAUTHSC == ar_nr_nonces[i].sector) && (cardAUTHKEY == ar_nr_nonces[i].keytype))
1188 index = i;
1189
1190 // keep track of empty slots.
1191 if ( ar_nr_nonces[i].state == EMPTY)
1192 empty = i;
1193 }
1194 // if no empty slots. Choose first and overwrite.
1195 if ( index == -1 ) {
1196 if ( empty == -1 ) {
1197 index = 0;
1198 ar_nr_nonces[index].state = EMPTY;
1199 } else {
1200 index = empty;
1201 }
1202 }
1203
1204 switch(ar_nr_nonces[index].state) {
1205 case EMPTY: {
1206 // first nonce collect
1207 ar_nr_nonces[index].cuid = cuid;
1208 ar_nr_nonces[index].sector = cardAUTHSC;
1209 ar_nr_nonces[index].keytype = cardAUTHKEY;
1210 ar_nr_nonces[index].nonce = nonce;
1211 ar_nr_nonces[index].nr = nr;
1212 ar_nr_nonces[index].ar = ar;
1213 ar_nr_nonces[index].state = FIRST;
1214 break;
1215 }
1216 case FIRST : {
1217 // second nonce collect
1218 ar_nr_nonces[index].nonce2 = nonce;
1219 ar_nr_nonces[index].nr2 = nr;
1220 ar_nr_nonces[index].ar2 = ar;
1221 ar_nr_nonces[index].state = SECOND;
1222
1223 // send to client
1224 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, 0, 0, &ar_nr_nonces[index], sizeof(nonces_t));
1225
1226 ar_nr_nonces[index].state = EMPTY;
1227 ar_nr_nonces[index].sector = 0;
1228 ar_nr_nonces[index].keytype = 0;
1229
1230 moebius_count++;
1231 break;
1232 }
1233 default: break;
1234 }
1235 }
1236 p_response = NULL;
1237
1238 } else if (receivedCmd[0] == MIFARE_ULC_AUTH_1 ) { // ULC authentication, or Desfire Authentication
1239 } else if (receivedCmd[0] == MIFARE_ULEV1_AUTH) { // NTAG / EV-1 authentication
1240 if ( tagType == 7 ) {
1241 uint16_t start = 13; // first 4 blocks of emu are [getversion answer - check tearing - pack - 0x00]
1242 uint8_t emdata[4];
1243 emlGetMemBt( emdata, start, 2);
1244 AppendCrc14443a(emdata, 2);
1245 EmSendCmdEx(emdata, sizeof(emdata), false);
1246 p_response = NULL;
1247 uint32_t pwd = bytes_to_num(receivedCmd+1,4);
1248
1249 if ( MF_DBGLEVEL >= 3) Dbprintf("Auth attempt: %08x", pwd);
1250 }
1251 } else {
1252 // Check for ISO 14443A-4 compliant commands, look at left nibble
1253 switch (receivedCmd[0]) {
1254 case 0x02:
1255 case 0x03: { // IBlock (command no CID)
1256 dynamic_response_info.response[0] = receivedCmd[0];
1257 dynamic_response_info.response[1] = 0x90;
1258 dynamic_response_info.response[2] = 0x00;
1259 dynamic_response_info.response_n = 3;
1260 } break;
1261 case 0x0B:
1262 case 0x0A: { // IBlock (command CID)
1263 dynamic_response_info.response[0] = receivedCmd[0];
1264 dynamic_response_info.response[1] = 0x00;
1265 dynamic_response_info.response[2] = 0x90;
1266 dynamic_response_info.response[3] = 0x00;
1267 dynamic_response_info.response_n = 4;
1268 } break;
1269
1270 case 0x1A:
1271 case 0x1B: { // Chaining command
1272 dynamic_response_info.response[0] = 0xaa | ((receivedCmd[0]) & 1);
1273 dynamic_response_info.response_n = 2;
1274 } break;
1275
1276 case 0xAA:
1277 case 0xBB: {
1278 dynamic_response_info.response[0] = receivedCmd[0] ^ 0x11;
1279 dynamic_response_info.response_n = 2;
1280 } break;
1281
1282 case 0xBA: { // ping / pong
1283 dynamic_response_info.response[0] = 0xAB;
1284 dynamic_response_info.response[1] = 0x00;
1285 dynamic_response_info.response_n = 2;
1286 } break;
1287
1288 case 0xCA:
1289 case 0xC2: { // Readers sends deselect command
1290 dynamic_response_info.response[0] = 0xCA;
1291 dynamic_response_info.response[1] = 0x00;
1292 dynamic_response_info.response_n = 2;
1293 } break;
1294
1295 default: {
1296 // Never seen this command before
1297 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1298 Dbprintf("Received unknown command (len=%d):",len);
1299 Dbhexdump(len,receivedCmd,false);
1300 // Do not respond
1301 dynamic_response_info.response_n = 0;
1302 } break;
1303 }
1304
1305 if (dynamic_response_info.response_n > 0) {
1306 // Copy the CID from the reader query
1307 dynamic_response_info.response[1] = receivedCmd[1];
1308
1309 // Add CRC bytes, always used in ISO 14443A-4 compliant cards
1310 AppendCrc14443a(dynamic_response_info.response, dynamic_response_info.response_n);
1311 dynamic_response_info.response_n += 2;
1312
1313 if (prepare_tag_modulation(&dynamic_response_info,DYNAMIC_MODULATION_BUFFER_SIZE) == false) {
1314 DbpString("Error preparing tag response");
1315 LogTrace(receivedCmd, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
1316 break;
1317 }
1318 p_response = &dynamic_response_info;
1319 }
1320 }
1321
1322 // Count number of wakeups received after a halt
1323 if(order == 6 && lastorder == 5) { happened++; }
1324
1325 // Count number of other messages after a halt
1326 if(order != 6 && lastorder == 5) { happened2++; }
1327
1328 // comment this limit if you want to simulation longer
1329 if (!tracing) {
1330 DbpString("Trace Full. Simulation stopped.");
1331 break;
1332 }
1333 // comment this limit if you want to simulation longer
1334 if(cmdsRecvd > 999) {
1335 DbpString("1000 commands later...");
1336 break;
1337 }
1338 cmdsRecvd++;
1339
1340 if (p_response != NULL) {
1341 EmSendCmd14443aRaw(p_response->modulation, p_response->modulation_n, receivedCmd[0] == 0x52);
1342 // do the tracing for the previous reader request and this tag answer:
1343 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1344 GetParity(p_response->response, p_response->response_n, par);
1345
1346 EmLogTrace(Uart.output,
1347 Uart.len,
1348 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1349 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1350 Uart.parity,
1351 p_response->response,
1352 p_response->response_n,
1353 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1354 (LastTimeProxToAirStart + p_response->ProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1355 par);
1356 }
1357 }
1358
1359 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1360 set_tracing(FALSE);
1361 BigBuf_free_keep_EM();
1362 LED_A_OFF();
1363
1364 if (MF_DBGLEVEL >= 4){
1365 Dbprintf("-[ Wake ups after halt [%d]", happened);
1366 Dbprintf("-[ Messages after halt [%d]", happened2);
1367 Dbprintf("-[ Num of received cmd [%d]", cmdsRecvd);
1368 Dbprintf("-[ Num of moebius tries [%d]", moebius_count);
1369 }
1370
1371 cmd_send(CMD_ACK,1,0,0,0,0);
1372 }
1373
1374 // prepare a delayed transfer. This simply shifts ToSend[] by a number
1375 // of bits specified in the delay parameter.
1376 void PrepareDelayedTransfer(uint16_t delay) {
1377 delay &= 0x07;
1378 if (!delay) return;
1379
1380 uint8_t bitmask = 0;
1381 uint8_t bits_to_shift = 0;
1382 uint8_t bits_shifted = 0;
1383 uint16_t i = 0;
1384
1385 for (i = 0; i < delay; ++i)
1386 bitmask |= (0x01 << i);
1387
1388 ToSend[++ToSendMax] = 0x00;
1389
1390 for (i = 0; i < ToSendMax; ++i) {
1391 bits_to_shift = ToSend[i] & bitmask;
1392 ToSend[i] = ToSend[i] >> delay;
1393 ToSend[i] = ToSend[i] | (bits_shifted << (8 - delay));
1394 bits_shifted = bits_to_shift;
1395 }
1396 }
1397
1398
1399 //-------------------------------------------------------------------------------------
1400 // Transmit the command (to the tag) that was placed in ToSend[].
1401 // Parameter timing:
1402 // if NULL: transfer at next possible time, taking into account
1403 // request guard time and frame delay time
1404 // if == 0: transfer immediately and return time of transfer
1405 // if != 0: delay transfer until time specified
1406 //-------------------------------------------------------------------------------------
1407 static void TransmitFor14443a(const uint8_t *cmd, uint16_t len, uint32_t *timing) {
1408 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
1409
1410 uint32_t ThisTransferTime = 0;
1411
1412 if (timing) {
1413 if(*timing == 0) { // Measure time
1414 *timing = (GetCountSspClk() + 8) & 0xfffffff8;
1415 } else {
1416 PrepareDelayedTransfer(*timing & 0x00000007); // Delay transfer (fine tuning - up to 7 MF clock ticks)
1417 }
1418 if(MF_DBGLEVEL >= 4 && GetCountSspClk() >= (*timing & 0xfffffff8)) Dbprintf("TransmitFor14443a: Missed timing");
1419 while(GetCountSspClk() < (*timing & 0xfffffff8)); // Delay transfer (multiple of 8 MF clock ticks)
1420 LastTimeProxToAirStart = *timing;
1421 } else {
1422 ThisTransferTime = ((MAX(NextTransferTime, GetCountSspClk()) & 0xfffffff8) + 8);
1423
1424 while(GetCountSspClk() < ThisTransferTime);
1425
1426 LastTimeProxToAirStart = ThisTransferTime;
1427 }
1428
1429 // clear TXRDY
1430 AT91C_BASE_SSC->SSC_THR = SEC_Y;
1431
1432 uint16_t c = 0;
1433 for(;;) {
1434 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1435 AT91C_BASE_SSC->SSC_THR = cmd[c];
1436 ++c;
1437 if(c >= len)
1438 break;
1439 }
1440 }
1441
1442 NextTransferTime = MAX(NextTransferTime, LastTimeProxToAirStart + REQUEST_GUARD_TIME);
1443 }
1444
1445 //-----------------------------------------------------------------------------
1446 // Prepare reader command (in bits, support short frames) to send to FPGA
1447 //-----------------------------------------------------------------------------
1448 void CodeIso14443aBitsAsReaderPar(const uint8_t *cmd, uint16_t bits, const uint8_t *parity) {
1449 int i, j;
1450 int last = 0;
1451 uint8_t b;
1452
1453 ToSendReset();
1454
1455 // Start of Communication (Seq. Z)
1456 ToSend[++ToSendMax] = SEC_Z;
1457 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1458
1459 size_t bytecount = nbytes(bits);
1460 // Generate send structure for the data bits
1461 for (i = 0; i < bytecount; i++) {
1462 // Get the current byte to send
1463 b = cmd[i];
1464 size_t bitsleft = MIN((bits-(i*8)),8);
1465
1466 for (j = 0; j < bitsleft; j++) {
1467 if (b & 1) {
1468 // Sequence X
1469 ToSend[++ToSendMax] = SEC_X;
1470 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1471 last = 1;
1472 } else {
1473 if (last == 0) {
1474 // Sequence Z
1475 ToSend[++ToSendMax] = SEC_Z;
1476 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1477 } else {
1478 // Sequence Y
1479 ToSend[++ToSendMax] = SEC_Y;
1480 last = 0;
1481 }
1482 }
1483 b >>= 1;
1484 }
1485
1486 // Only transmit parity bit if we transmitted a complete byte
1487 if (j == 8 && parity != NULL) {
1488 // Get the parity bit
1489 if (parity[i>>3] & (0x80 >> (i&0x0007))) {
1490 // Sequence X
1491 ToSend[++ToSendMax] = SEC_X;
1492 LastProxToAirDuration = 8 * (ToSendMax+1) - 2;
1493 last = 1;
1494 } else {
1495 if (last == 0) {
1496 // Sequence Z
1497 ToSend[++ToSendMax] = SEC_Z;
1498 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1499 } else {
1500 // Sequence Y
1501 ToSend[++ToSendMax] = SEC_Y;
1502 last = 0;
1503 }
1504 }
1505 }
1506 }
1507
1508 // End of Communication: Logic 0 followed by Sequence Y
1509 if (last == 0) {
1510 // Sequence Z
1511 ToSend[++ToSendMax] = SEC_Z;
1512 LastProxToAirDuration = 8 * (ToSendMax+1) - 6;
1513 } else {
1514 // Sequence Y
1515 ToSend[++ToSendMax] = SEC_Y;
1516 last = 0;
1517 }
1518 ToSend[++ToSendMax] = SEC_Y;
1519
1520 // Convert to length of command:
1521 ++ToSendMax;
1522 }
1523
1524 //-----------------------------------------------------------------------------
1525 // Prepare reader command to send to FPGA
1526 //-----------------------------------------------------------------------------
1527 void CodeIso14443aAsReaderPar(const uint8_t *cmd, uint16_t len, const uint8_t *parity) {
1528 CodeIso14443aBitsAsReaderPar(cmd, len*8, parity);
1529 }
1530
1531 //-----------------------------------------------------------------------------
1532 // Wait for commands from reader
1533 // Stop when button is pressed (return 1) or field was gone (return 2)
1534 // Or return 0 when command is captured
1535 //-----------------------------------------------------------------------------
1536 int EmGetCmd(uint8_t *received, uint16_t *len, uint8_t *parity) {
1537 *len = 0;
1538
1539 uint32_t timer = 0, vtime = 0;
1540 int analogCnt = 0;
1541 int analogAVG = 0;
1542
1543 // Set FPGA mode to "simulated ISO 14443 tag", no modulation (listen
1544 // only, since we are receiving, not transmitting).
1545 // Signal field is off with the appropriate LED
1546 LED_D_OFF();
1547 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_LISTEN);
1548
1549 // Set ADC to read field strength
1550 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
1551 AT91C_BASE_ADC->ADC_MR =
1552 ADC_MODE_PRESCALE(63) |
1553 ADC_MODE_STARTUP_TIME(1) |
1554 ADC_MODE_SAMPLE_HOLD_TIME(15);
1555 AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ADC_CHAN_HF);
1556 // start ADC
1557 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1558
1559 // Now run a 'software UART' on the stream of incoming samples.
1560 UartInit(received, parity);
1561
1562 // Clear RXRDY:
1563 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1564
1565 for(;;) {
1566 WDT_HIT();
1567
1568 if (BUTTON_PRESS()) return 1;
1569
1570 // test if the field exists
1571 if (AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ADC_CHAN_HF)) {
1572 analogCnt++;
1573 analogAVG += AT91C_BASE_ADC->ADC_CDR[ADC_CHAN_HF];
1574 AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
1575 if (analogCnt >= 32) {
1576 if ((MAX_ADC_HF_VOLTAGE * (analogAVG / analogCnt) >> 10) < MF_MINFIELDV) {
1577 vtime = GetTickCount();
1578 if (!timer) timer = vtime;
1579 // 50ms no field --> card to idle state
1580 if (vtime - timer > 50) return 2;
1581 } else
1582 if (timer) timer = 0;
1583 analogCnt = 0;
1584 analogAVG = 0;
1585 }
1586 }
1587
1588 // receive and test the miller decoding
1589 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1590 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1591 if(MillerDecoding(b, 0)) {
1592 *len = Uart.len;
1593 return 0;
1594 }
1595 }
1596 }
1597 }
1598
1599 int EmSendCmd14443aRaw(uint8_t *resp, uint16_t respLen, bool correctionNeeded) {
1600 uint8_t b;
1601 uint16_t i = 0;
1602 uint32_t ThisTransferTime;
1603
1604 // Modulate Manchester
1605 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_TAGSIM_MOD);
1606
1607 // Include correction bit if necessary
1608 if (Uart.bitCount == 7)
1609 {
1610 // Short tags (7 bits) don't have parity, determine the correct value from MSB
1611 correctionNeeded = Uart.output[0] & 0x40;
1612 }
1613 else
1614 {
1615 // The parity bits are left-aligned
1616 correctionNeeded = Uart.parity[(Uart.len-1)/8] & (0x80 >> ((Uart.len-1) & 7));
1617 }
1618 // 1236, so correction bit needed
1619 i = (correctionNeeded) ? 0 : 1;
1620
1621 // clear receiving shift register and holding register
1622 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1623 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1624 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1625 b = AT91C_BASE_SSC->SSC_RHR; (void) b;
1626
1627 // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
1628 for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
1629 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
1630 if (AT91C_BASE_SSC->SSC_RHR) break;
1631 }
1632
1633 while ((ThisTransferTime = GetCountSspClk()) & 0x00000007);
1634
1635 // Clear TXRDY:
1636 AT91C_BASE_SSC->SSC_THR = SEC_F;
1637
1638 // send cycle
1639 for(; i < respLen; ) {
1640 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1641 AT91C_BASE_SSC->SSC_THR = resp[i++];
1642 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1643 }
1644
1645 if(BUTTON_PRESS()) break;
1646 }
1647
1648 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
1649 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3; // twich /8 ?? >>3,
1650 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
1651 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
1652 AT91C_BASE_SSC->SSC_THR = SEC_F;
1653 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1654 i++;
1655 }
1656 }
1657 LastTimeProxToAirStart = ThisTransferTime + (correctionNeeded?8:0);
1658 return 0;
1659 }
1660
1661 int EmSend4bitEx(uint8_t resp, bool correctionNeeded){
1662 Code4bitAnswerAsTag(resp);
1663 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1664 // do the tracing for the previous reader request and this tag answer:
1665 uint8_t par[1] = {0x00};
1666 GetParity(&resp, 1, par);
1667 EmLogTrace(Uart.output,
1668 Uart.len,
1669 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1670 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1671 Uart.parity,
1672 &resp,
1673 1,
1674 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1675 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1676 par);
1677 return res;
1678 }
1679
1680 int EmSend4bit(uint8_t resp){
1681 return EmSend4bitEx(resp, false);
1682 }
1683
1684 int EmSendCmdExPar(uint8_t *resp, uint16_t respLen, bool correctionNeeded, uint8_t *par){
1685 CodeIso14443aAsTagPar(resp, respLen, par);
1686 int res = EmSendCmd14443aRaw(ToSend, ToSendMax, correctionNeeded);
1687 // do the tracing for the previous reader request and this tag answer:
1688 EmLogTrace(Uart.output,
1689 Uart.len,
1690 Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG,
1691 Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG,
1692 Uart.parity,
1693 resp,
1694 respLen,
1695 LastTimeProxToAirStart*16 + DELAY_ARM2AIR_AS_TAG,
1696 (LastTimeProxToAirStart + LastProxToAirDuration)*16 + DELAY_ARM2AIR_AS_TAG,
1697 par);
1698 return res;
1699 }
1700
1701 int EmSendCmdEx(uint8_t *resp, uint16_t respLen, bool correctionNeeded){
1702 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1703 GetParity(resp, respLen, par);
1704 return EmSendCmdExPar(resp, respLen, correctionNeeded, par);
1705 }
1706
1707 int EmSendCmd(uint8_t *resp, uint16_t respLen){
1708 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1709 GetParity(resp, respLen, par);
1710 return EmSendCmdExPar(resp, respLen, false, par);
1711 }
1712
1713 int EmSendCmdPar(uint8_t *resp, uint16_t respLen, uint8_t *par){
1714 return EmSendCmdExPar(resp, respLen, false, par);
1715 }
1716
1717 bool EmLogTrace(uint8_t *reader_data, uint16_t reader_len, uint32_t reader_StartTime, uint32_t reader_EndTime, uint8_t *reader_Parity,
1718 uint8_t *tag_data, uint16_t tag_len, uint32_t tag_StartTime, uint32_t tag_EndTime, uint8_t *tag_Parity)
1719 {
1720 // we cannot exactly measure the end and start of a received command from reader. However we know that the delay from
1721 // end of the received command to start of the tag's (simulated by us) answer is n*128+20 or n*128+84 resp.
1722 // with n >= 9. The start of the tags answer can be measured and therefore the end of the received command be calculated:
1723 uint16_t reader_modlen = reader_EndTime - reader_StartTime;
1724 uint16_t approx_fdt = tag_StartTime - reader_EndTime;
1725 uint16_t exact_fdt = (approx_fdt - 20 + 32)/64 * 64 + 20;
1726 reader_EndTime = tag_StartTime - exact_fdt;
1727 reader_StartTime = reader_EndTime - reader_modlen;
1728
1729 if (!LogTrace(reader_data, reader_len, reader_StartTime, reader_EndTime, reader_Parity, TRUE))
1730 return FALSE;
1731 else
1732 return(!LogTrace(tag_data, tag_len, tag_StartTime, tag_EndTime, tag_Parity, FALSE));
1733
1734 }
1735
1736 //-----------------------------------------------------------------------------
1737 // Wait a certain time for tag response
1738 // If a response is captured return TRUE
1739 // If it takes too long return FALSE
1740 //-----------------------------------------------------------------------------
1741 static int GetIso14443aAnswerFromTag(uint8_t *receivedResponse, uint8_t *receivedResponsePar, uint16_t offset) {
1742 uint32_t c = 0x00;
1743
1744 // Set FPGA mode to "reader listen mode", no modulation (listen
1745 // only, since we are receiving, not transmitting).
1746 // Signal field is on with the appropriate LED
1747 LED_D_ON();
1748 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_LISTEN);
1749
1750 // Now get the answer from the card
1751 DemodInit(receivedResponse, receivedResponsePar);
1752
1753 // clear RXRDY:
1754 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1755
1756 for(;;) {
1757 WDT_HIT();
1758
1759 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
1760 b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1761 if(ManchesterDecoding(b, offset, 0)) {
1762 NextTransferTime = MAX(NextTransferTime, Demod.endTime - (DELAY_AIR2ARM_AS_READER + DELAY_ARM2AIR_AS_READER)/16 + FRAME_DELAY_TIME_PICC_TO_PCD);
1763 return TRUE;
1764 } else if (c++ > iso14a_timeout && Demod.state == DEMOD_UNSYNCD) {
1765 return FALSE;
1766 }
1767 }
1768 }
1769 }
1770
1771 void ReaderTransmitBitsPar(uint8_t* frame, uint16_t bits, uint8_t *par, uint32_t *timing) {
1772
1773 CodeIso14443aBitsAsReaderPar(frame, bits, par);
1774 // Send command to tag
1775 TransmitFor14443a(ToSend, ToSendMax, timing);
1776 if(trigger) LED_A_ON();
1777
1778 LogTrace(frame, nbytes(bits), (LastTimeProxToAirStart<<4) + DELAY_ARM2AIR_AS_READER, ((LastTimeProxToAirStart + LastProxToAirDuration)<<4) + DELAY_ARM2AIR_AS_READER, par, TRUE);
1779 }
1780
1781 void ReaderTransmitPar(uint8_t* frame, uint16_t len, uint8_t *par, uint32_t *timing) {
1782 ReaderTransmitBitsPar(frame, len*8, par, timing);
1783 }
1784
1785 void ReaderTransmitBits(uint8_t* frame, uint16_t len, uint32_t *timing) {
1786 // Generate parity and redirect
1787 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1788 GetParity(frame, len/8, par);
1789 ReaderTransmitBitsPar(frame, len, par, timing);
1790 }
1791
1792 void ReaderTransmit(uint8_t* frame, uint16_t len, uint32_t *timing) {
1793 // Generate parity and redirect
1794 uint8_t par[MAX_PARITY_SIZE] = {0x00};
1795 GetParity(frame, len, par);
1796 ReaderTransmitBitsPar(frame, len*8, par, timing);
1797 }
1798
1799 int ReaderReceiveOffset(uint8_t* receivedAnswer, uint16_t offset, uint8_t *parity) {
1800 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, offset))
1801 return FALSE;
1802 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1803 return Demod.len;
1804 }
1805
1806 int ReaderReceive(uint8_t *receivedAnswer, uint8_t *parity) {
1807 if (!GetIso14443aAnswerFromTag(receivedAnswer, parity, 0))
1808 return FALSE;
1809 LogTrace(receivedAnswer, Demod.len, Demod.startTime*16 - DELAY_AIR2ARM_AS_READER, Demod.endTime*16 - DELAY_AIR2ARM_AS_READER, parity, FALSE);
1810 return Demod.len;
1811 }
1812
1813 // performs iso14443a anticollision (optional) and card select procedure
1814 // fills the uid and cuid pointer unless NULL
1815 // fills the card info record unless NULL
1816 // if anticollision is false, then the UID must be provided in uid_ptr[]
1817 // and num_cascades must be set (1: 4 Byte UID, 2: 7 Byte UID, 3: 10 Byte UID)
1818 int iso14443a_select_card(byte_t *uid_ptr, iso14a_card_select_t *p_hi14a_card, uint32_t *cuid_ptr, bool anticollision, uint8_t num_cascades) {
1819 uint8_t wupa[] = { ISO14443A_CMD_WUPA }; // 0x26 - ISO14443A_CMD_REQA 0x52 - ISO14443A_CMD_WUPA
1820 uint8_t sel_all[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x20 };
1821 uint8_t sel_uid[] = { ISO14443A_CMD_ANTICOLL_OR_SELECT,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
1822 uint8_t rats[] = { ISO14443A_CMD_RATS,0x80,0x00,0x00 }; // FSD=256, FSDI=8, CID=0
1823 uint8_t resp[MAX_FRAME_SIZE] = {0}; // theoretically. A usual RATS will be much smaller
1824 uint8_t resp_par[MAX_PARITY_SIZE] = {0};
1825 byte_t uid_resp[4] = {0};
1826 size_t uid_resp_len = 0;
1827
1828 uint8_t sak = 0x04; // cascade uid
1829 int cascade_level = 0;
1830 int len;
1831
1832 // Broadcast for a card, WUPA (0x52) will force response from all cards in the field
1833 ReaderTransmitBitsPar(wupa, 7, NULL, NULL);
1834
1835 // Receive the ATQA
1836 if(!ReaderReceive(resp, resp_par)) return 0;
1837
1838 if(p_hi14a_card) {
1839 memcpy(p_hi14a_card->atqa, resp, 2);
1840 p_hi14a_card->uidlen = 0;
1841 memset(p_hi14a_card->uid,0,10);
1842 }
1843
1844 if (anticollision) {
1845 // clear uid
1846 if (uid_ptr)
1847 memset(uid_ptr,0,10);
1848 }
1849
1850 // reset the PCB block number
1851 iso14_pcb_blocknum = 0;
1852
1853 // check for proprietary anticollision:
1854 if ((resp[0] & 0x1F) == 0) return 3;
1855
1856 // OK we will select at least at cascade 1, lets see if first byte of UID was 0x88 in
1857 // which case we need to make a cascade 2 request and select - this is a long UID
1858 // While the UID is not complete, the 3nd bit (from the right) is set in the SAK.
1859 for(; sak & 0x04; cascade_level++) {
1860 // SELECT_* (L1: 0x93, L2: 0x95, L3: 0x97)
1861 sel_uid[0] = sel_all[0] = 0x93 + cascade_level * 2;
1862
1863 if (anticollision) {
1864 // SELECT_ALL
1865 ReaderTransmit(sel_all, sizeof(sel_all), NULL);
1866 if (!ReaderReceive(resp, resp_par)) return 0;
1867
1868 if (Demod.collisionPos) { // we had a collision and need to construct the UID bit by bit
1869 memset(uid_resp, 0, 4);
1870 uint16_t uid_resp_bits = 0;
1871 uint16_t collision_answer_offset = 0;
1872 // anti-collision-loop:
1873 while (Demod.collisionPos) {
1874 Dbprintf("Multiple tags detected. Collision after Bit %d", Demod.collisionPos);
1875 for (uint16_t i = collision_answer_offset; i < Demod.collisionPos; i++, uid_resp_bits++) { // add valid UID bits before collision point
1876 uint16_t UIDbit = (resp[i/8] >> (i % 8)) & 0x01;
1877 uid_resp[uid_resp_bits / 8] |= UIDbit << (uid_resp_bits % 8);
1878 }
1879 uid_resp[uid_resp_bits/8] |= 1 << (uid_resp_bits % 8); // next time select the card(s) with a 1 in the collision position
1880 uid_resp_bits++;
1881 // construct anticollosion command:
1882 sel_uid[1] = ((2 + uid_resp_bits/8) << 4) | (uid_resp_bits & 0x07); // length of data in bytes and bits
1883 for (uint16_t i = 0; i <= uid_resp_bits/8; i++) {
1884 sel_uid[2+i] = uid_resp[i];
1885 }
1886 collision_answer_offset = uid_resp_bits%8;
1887 ReaderTransmitBits(sel_uid, 16 + uid_resp_bits, NULL);
1888 if (!ReaderReceiveOffset(resp, collision_answer_offset, resp_par)) return 0;
1889 }
1890 // finally, add the last bits and BCC of the UID
1891 for (uint16_t i = collision_answer_offset; i < (Demod.len-1)*8; i++, uid_resp_bits++) {
1892 uint16_t UIDbit = (resp[i/8] >> (i%8)) & 0x01;
1893 uid_resp[uid_resp_bits/8] |= UIDbit << (uid_resp_bits % 8);
1894 }
1895
1896 } else { // no collision, use the response to SELECT_ALL as current uid
1897 memcpy(uid_resp, resp, 4);
1898 }
1899
1900 } else {
1901 if (cascade_level < num_cascades - 1) {
1902 uid_resp[0] = 0x88;
1903 memcpy(uid_resp+1, uid_ptr+cascade_level*3, 3);
1904 } else {
1905 memcpy(uid_resp, uid_ptr+cascade_level*3, 4);
1906 }
1907 }
1908 uid_resp_len = 4;
1909
1910 // calculate crypto UID. Always use last 4 Bytes.
1911 if(cuid_ptr)
1912 *cuid_ptr = bytes_to_num(uid_resp, 4);
1913
1914 // Construct SELECT UID command
1915 sel_uid[1] = 0x70; // transmitting a full UID (1 Byte cmd, 1 Byte NVB, 4 Byte UID, 1 Byte BCC, 2 Bytes CRC)
1916 memcpy(sel_uid+2, uid_resp, 4); // the UID received during anticollision, or the provided UID
1917 sel_uid[6] = sel_uid[2] ^ sel_uid[3] ^ sel_uid[4] ^ sel_uid[5]; // calculate and add BCC
1918 AppendCrc14443a(sel_uid, 7); // calculate and add CRC
1919 ReaderTransmit(sel_uid, sizeof(sel_uid), NULL);
1920
1921 // Receive the SAK
1922 if (!ReaderReceive(resp, resp_par)) return 0;
1923
1924 sak = resp[0];
1925
1926 // Test if more parts of the uid are coming
1927 if ((sak & 0x04) /* && uid_resp[0] == 0x88 */) {
1928 // Remove first byte, 0x88 is not an UID byte, it CT, see page 3 of:
1929 // http://www.nxp.com/documents/application_note/AN10927.pdf
1930 uid_resp[0] = uid_resp[1];
1931 uid_resp[1] = uid_resp[2];
1932 uid_resp[2] = uid_resp[3];
1933 uid_resp_len = 3;
1934 }
1935
1936 if(uid_ptr && anticollision)
1937 memcpy(uid_ptr + (cascade_level*3), uid_resp, uid_resp_len);
1938
1939 if(p_hi14a_card) {
1940 memcpy(p_hi14a_card->uid + (cascade_level*3), uid_resp, uid_resp_len);
1941 p_hi14a_card->uidlen += uid_resp_len;
1942 }
1943 }
1944
1945 if(p_hi14a_card) {
1946 p_hi14a_card->sak = sak;
1947 p_hi14a_card->ats_len = 0;
1948 }
1949
1950 // non iso14443a compliant tag
1951 if( (sak & 0x20) == 0) return 2;
1952
1953 // Request for answer to select
1954 AppendCrc14443a(rats, 2);
1955 ReaderTransmit(rats, sizeof(rats), NULL);
1956
1957 if (!(len = ReaderReceive(resp, resp_par))) return 0;
1958
1959 if(p_hi14a_card) {
1960 memcpy(p_hi14a_card->ats, resp, sizeof(p_hi14a_card->ats));
1961 p_hi14a_card->ats_len = len;
1962 }
1963
1964 // set default timeout based on ATS
1965 iso14a_set_ATS_timeout(resp);
1966 return 1;
1967 }
1968
1969 void iso14443a_setup(uint8_t fpga_minor_mode) {
1970
1971 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1972 // Set up the synchronous serial port
1973 FpgaSetupSsc();
1974 // connect Demodulated Signal to ADC:
1975 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1976
1977 LED_D_OFF();
1978 // Signal field is on with the appropriate LED
1979 if (fpga_minor_mode == FPGA_HF_ISO14443A_READER_MOD ||
1980 fpga_minor_mode == FPGA_HF_ISO14443A_READER_LISTEN)
1981 LED_D_ON();
1982
1983 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | fpga_minor_mode);
1984
1985 SpinDelay(20);
1986
1987 // Start the timer
1988 StartCountSspClk();
1989
1990 // Prepare the demodulation functions
1991 DemodReset();
1992 UartReset();
1993 NextTransferTime = 2 * DELAY_ARM2AIR_AS_READER;
1994 iso14a_set_timeout(10*106); // 20ms default
1995 }
1996
1997 int iso14_apdu(uint8_t *cmd, uint16_t cmd_len, void *data) {
1998 uint8_t parity[MAX_PARITY_SIZE] = {0x00};
1999 uint8_t real_cmd[cmd_len+4];
2000 real_cmd[0] = 0x0a; //I-Block
2001 // put block number into the PCB
2002 real_cmd[0] |= iso14_pcb_blocknum;
2003 real_cmd[1] = 0x00; //CID: 0 //FIXME: allow multiple selected cards
2004 memcpy(real_cmd+2, cmd, cmd_len);
2005 AppendCrc14443a(real_cmd,cmd_len+2);
2006
2007 ReaderTransmit(real_cmd, cmd_len+4, NULL);
2008 size_t len = ReaderReceive(data, parity);
2009 //DATA LINK ERROR
2010 if (!len) return 0;
2011
2012 uint8_t *data_bytes = (uint8_t *) data;
2013
2014 // if we received an I- or R(ACK)-Block with a block number equal to the
2015 // current block number, toggle the current block number
2016 if (len >= 4 // PCB+CID+CRC = 4 bytes
2017 && ((data_bytes[0] & 0xC0) == 0 // I-Block
2018 || (data_bytes[0] & 0xD0) == 0x80) // R-Block with ACK bit set to 0
2019 && (data_bytes[0] & 0x01) == iso14_pcb_blocknum) // equal block numbers
2020 {
2021 iso14_pcb_blocknum ^= 1;
2022 }
2023 return len;
2024 }
2025
2026
2027 //-----------------------------------------------------------------------------
2028 // Read an ISO 14443a tag. Send out commands and store answers.
2029 //-----------------------------------------------------------------------------
2030 void ReaderIso14443a(UsbCommand *c) {
2031 iso14a_command_t param = c->arg[0];
2032 size_t len = c->arg[1] & 0xffff;
2033 size_t lenbits = c->arg[1] >> 16;
2034 uint32_t timeout = c->arg[2];
2035 uint8_t *cmd = c->d.asBytes;
2036 uint32_t arg0 = 0;
2037 byte_t buf[USB_CMD_DATA_SIZE] = {0x00};
2038 uint8_t par[MAX_PARITY_SIZE] = {0x00};
2039
2040 if (param & ISO14A_CONNECT)
2041 clear_trace();
2042
2043 set_tracing(TRUE);
2044
2045 if (param & ISO14A_REQUEST_TRIGGER)
2046 iso14a_set_trigger(TRUE);
2047
2048 if (param & ISO14A_CONNECT) {
2049 iso14443a_setup(FPGA_HF_ISO14443A_READER_LISTEN);
2050 if(!(param & ISO14A_NO_SELECT)) {
2051 iso14a_card_select_t *card = (iso14a_card_select_t*)buf;
2052 arg0 = iso14443a_select_card(NULL,card,NULL, true, 0);
2053 cmd_send(CMD_ACK, arg0, card->uidlen, 0, buf, sizeof(iso14a_card_select_t));
2054 // if it fails, the cmdhf14a.c client quites.. however this one still executes.
2055 if ( arg0 == 0 ) return;
2056 }
2057 }
2058
2059 if (param & ISO14A_SET_TIMEOUT)
2060 iso14a_set_timeout(timeout);
2061
2062 if (param & ISO14A_APDU) {
2063 arg0 = iso14_apdu(cmd, len, buf);
2064 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2065 }
2066
2067 if (param & ISO14A_RAW) {
2068 if (param & ISO14A_APPEND_CRC) {
2069 if (param & ISO14A_TOPAZMODE)
2070 AppendCrc14443b(cmd,len);
2071 else
2072 AppendCrc14443a(cmd,len);
2073
2074 len += 2;
2075 if (lenbits) lenbits += 16;
2076 }
2077 if (lenbits>0) { // want to send a specific number of bits (e.g. short commands)
2078 if (param & ISO14A_TOPAZMODE) {
2079 int bits_to_send = lenbits;
2080 uint16_t i = 0;
2081 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 7), NULL, NULL); // first byte is always short (7bits) and no parity
2082 bits_to_send -= 7;
2083 while (bits_to_send > 0) {
2084 ReaderTransmitBitsPar(&cmd[i++], MIN(bits_to_send, 8), NULL, NULL); // following bytes are 8 bit and no parity
2085 bits_to_send -= 8;
2086 }
2087 } else {
2088 GetParity(cmd, lenbits/8, par);
2089 ReaderTransmitBitsPar(cmd, lenbits, par, NULL); // bytes are 8 bit with odd parity
2090 }
2091 } else { // want to send complete bytes only
2092 if (param & ISO14A_TOPAZMODE) {
2093 uint16_t i = 0;
2094 ReaderTransmitBitsPar(&cmd[i++], 7, NULL, NULL); // first byte: 7 bits, no paritiy
2095 while (i < len) {
2096 ReaderTransmitBitsPar(&cmd[i++], 8, NULL, NULL); // following bytes: 8 bits, no paritiy
2097 }
2098 } else {
2099 ReaderTransmit(cmd,len, NULL); // 8 bits, odd parity
2100 }
2101 }
2102 arg0 = ReaderReceive(buf, par);
2103 cmd_send(CMD_ACK,arg0,0,0,buf,sizeof(buf));
2104 }
2105
2106 if (param & ISO14A_REQUEST_TRIGGER)
2107 iso14a_set_trigger(FALSE);
2108
2109 if (param & ISO14A_NO_DISCONNECT)
2110 return;
2111
2112 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2113 set_tracing(FALSE);
2114 LEDsoff();
2115 }
2116
2117 // Determine the distance between two nonces.
2118 // Assume that the difference is small, but we don't know which is first.
2119 // Therefore try in alternating directions.
2120 int32_t dist_nt(uint32_t nt1, uint32_t nt2) {
2121
2122 if (nt1 == nt2) return 0;
2123
2124 uint32_t nttmp1 = nt1;
2125 uint32_t nttmp2 = nt2;
2126
2127 // 0xFFFF -- Half up and half down to find distance between nonces
2128 for (uint16_t i = 1; i < 32768/8; i += 8) {
2129 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i;
2130 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+1;
2131 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+2;
2132 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+3;
2133 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+4;
2134 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+5;
2135 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+6;
2136 nttmp1 = prng_successor(nttmp1, 1); if (nttmp1 == nt2) return i+7;
2137
2138 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -i;
2139 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+1);
2140 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+2);
2141 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+3);
2142 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+4);
2143 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+5);
2144 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+6);
2145 nttmp2 = prng_successor(nttmp2, 1); if (nttmp2 == nt1) return -(i+7);
2146 }
2147 // either nt1 or nt2 are invalid nonces
2148 return(-99999);
2149 }
2150
2151 //-----------------------------------------------------------------------------
2152 // Recover several bits of the cypher stream. This implements (first stages of)
2153 // the algorithm described in "The Dark Side of Security by Obscurity and
2154 // Cloning MiFare Classic Rail and Building Passes, Anywhere, Anytime"
2155 // (article by Nicolas T. Courtois, 2009)
2156 //-----------------------------------------------------------------------------
2157
2158 void ReaderMifare(bool first_try, uint8_t block, uint8_t keytype ) {
2159
2160 uint8_t mf_auth[] = { keytype, block, 0x00, 0x00 };
2161 uint8_t mf_nr_ar[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 };
2162 uint8_t uid[10] = {0,0,0,0,0,0,0,0,0,0};
2163 uint8_t par_list[8] = {0,0,0,0,0,0,0,0};
2164 uint8_t ks_list[8] = {0,0,0,0,0,0,0,0};
2165 uint8_t receivedAnswer[MAX_MIFARE_FRAME_SIZE] = {0x00};
2166 uint8_t receivedAnswerPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
2167 uint8_t par[1] = {0}; // maximum 8 Bytes to be sent here, 1 byte parity is therefore enough
2168 byte_t nt_diff = 0;
2169 uint32_t nt = 0;
2170 uint32_t previous_nt = 0;
2171 uint32_t cuid = 0;
2172
2173 int32_t catch_up_cycles = 0;
2174 int32_t last_catch_up = 0;
2175 int32_t isOK = 0;
2176 int32_t nt_distance = 0;
2177
2178 uint16_t elapsed_prng_sequences = 1;
2179 uint16_t consecutive_resyncs = 0;
2180 uint16_t unexpected_random = 0;
2181 uint16_t sync_tries = 0;
2182
2183 // static variables here, is re-used in the next call
2184 static uint32_t nt_attacked = 0;
2185 static uint32_t sync_time = 0;
2186 static uint32_t sync_cycles = 0;
2187 static uint8_t par_low = 0;
2188 static uint8_t mf_nr_ar3 = 0;
2189
2190 #define PRNG_SEQUENCE_LENGTH (1 << 16)
2191 #define MAX_UNEXPECTED_RANDOM 4 // maximum number of unexpected (i.e. real) random numbers when trying to sync. Then give up.
2192 #define MAX_SYNC_TRIES 32
2193
2194 AppendCrc14443a(mf_auth, 2);
2195
2196 BigBuf_free(); BigBuf_Clear_ext(false);
2197 clear_trace();
2198 set_tracing(FALSE);
2199 iso14443a_setup(FPGA_HF_ISO14443A_READER_MOD);
2200
2201 sync_time = GetCountSspClk() & 0xfffffff8;
2202 sync_cycles = PRNG_SEQUENCE_LENGTH; // Mifare Classic's random generator repeats every 2^16 cycles (and so do the nonces).
2203 nt_attacked = 0;
2204
2205 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare::Sync %u", sync_time);
2206
2207 if (first_try) {
2208 mf_nr_ar3 = 0;
2209 par_low = 0;
2210 } else {
2211 // we were unsuccessful on a previous call.
2212 // Try another READER nonce (first 3 parity bits remain the same)
2213 ++mf_nr_ar3;
2214 mf_nr_ar[3] = mf_nr_ar3;
2215 par[0] = par_low;
2216 }
2217
2218 bool have_uid = FALSE;
2219 uint8_t cascade_levels = 0;
2220
2221 LED_C_ON();
2222 uint16_t i;
2223 for(i = 0; TRUE; ++i) {
2224
2225 WDT_HIT();
2226
2227 // Test if the action was cancelled
2228 if(BUTTON_PRESS()) {
2229 isOK = -1;
2230 break;
2231 }
2232
2233 // this part is from Piwi's faster nonce collecting part in Hardnested.
2234 if (!have_uid) { // need a full select cycle to get the uid first
2235 iso14a_card_select_t card_info;
2236 if(!iso14443a_select_card(uid, &card_info, &cuid, true, 0)) {
2237 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (ALL)");
2238 break;
2239 }
2240 switch (card_info.uidlen) {
2241 case 4 : cascade_levels = 1; break;
2242 case 7 : cascade_levels = 2; break;
2243 case 10: cascade_levels = 3; break;
2244 default: break;
2245 }
2246 have_uid = TRUE;
2247 } else { // no need for anticollision. We can directly select the card
2248 if(!iso14443a_select_card(uid, NULL, &cuid, false, cascade_levels)) {
2249 if (MF_DBGLEVEL >= 4) Dbprintf("Mifare: Can't select card (UID)");
2250 continue;
2251 }
2252 }
2253
2254 // Sending timeslot of ISO14443a frame
2255 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles + catch_up_cycles;
2256 catch_up_cycles = 0;
2257
2258 // if we missed the sync time already, advance to the next nonce repeat
2259 while( GetCountSspClk() > sync_time) {
2260 ++elapsed_prng_sequences;
2261 sync_time = (sync_time & 0xfffffff8 ) + sync_cycles;
2262 }
2263
2264 // Transmit MIFARE_CLASSIC_AUTH at synctime. Should result in returning the same tag nonce (== nt_attacked)
2265 ReaderTransmit(mf_auth, sizeof(mf_auth), &sync_time);
2266
2267 // Receive the (4 Byte) "random" nonce from TAG
2268 if (!ReaderReceive(receivedAnswer, receivedAnswerPar))
2269 continue;
2270
2271 previous_nt = nt;
2272 nt = bytes_to_num(receivedAnswer, 4);
2273
2274 // Transmit reader nonce with fake par
2275 ReaderTransmitPar(mf_nr_ar, sizeof(mf_nr_ar), par, NULL);
2276
2277 // we didn't calibrate our clock yet,
2278 // iceman: has to be calibrated every time.
2279 if (previous_nt && !nt_attacked) {
2280
2281 nt_distance = dist_nt(previous_nt, nt);
2282
2283 // if no distance between, then we are in sync.
2284 if (nt_distance == 0) {
2285 nt_attacked = nt;
2286 } else {
2287 if (nt_distance == -99999) { // invalid nonce received
2288 ++unexpected_random;
2289 if (unexpected_random > MAX_UNEXPECTED_RANDOM) {
2290 isOK = -3; // Card has an unpredictable PRNG. Give up
2291 break;
2292 } else {
2293 if (sync_cycles <= 0) sync_cycles += PRNG_SEQUENCE_LENGTH;
2294 LED_B_OFF();
2295 continue; // continue trying...
2296 }
2297 }
2298
2299 if (++sync_tries > MAX_SYNC_TRIES) {
2300 isOK = -4; // Card's PRNG runs at an unexpected frequency or resets unexpectedly
2301 break;
2302 }
2303
2304 sync_cycles = (sync_cycles - nt_distance)/elapsed_prng_sequences;
2305
2306 if (sync_cycles <= 0)
2307 sync_cycles += PRNG_SEQUENCE_LENGTH;
2308
2309 if (MF_DBGLEVEL >= 4)
2310 Dbprintf("calibrating in cycle %d. nt_distance=%d, elapsed_prng_sequences=%d, new sync_cycles: %d\n", i, nt_distance, elapsed_prng_sequences, sync_cycles);
2311
2312 LED_B_OFF();
2313 continue;
2314 }
2315 }
2316 LED_B_OFF();
2317
2318 if ( (nt != nt_attacked) && nt_attacked) { // we somehow lost sync. Try to catch up again...
2319
2320 catch_up_cycles = ABS(dist_nt(nt_attacked, nt));
2321 if (catch_up_cycles == 99999) { // invalid nonce received. Don't resync on that one.
2322 catch_up_cycles = 0;
2323 continue;
2324 }
2325 // average?
2326 catch_up_cycles /= elapsed_prng_sequences;
2327
2328 if (catch_up_cycles == last_catch_up) {
2329 ++consecutive_resyncs;
2330 } else {
2331 last_catch_up = catch_up_cycles;
2332 consecutive_resyncs = 0;
2333 }
2334
2335 if (consecutive_resyncs < 3) {
2336 if (MF_DBGLEVEL >= 4)
2337 Dbprintf("Lost sync in cycle %d. nt_distance=%d. Consecutive Resyncs = %d. Trying one time catch up...\n", i, catch_up_cycles, consecutive_resyncs);
2338 } else {
2339 sync_cycles += catch_up_cycles;
2340
2341 if (MF_DBGLEVEL >= 4)
2342 Dbprintf("Lost sync in cycle %d for the fourth time consecutively (nt_distance = %d). Adjusting sync_cycles to %d.\n", i, catch_up_cycles, sync_cycles);
2343
2344 last_catch_up = 0;
2345 catch_up_cycles = 0;
2346 consecutive_resyncs = 0;
2347 }
2348 continue;
2349 }
2350
2351 // Receive answer. This will be a 4 Bit NACK when the 8 parity bits are OK after decoding
2352 if (ReaderReceive(receivedAnswer, receivedAnswerPar)) {
2353 catch_up_cycles = 8; // the PRNG is delayed by 8 cycles due to the NAC (4Bits = 0x05 encrypted) transfer
2354
2355 if (nt_diff == 0)
2356 par_low = par[0] & 0xE0; // there is no need to check all parities for other nt_diff. Parity Bits for mf_nr_ar[0..2] won't change
2357
2358 par_list[nt_diff] = SwapBits(par[0], 8);
2359 ks_list[nt_diff] = receivedAnswer[0] ^ 0x05; // xor with NACK value to get keystream
2360
2361 // Test if the information is complete
2362 if (nt_diff == 0x07) {
2363 isOK = 1;
2364 break;
2365 }
2366
2367 nt_diff = (nt_diff + 1) & 0x07;
2368 mf_nr_ar[3] = (mf_nr_ar[3] & 0x1F) | (nt_diff << 5);
2369 par[0] = par_low;
2370
2371 } else {
2372 // No NACK.
2373 if (nt_diff == 0 && first_try) {
2374 par[0]++;
2375 if (par[0] == 0x00) { // tried all 256 possible parities without success. Card doesn't send NACK.
2376 isOK = -2;
2377 break;
2378 }
2379 } else {
2380 // Why this?
2381 par[0] = ((par[0] & 0x1F) + 1) | par_low;
2382 }
2383 }
2384
2385 // reset the resyncs since we got a complete transaction on right time.
2386 consecutive_resyncs = 0;
2387 } // end for loop
2388
2389 mf_nr_ar[3] &= 0x1F;
2390
2391 if (MF_DBGLEVEL >= 4) Dbprintf("Number of sent auth requestes: %u", i);
2392
2393 uint8_t buf[28] = {0x00};
2394 memset(buf, 0x00, sizeof(buf));
2395 num_to_bytes(cuid, 4, buf);
2396 num_to_bytes(nt, 4, buf + 4);
2397 memcpy(buf + 8, par_list, 8);
2398 memcpy(buf + 16, ks_list, 8);
2399 memcpy(buf + 24, mf_nr_ar, 4);
2400
2401 cmd_send(CMD_ACK, isOK, 0, 0, buf, sizeof(buf) );
2402
2403 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
2404 LEDsoff();
2405 set_tracing(FALSE);
2406 }
2407
2408
2409 /**
2410 *MIFARE 1K simulate.
2411 *
2412 *@param flags :
2413 * FLAG_INTERACTIVE - In interactive mode, we are expected to finish the operation with an ACK
2414 * FLAG_4B_UID_IN_DATA - use 4-byte UID in the data-section
2415 * FLAG_7B_UID_IN_DATA - use 7-byte UID in the data-section
2416 * FLAG_10B_UID_IN_DATA - use 10-byte UID in the data-section
2417 * FLAG_UID_IN_EMUL - use 4-byte UID from emulator memory
2418 * FLAG_NR_AR_ATTACK - collect NR_AR responses for bruteforcing later
2419 *@param exitAfterNReads, exit simulation after n blocks have been read, 0 is inifite
2420 */
2421 void Mifare1ksim(uint8_t flags, uint8_t exitAfterNReads, uint8_t arg2, uint8_t *datain) {
2422
2423 // init pseudorand
2424 fast_prand( GetTickCount() );
2425
2426 int cardSTATE = MFEMUL_NOFIELD;
2427 int _UID_LEN = 0; // 4, 7, 10
2428 int vHf = 0; // in mV
2429 int res = 0;
2430 uint32_t selTimer = 0;
2431 uint32_t authTimer = 0;
2432 uint16_t len = 0;
2433 uint8_t cardWRBL = 0;
2434 uint8_t cardAUTHSC = 0;
2435 uint8_t cardAUTHKEY = 0xff; // no authentication
2436 uint32_t cuid = 0;
2437 uint32_t ans = 0;
2438 uint32_t cardINTREG = 0;
2439 uint8_t cardINTBLOCK = 0;
2440 struct Crypto1State mpcs = {0, 0};
2441 struct Crypto1State *pcs;
2442 pcs = &mpcs;
2443 uint32_t numReads = 0; // Counts numer of times reader read a block
2444 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
2445 uint8_t receivedCmd_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2446 uint8_t response[MAX_MIFARE_FRAME_SIZE] = {0x00};
2447 uint8_t response_par[MAX_MIFARE_PARITY_SIZE] = {0x00};
2448
2449 uint8_t atqa[] = {0x04, 0x00}; // Mifare classic 1k
2450 uint8_t sak_4[] = {0x0C, 0x00, 0x00}; // CL1 - 4b uid
2451 uint8_t sak_7[] = {0x0C, 0x00, 0x00}; // CL2 - 7b uid
2452 uint8_t sak_10[] = {0x0C, 0x00, 0x00}; // CL3 - 10b uid
2453 // uint8_t sak[] = {0x09, 0x3f, 0xcc }; // Mifare Mini
2454
2455 uint8_t rUIDBCC1[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2456 uint8_t rUIDBCC2[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2457 uint8_t rUIDBCC3[] = {0xde, 0xad, 0xbe, 0xaf, 0x62};
2458
2459 // TAG Nonce - Authenticate response
2460 uint8_t rAUTH_NT[4];
2461 uint32_t nonce = prand();
2462 num_to_bytes(nonce, 4, rAUTH_NT);
2463
2464 // uint8_t rAUTH_NT[] = {0x55, 0x41, 0x49, 0x92};// nonce from nested? why this?
2465 uint8_t rAUTH_AT[] = {0x00, 0x00, 0x00, 0x00};
2466
2467 // Here, we collect CUID, NT, NR, AR, CUID2, NT2, NR2, AR2
2468 // This can be used in a reader-only attack.
2469 nonces_t ar_nr_nonces[ATTACK_KEY_COUNT];
2470 memset(ar_nr_nonces, 0x00, sizeof(ar_nr_nonces));
2471
2472 // -- Determine the UID
2473 // Can be set from emulator memory or incoming data
2474 // Length: 4,7,or 10 bytes
2475 if ( (flags & FLAG_UID_IN_EMUL) == FLAG_UID_IN_EMUL)
2476 emlGetMemBt(datain, 0, 10); // load 10bytes from EMUL to the datain pointer. to be used below.
2477
2478 if ( (flags & FLAG_4B_UID_IN_DATA) == FLAG_4B_UID_IN_DATA) {
2479 memcpy(rUIDBCC1, datain, 4);
2480 _UID_LEN = 4;
2481 } else if ( (flags & FLAG_7B_UID_IN_DATA) == FLAG_7B_UID_IN_DATA) {
2482 memcpy(&rUIDBCC1[1], datain, 3);
2483 memcpy( rUIDBCC2, datain+3, 4);
2484 _UID_LEN = 7;
2485 } else if ( (flags & FLAG_10B_UID_IN_DATA) == FLAG_10B_UID_IN_DATA) {
2486 memcpy(&rUIDBCC1[1], datain, 3);
2487 memcpy(&rUIDBCC2[1], datain+3, 3);
2488 memcpy( rUIDBCC3, datain+6, 4);
2489 _UID_LEN = 10;
2490 }
2491
2492 switch (_UID_LEN) {
2493 case 4:
2494 sak_4[0] &= 0xFB;
2495 // save CUID
2496 cuid = bytes_to_num(rUIDBCC1, 4);
2497 // BCC
2498 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2499 if (MF_DBGLEVEL >= 2) {
2500 Dbprintf("4B UID: %02x%02x%02x%02x",
2501 rUIDBCC1[0],
2502 rUIDBCC1[1],
2503 rUIDBCC1[2],
2504 rUIDBCC1[3]
2505 );
2506 }
2507 break;
2508 case 7:
2509 atqa[0] |= 0x40;
2510 sak_7[0] &= 0xFB;
2511 // save CUID
2512 cuid = bytes_to_num(rUIDBCC2, 4);
2513 // CascadeTag, CT
2514 rUIDBCC1[0] = 0x88;
2515 // BCC
2516 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2517 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2518 if (MF_DBGLEVEL >= 2) {
2519 Dbprintf("7B UID: %02x %02x %02x %02x %02x %02x %02x",
2520 rUIDBCC1[1],
2521 rUIDBCC1[2],
2522 rUIDBCC1[3],
2523 rUIDBCC2[0],
2524 rUIDBCC2[1],
2525 rUIDBCC2[2],
2526 rUIDBCC2[3]
2527 );
2528 }
2529 break;
2530 case 10:
2531 atqa[0] |= 0x80;
2532 sak_10[0] &= 0xFB;
2533 // save CUID
2534 cuid = bytes_to_num(rUIDBCC3, 4);
2535 // CascadeTag, CT
2536 rUIDBCC1[0] = 0x88;
2537 rUIDBCC2[0] = 0x88;
2538 // BCC
2539 rUIDBCC1[4] = rUIDBCC1[0] ^ rUIDBCC1[1] ^ rUIDBCC1[2] ^ rUIDBCC1[3];
2540 rUIDBCC2[4] = rUIDBCC2[0] ^ rUIDBCC2[1] ^ rUIDBCC2[2] ^ rUIDBCC2[3];
2541 rUIDBCC3[4] = rUIDBCC3[0] ^ rUIDBCC3[1] ^ rUIDBCC3[2] ^ rUIDBCC3[3];
2542
2543 if (MF_DBGLEVEL >= 2) {
2544 Dbprintf("10B UID: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
2545 rUIDBCC1[1],
2546 rUIDBCC1[2],
2547 rUIDBCC1[3],
2548 rUIDBCC2[1],
2549 rUIDBCC2[2],
2550 rUIDBCC2[3],
2551 rUIDBCC3[0],
2552 rUIDBCC3[1],
2553 rUIDBCC3[2],
2554 rUIDBCC3[3]
2555 );
2556 }
2557 break;
2558 default:
2559 break;
2560 }
2561 // calc some crcs
2562 ComputeCrc14443(CRC_14443_A, sak_4, 1, &sak_4[1], &sak_4[2]);
2563 ComputeCrc14443(CRC_14443_A, sak_7, 1, &sak_7[1], &sak_7[2]);
2564 ComputeCrc14443(CRC_14443_A, sak_10, 1, &sak_10[1], &sak_10[2]);
2565
2566 // We need to listen to the high-frequency, peak-detected path.
2567 iso14443a_setup(FPGA_HF_ISO14443A_TAGSIM_LISTEN);
2568
2569 // free eventually allocated BigBuf memory but keep Emulator Memory
2570 BigBuf_free_keep_EM();
2571 clear_trace();
2572 set_tracing(TRUE);
2573
2574 bool finished = FALSE;
2575 while (!BUTTON_PRESS() && !finished && !usb_poll_validate_length()) {
2576 WDT_HIT();
2577
2578 // find reader field
2579 if (cardSTATE == MFEMUL_NOFIELD) {
2580 vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
2581 if (vHf > MF_MINFIELDV) {
2582 cardSTATE_TO_IDLE();
2583 LED_A_ON();
2584 }
2585 }
2586 if (cardSTATE == MFEMUL_NOFIELD) continue;
2587
2588 // Now, get data
2589 res = EmGetCmd(receivedCmd, &len, receivedCmd_par);
2590 if (res == 2) { //Field is off!
2591 cardSTATE = MFEMUL_NOFIELD;
2592 LEDsoff();
2593 continue;
2594 } else if (res == 1) {
2595 break; // return value 1 means button press
2596 }
2597
2598 // REQ or WUP request in ANY state and WUP in HALTED state
2599 // this if-statement doesn't match the specification above. (iceman)
2600 if (len == 1 && ((receivedCmd[0] == ISO14443A_CMD_REQA && cardSTATE != MFEMUL_HALTED) || receivedCmd[0] == ISO14443A_CMD_WUPA)) {
2601 selTimer = GetTickCount();
2602 EmSendCmdEx(atqa, sizeof(atqa), (receivedCmd[0] == ISO14443A_CMD_WUPA));
2603 cardSTATE = MFEMUL_SELECT1;
2604 crypto1_destroy(pcs);
2605 cardAUTHKEY = 0xff;
2606 LEDsoff();
2607 nonce = prand();
2608 continue;
2609 }
2610
2611 switch (cardSTATE) {
2612 case MFEMUL_NOFIELD:
2613 case MFEMUL_HALTED:
2614 case MFEMUL_IDLE:{
2615 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2616 break;
2617 }
2618 case MFEMUL_SELECT1:{
2619 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT && receivedCmd[1] == 0x20)) {
2620 if (MF_DBGLEVEL >= 4) Dbprintf("SELECT ALL received");
2621 EmSendCmd(rUIDBCC1, sizeof(rUIDBCC1));
2622 break;
2623 }
2624 // select card
2625 if (len == 9 &&
2626 ( receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT &&
2627 receivedCmd[1] == 0x70 &&
2628 memcmp(&receivedCmd[2], rUIDBCC1, 4) == 0)) {
2629
2630 // SAK 4b
2631 EmSendCmd(sak_4, sizeof(sak_4));
2632 switch(_UID_LEN){
2633 case 4:
2634 cardSTATE = MFEMUL_WORK;
2635 LED_B_ON();
2636 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol1 time: %d", GetTickCount() - selTimer);
2637 continue;
2638 case 7:
2639 case 10:
2640 cardSTATE = MFEMUL_SELECT2;
2641 continue;
2642 default:break;
2643 }
2644 } else {
2645 cardSTATE_TO_IDLE();
2646 }
2647 break;
2648 }
2649 case MFEMUL_SELECT2:{
2650 if (!len) {
2651 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2652 break;
2653 }
2654 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 && receivedCmd[1] == 0x20)) {
2655 EmSendCmd(rUIDBCC2, sizeof(rUIDBCC2));
2656 break;
2657 }
2658 if (len == 9 &&
2659 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_2 &&
2660 receivedCmd[1] == 0x70 &&
2661 memcmp(&receivedCmd[2], rUIDBCC2, 4) == 0) ) {
2662
2663 EmSendCmd(sak_7, sizeof(sak_7));
2664 switch(_UID_LEN){
2665 case 7:
2666 cardSTATE = MFEMUL_WORK;
2667 LED_B_ON();
2668 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol2 time: %d", GetTickCount() - selTimer);
2669 continue;
2670 case 10:
2671 cardSTATE = MFEMUL_SELECT3;
2672 continue;
2673 default:break;
2674 }
2675 }
2676 cardSTATE_TO_IDLE();
2677 break;
2678 }
2679 case MFEMUL_SELECT3:{
2680 if (!len) {
2681 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2682 break;
2683 }
2684 if (len == 2 && (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 && receivedCmd[1] == 0x20)) {
2685 EmSendCmd(rUIDBCC3, sizeof(rUIDBCC3));
2686 break;
2687 }
2688 if (len == 9 &&
2689 (receivedCmd[0] == ISO14443A_CMD_ANTICOLL_OR_SELECT_3 &&
2690 receivedCmd[1] == 0x70 &&
2691 memcmp(&receivedCmd[2], rUIDBCC3, 4) == 0) ) {
2692
2693 EmSendCmd(sak_10, sizeof(sak_10));
2694 cardSTATE = MFEMUL_WORK;
2695 LED_B_ON();
2696 if (MF_DBGLEVEL >= 4) Dbprintf("--> WORK. anticol3 time: %d", GetTickCount() - selTimer);
2697 break;
2698 }
2699 cardSTATE_TO_IDLE();
2700 break;
2701 }
2702 case MFEMUL_AUTH1:{
2703 if( len != 8) {
2704 cardSTATE_TO_IDLE();
2705 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2706 break;
2707 }
2708
2709 uint32_t nr = bytes_to_num(receivedCmd, 4);
2710 uint32_t ar = bytes_to_num(&receivedCmd[4], 4);
2711
2712 // Collect AR/NR per keytype & sector
2713 if ( (flags & FLAG_NR_AR_ATTACK) == FLAG_NR_AR_ATTACK ) {
2714
2715 int8_t index = -1;
2716 int8_t empty = -1;
2717 for (uint8_t i = 0; i < ATTACK_KEY_COUNT; i++) {
2718 // find which index to use
2719 if ( (cardAUTHSC == ar_nr_nonces[i].sector) && (cardAUTHKEY == ar_nr_nonces[i].keytype))
2720 index = i;
2721
2722 // keep track of empty slots.
2723 if ( ar_nr_nonces[i].state == EMPTY)
2724 empty = i;
2725 }
2726 // if no empty slots. Choose first and overwrite.
2727 if ( index == -1 ) {
2728 if ( empty == -1 ) {
2729 index = 0;
2730 ar_nr_nonces[index].state = EMPTY;
2731 } else {
2732 index = empty;
2733 }
2734 }
2735
2736 switch(ar_nr_nonces[index].state) {
2737 case EMPTY: {
2738 // first nonce collect
2739 ar_nr_nonces[index].cuid = cuid;
2740 ar_nr_nonces[index].sector = cardAUTHSC;
2741 ar_nr_nonces[index].keytype = cardAUTHKEY;
2742 ar_nr_nonces[index].nonce = nonce;
2743 ar_nr_nonces[index].nr = nr;
2744 ar_nr_nonces[index].ar = ar;
2745 ar_nr_nonces[index].state = FIRST;
2746 break;
2747 }
2748 case FIRST : {
2749 // second nonce collect
2750 ar_nr_nonces[index].nonce2 = nonce;
2751 ar_nr_nonces[index].nr2 = nr;
2752 ar_nr_nonces[index].ar2 = ar;
2753 ar_nr_nonces[index].state = SECOND;
2754
2755 // send to client
2756 cmd_send(CMD_ACK, CMD_SIMULATE_MIFARE_CARD, 0, 0, &ar_nr_nonces[index], sizeof(nonces_t));
2757
2758 ar_nr_nonces[index].state = EMPTY;
2759 ar_nr_nonces[index].sector = 0;
2760 ar_nr_nonces[index].keytype = 0;
2761 break;
2762 }
2763 default: break;
2764 }
2765 }
2766
2767 crypto1_word(pcs, nr , 1);
2768 uint32_t cardRr = ar ^ crypto1_word(pcs, 0, 0);
2769
2770 //test if auth OK
2771 if (cardRr != prng_successor(nonce, 64)){
2772
2773 if (MF_DBGLEVEL >= 3) {
2774 Dbprintf("AUTH FAILED for sector %d with key %c. [nr=%08x cardRr=%08x] [nt=%08x succ=%08x]"
2775 , cardAUTHSC
2776 , (cardAUTHKEY == 0) ? 'A' : 'B'
2777 , nr
2778 , cardRr
2779 , nonce // nt
2780 , prng_successor(nonce, 64)
2781 );
2782 }
2783 // Shouldn't we respond anything here?
2784 // Right now, we don't nack or anything, which causes the
2785 // reader to do a WUPA after a while. /Martin
2786 // -- which is the correct response. /piwi
2787 cardSTATE_TO_IDLE();
2788 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2789 break;
2790 }
2791
2792 ans = prng_successor(nonce, 96) ^ crypto1_word(pcs, 0, 0);
2793 num_to_bytes(ans, 4, rAUTH_AT);
2794 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2795 LED_C_ON();
2796
2797 if (MF_DBGLEVEL >= 1) {
2798 Dbprintf("AUTH COMPLETED for sector %d with key %c. time=%d",
2799 cardAUTHSC,
2800 cardAUTHKEY == 0 ? 'A' : 'B',
2801 GetTickCount() - authTimer
2802 );
2803 }
2804 cardSTATE = MFEMUL_WORK;
2805 break;
2806 }
2807 case MFEMUL_WORK:{
2808 if (len == 0) {
2809 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2810 break;
2811 }
2812 bool encrypted_data = (cardAUTHKEY != 0xFF) ;
2813
2814 if(encrypted_data)
2815 mf_crypto1_decrypt(pcs, receivedCmd, len);
2816
2817 if (len == 4 && (receivedCmd[0] == MIFARE_AUTH_KEYA ||
2818 receivedCmd[0] == MIFARE_AUTH_KEYB) ) {
2819
2820 authTimer = GetTickCount();
2821 cardAUTHSC = receivedCmd[1] / 4; // received block -> sector
2822 cardAUTHKEY = receivedCmd[0] & 0x1;
2823 crypto1_destroy(pcs);
2824
2825 // load key into crypto
2826 crypto1_create(pcs, emlGetKey(cardAUTHSC, cardAUTHKEY));
2827
2828 if (!encrypted_data) {
2829 // first authentication
2830 // Update crypto state init (UID ^ NONCE)
2831 crypto1_word(pcs, cuid ^ nonce, 0);
2832 num_to_bytes(nonce, 4, rAUTH_AT);
2833 } else {
2834 // nested authentication
2835 ans = nonce ^ crypto1_word(pcs, cuid ^ nonce, 0);
2836 num_to_bytes(ans, 4, rAUTH_AT);
2837
2838 if (MF_DBGLEVEL >= 3) Dbprintf("Reader doing nested authentication for block %d (0x%02x) with key %c", receivedCmd[1], receivedCmd[1], cardAUTHKEY == 0 ? 'A' : 'B');
2839 }
2840
2841 EmSendCmd(rAUTH_AT, sizeof(rAUTH_AT));
2842 cardSTATE = MFEMUL_AUTH1;
2843 break;
2844 }
2845
2846 // rule 13 of 7.5.3. in ISO 14443-4. chaining shall be continued
2847 // BUT... ACK --> NACK
2848 if (len == 1 && receivedCmd[0] == CARD_ACK) {
2849 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2850 break;
2851 }
2852
2853 // rule 12 of 7.5.3. in ISO 14443-4. R(NAK) --> R(ACK)
2854 if (len == 1 && receivedCmd[0] == CARD_NACK_NA) {
2855 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2856 break;
2857 }
2858
2859 if(len != 4) {
2860 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2861 break;
2862 }
2863
2864 if ( receivedCmd[0] == ISO14443A_CMD_READBLOCK ||
2865 receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK ||
2866 receivedCmd[0] == MIFARE_CMD_INC ||
2867 receivedCmd[0] == MIFARE_CMD_DEC ||
2868 receivedCmd[0] == MIFARE_CMD_RESTORE ||
2869 receivedCmd[0] == MIFARE_CMD_TRANSFER ) {
2870
2871 if (receivedCmd[1] >= 16 * 4) {
2872 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2873 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on out of range block: %d (0x%02x), nacking",receivedCmd[0],receivedCmd[1],receivedCmd[1]);
2874 break;
2875 }
2876
2877 if (receivedCmd[1] / 4 != cardAUTHSC) {
2878 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2879 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate (0x%02) on block (0x%02x) not authenticated for (0x%02x), nacking",receivedCmd[0],receivedCmd[1],cardAUTHSC);
2880 break;
2881 }
2882 }
2883 // read block
2884 if (receivedCmd[0] == ISO14443A_CMD_READBLOCK) {
2885 if (MF_DBGLEVEL >= 4) Dbprintf("Reader reading block %d (0x%02x)", receivedCmd[1], receivedCmd[1]);
2886
2887 emlGetMem(response, receivedCmd[1], 1);
2888 AppendCrc14443a(response, 16);
2889 mf_crypto1_encrypt(pcs, response, 18, response_par);
2890 EmSendCmdPar(response, 18, response_par);
2891 numReads++;
2892 if(exitAfterNReads > 0 && numReads >= exitAfterNReads) {
2893 Dbprintf("%d reads done, exiting", numReads);
2894 finished = true;
2895 }
2896 break;
2897 }
2898 // write block
2899 if (receivedCmd[0] == ISO14443A_CMD_WRITEBLOCK) {
2900 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0xA0 write block %d (%02x)", receivedCmd[1], receivedCmd[1]);
2901 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2902 cardSTATE = MFEMUL_WRITEBL2;
2903 cardWRBL = receivedCmd[1];
2904 break;
2905 }
2906 // increment, decrement, restore
2907 if ( receivedCmd[0] == MIFARE_CMD_INC ||
2908 receivedCmd[0] == MIFARE_CMD_DEC ||
2909 receivedCmd[0] == MIFARE_CMD_RESTORE) {
2910
2911 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x inc(0xC1)/dec(0xC0)/restore(0xC2) block %d (%02x)",receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2912
2913 if (emlCheckValBl(receivedCmd[1])) {
2914 if (MF_DBGLEVEL >= 4) Dbprintf("Reader tried to operate on block, but emlCheckValBl failed, nacking");
2915 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2916 break;
2917 }
2918 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2919 if (receivedCmd[0] == MIFARE_CMD_INC) cardSTATE = MFEMUL_INTREG_INC;
2920 if (receivedCmd[0] == MIFARE_CMD_DEC) cardSTATE = MFEMUL_INTREG_DEC;
2921 if (receivedCmd[0] == MIFARE_CMD_RESTORE) cardSTATE = MFEMUL_INTREG_REST;
2922 cardWRBL = receivedCmd[1];
2923 break;
2924 }
2925 // transfer
2926 if (receivedCmd[0] == MIFARE_CMD_TRANSFER) {
2927 if (MF_DBGLEVEL >= 4) Dbprintf("RECV 0x%02x transfer block %d (%02x)", receivedCmd[0], receivedCmd[1], receivedCmd[1]);
2928 if (emlSetValBl(cardINTREG, cardINTBLOCK, receivedCmd[1]))
2929 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2930 else
2931 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2932 break;
2933 }
2934 // halt
2935 if (receivedCmd[0] == ISO14443A_CMD_HALT && receivedCmd[1] == 0x00) {
2936 LED_B_OFF();
2937 LED_C_OFF();
2938 cardSTATE = MFEMUL_HALTED;
2939 if (MF_DBGLEVEL >= 4) Dbprintf("--> HALTED. Selected time: %d ms", GetTickCount() - selTimer);
2940 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2941 break;
2942 }
2943 // RATS
2944 if (receivedCmd[0] == ISO14443A_CMD_RATS) {
2945 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2946 break;
2947 }
2948 // command not allowed
2949 if (MF_DBGLEVEL >= 4) Dbprintf("Received command not allowed, nacking");
2950 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2951 break;
2952 }
2953 case MFEMUL_WRITEBL2:{
2954 if (len == 18) {
2955 mf_crypto1_decrypt(pcs, receivedCmd, len);
2956 emlSetMem(receivedCmd, cardWRBL, 1);
2957 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_ACK));
2958 cardSTATE = MFEMUL_WORK;
2959 } else {
2960 cardSTATE_TO_IDLE();
2961 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2962 }
2963 break;
2964 }
2965 case MFEMUL_INTREG_INC:{
2966 mf_crypto1_decrypt(pcs, receivedCmd, len);
2967 memcpy(&ans, receivedCmd, 4);
2968 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2969 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2970 cardSTATE_TO_IDLE();
2971 break;
2972 }
2973 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2974 cardINTREG = cardINTREG + ans;
2975 cardSTATE = MFEMUL_WORK;
2976 break;
2977 }
2978 case MFEMUL_INTREG_DEC:{
2979 mf_crypto1_decrypt(pcs, receivedCmd, len);
2980 memcpy(&ans, receivedCmd, 4);
2981 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2982 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2983 cardSTATE_TO_IDLE();
2984 break;
2985 }
2986 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
2987 cardINTREG = cardINTREG - ans;
2988 cardSTATE = MFEMUL_WORK;
2989 break;
2990 }
2991 case MFEMUL_INTREG_REST:{
2992 mf_crypto1_decrypt(pcs, receivedCmd, len);
2993 memcpy(&ans, receivedCmd, 4);
2994 if (emlGetValBl(&cardINTREG, &cardINTBLOCK, cardWRBL)) {
2995 EmSend4bit(mf_crypto1_encrypt4bit(pcs, CARD_NACK_NA));
2996 cardSTATE_TO_IDLE();
2997 break;
2998 }
2999 LogTrace(Uart.output, Uart.len, Uart.startTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.endTime*16 - DELAY_AIR2ARM_AS_TAG, Uart.parity, TRUE);
3000 cardSTATE = MFEMUL_WORK;
3001 break;
3002 }
3003 }
3004 }
3005
3006 if (MF_DBGLEVEL >= 1)
3007 Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
3008
3009 cmd_send(CMD_ACK,1,0,0,0,0); FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3010 LEDsoff();
3011 set_tracing(FALSE);
3012 }
3013
3014
3015 //-----------------------------------------------------------------------------
3016 // MIFARE sniffer.
3017 //
3018 // if no activity for 2sec, it sends the collected data to the client.
3019 //-----------------------------------------------------------------------------
3020 // "hf mf sniff"
3021 void RAMFUNC SniffMifare(uint8_t param) {
3022
3023 LEDsoff();
3024
3025 // free eventually allocated BigBuf memory
3026 BigBuf_free(); BigBuf_Clear_ext(false);
3027 clear_trace();
3028 set_tracing(TRUE);
3029
3030 // The command (reader -> tag) that we're receiving.
3031 uint8_t receivedCmd[MAX_MIFARE_FRAME_SIZE] = {0x00};
3032 uint8_t receivedCmdPar[MAX_MIFARE_PARITY_SIZE] = {0x00};
3033
3034 // The response (tag -> reader) that we're receiving.
3035 uint8_t receivedResponse[MAX_MIFARE_FRAME_SIZE] = {0x00};
3036 uint8_t receivedResponsePar[MAX_MIFARE_PARITY_SIZE] = {0x00};
3037
3038 iso14443a_setup(FPGA_HF_ISO14443A_SNIFFER);
3039
3040 // allocate the DMA buffer, used to stream samples from the FPGA
3041 // [iceman] is this sniffed data unsigned?
3042 uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
3043 uint8_t *data = dmaBuf;
3044 uint8_t previous_data = 0;
3045 int maxDataLen = 0;
3046 int dataLen = 0;
3047 bool ReaderIsActive = FALSE;
3048 bool TagIsActive = FALSE;
3049
3050 // Set up the demodulator for tag -> reader responses.
3051 DemodInit(receivedResponse, receivedResponsePar);
3052
3053 // Set up the demodulator for the reader -> tag commands
3054 UartInit(receivedCmd, receivedCmdPar);
3055
3056 // Setup and start DMA.
3057 // set transfer address and number of bytes. Start transfer.
3058 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3059 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3060 return;
3061 }
3062
3063 LED_D_OFF();
3064
3065 MfSniffInit();
3066
3067 // And now we loop, receiving samples.
3068 for(uint32_t sniffCounter = 0;; ) {
3069
3070 LED_A_ON();
3071 WDT_HIT();
3072
3073 if(BUTTON_PRESS()) {
3074 DbpString("cancelled by button");
3075 break;
3076 }
3077
3078 if ((sniffCounter & 0x0000FFFF) == 0) { // from time to time
3079 // check if a transaction is completed (timeout after 2000ms).
3080 // if yes, stop the DMA transfer and send what we have so far to the client
3081 if (MfSniffSend(2000)) {
3082 // Reset everything - we missed some sniffed data anyway while the DMA was stopped
3083 sniffCounter = 0;
3084 data = dmaBuf;
3085 maxDataLen = 0;
3086 ReaderIsActive = FALSE;
3087 TagIsActive = FALSE;
3088 // Setup and start DMA. set transfer address and number of bytes. Start transfer.
3089 if ( !FpgaSetupSscDma((uint8_t*) dmaBuf, DMA_BUFFER_SIZE) ){
3090 if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
3091 return;
3092 }
3093 }
3094 }
3095
3096 int register readBufDataP = data - dmaBuf; // number of bytes we have processed so far
3097 int register dmaBufDataP = DMA_BUFFER_SIZE - AT91C_BASE_PDC_SSC->PDC_RCR; // number of bytes already transferred
3098
3099 if (readBufDataP <= dmaBufDataP) // we are processing the same block of data which is currently being transferred
3100 dataLen = dmaBufDataP - readBufDataP; // number of bytes still to be processed
3101 else
3102 dataLen = DMA_BUFFER_SIZE - readBufDataP + dmaBufDataP; // number of bytes still to be processed
3103
3104 // test for length of buffer
3105 if(dataLen > maxDataLen) { // we are more behind than ever...
3106 maxDataLen = dataLen;
3107 if(dataLen > (9 * DMA_BUFFER_SIZE / 10)) {
3108 Dbprintf("blew circular buffer! dataLen=0x%x", dataLen);
3109 break;
3110 }
3111 }
3112 if(dataLen < 1) continue;
3113
3114 // primary buffer was stopped ( <-- we lost data!
3115 if (!AT91C_BASE_PDC_SSC->PDC_RCR) {
3116 AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) dmaBuf;
3117 AT91C_BASE_PDC_SSC->PDC_RCR = DMA_BUFFER_SIZE;
3118 Dbprintf("RxEmpty ERROR, data length:%d", dataLen); // temporary
3119 }
3120 // secondary buffer sets as primary, secondary buffer was stopped
3121 if (!AT91C_BASE_PDC_SSC->PDC_RNCR) {
3122 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
3123 AT91C_BASE_PDC_SSC->PDC_RNCR = DMA_BUFFER_SIZE;
3124 }
3125
3126 LED_A_OFF();
3127
3128 if (sniffCounter & 0x01) {
3129
3130 // no need to try decoding tag data if the reader is sending
3131 if(!TagIsActive) {
3132 uint8_t readerdata = (previous_data & 0xF0) | (*data >> 4);
3133 if(MillerDecoding(readerdata, (sniffCounter-1)*4)) {
3134 LED_C_INV();
3135
3136 if (MfSniffLogic(receivedCmd, Uart.len, Uart.parity, Uart.bitCount, TRUE)) break;
3137
3138 UartInit(receivedCmd, receivedCmdPar);
3139 DemodReset();
3140 }
3141 ReaderIsActive = (Uart.state != STATE_UNSYNCD);
3142 }
3143
3144 // no need to try decoding tag data if the reader is sending
3145 if(!ReaderIsActive) {
3146 uint8_t tagdata = (previous_data << 4) | (*data & 0x0F);
3147 if(ManchesterDecoding(tagdata, 0, (sniffCounter-1)*4)) {
3148 LED_C_INV();
3149
3150 if (MfSniffLogic(receivedResponse, Demod.len, Demod.parity, Demod.bitCount, FALSE)) break;
3151
3152 DemodReset();
3153 UartInit(receivedCmd, receivedCmdPar);
3154 }
3155 TagIsActive = (Demod.state != DEMOD_UNSYNCD);
3156 }
3157 }
3158
3159 previous_data = *data;
3160 sniffCounter++;
3161 data++;
3162
3163 if(data == dmaBuf + DMA_BUFFER_SIZE)
3164 data = dmaBuf;
3165
3166 } // main cycle
3167
3168 if (MF_DBGLEVEL >= 1) Dbprintf("maxDataLen=%x, Uart.state=%x, Uart.len=%x", maxDataLen, Uart.state, Uart.len);
3169
3170 FpgaDisableSscDma();
3171 MfSniffEnd();
3172 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
3173 LEDsoff();
3174 set_tracing(FALSE);
3175 }
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