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   1 //-----------------------------------------------------------------------------
   2 // For reading TI tags, we need to place the FPGA in pass through mode
   3 // and pass everything through to the ARM
   4 //-----------------------------------------------------------------------------
   5
   6 module lo_passthru(
   7         input pck_divclk,
   8         output pwr_lo, output pwr_hi,
   9         output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
  10         output adc_clk,
  11         output ssp_din, input ssp_dout,
  12         input cross_lo,
  13         output dbg
  14 );
  15
  16 // the antenna is modulated when ssp_dout = 1, when 0 the
  17 // antenna drivers stop modulating and go into listen mode
  18 assign pwr_oe3 = 1'b0;
  19 assign pwr_oe1 = ssp_dout;
  20 assign pwr_oe2 = ssp_dout;
  21 assign pwr_oe4 = ssp_dout;
  22 assign pwr_lo = pck_divclk && ssp_dout;
  23 assign pwr_hi = 1'b0;
  24 assign adc_clk = 1'b0;
  25 assign ssp_din = cross_lo;
  26 assign dbg = cross_lo;
  27
  28 endmodule