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1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18
19 /**
20 * Does the sample acquisition. If threshold is specified, the actual sampling
21 * is not commenced until the threshold has been reached.
22 * @param trigger_threshold - the threshold
23 * @param silent - is true, now outputs are made. If false, dbprints the status
24 */
25 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
26 {
27 uint8_t *dest = (uint8_t *)BigBuf;
28 int n = sizeof(BigBuf);
29 int i;
30
31 memset(dest, 0, n);
32 i = 0;
33 for(;;) {
34 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
35 AT91C_BASE_SSC->SSC_THR = 0x43;
36 LED_D_ON();
37 }
38 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
39 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
40 LED_D_OFF();
41 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
42 continue;
43 else
44 trigger_threshold = -1;
45 if (++i >= n) break;
46 }
47 }
48 if(!silent)
49 {
50 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
51 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
52
53 }
54 }
55 /**
56 * Perform sample aquisition.
57 */
58 void DoAcquisition125k(int trigger_threshold)
59 {
60 DoAcquisition125k_internal(trigger_threshold, false);
61 }
62
63 /**
64 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
65 * if not already loaded, sets divisor and starts up the antenna.
66 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
67 * 0 or 95 ==> 125 KHz
68 *
69 **/
70 void LFSetupFPGAForADC(int divisor, bool lf_field)
71 {
72 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
73 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
74 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
75 else if (divisor == 0)
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
77 else
78 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
79
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
81
82 // Connect the A/D to the peak-detected low-frequency path.
83 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
84 // Give it a bit of time for the resonant antenna to settle.
85 SpinDelay(50);
86 // Now set up the SSC to get the ADC samples that are now streaming at us.
87 FpgaSetupSsc();
88 }
89 /**
90 * Initializes the FPGA, and acquires the samples.
91 **/
92 void AcquireRawAdcSamples125k(int divisor)
93 {
94 LFSetupFPGAForADC(divisor, true);
95 // Now call the acquisition routine
96 DoAcquisition125k_internal(-1,false);
97 }
98 /**
99 * Initializes the FPGA for snoop-mode, and acquires the samples.
100 **/
101
102 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
103 {
104 LFSetupFPGAForADC(divisor, false);
105 DoAcquisition125k(trigger_threshold);
106 }
107
108 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
109 {
110
111 /* Make sure the tag is reset */
112 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
114 SpinDelay(2500);
115
116
117 int divisor_used = 95; // 125 KHz
118 // see if 'h' was specified
119
120 if (command[strlen((char *) command) - 1] == 'h')
121 divisor_used = 88; // 134.8 KHz
122
123
124 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
126 // Give it a bit of time for the resonant antenna to settle.
127 SpinDelay(50);
128
129 // And a little more time for the tag to fully power up
130 SpinDelay(2000);
131
132 // Now set up the SSC to get the ADC samples that are now streaming at us.
133 FpgaSetupSsc();
134
135 // now modulate the reader field
136 while(*command != '\0' && *command != ' ') {
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
138 LED_D_OFF();
139 SpinDelayUs(delay_off);
140 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
141
142 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
143 LED_D_ON();
144 if(*(command++) == '0')
145 SpinDelayUs(period_0);
146 else
147 SpinDelayUs(period_1);
148 }
149 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
150 LED_D_OFF();
151 SpinDelayUs(delay_off);
152 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
153
154 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
155
156 // now do the read
157 DoAcquisition125k(-1);
158 }
159
160 /* blank r/w tag data stream
161 ...0000000000000000 01111111
162 1010101010101010101010101010101010101010101010101010101010101010
163 0011010010100001
164 01111111
165 101010101010101[0]000...
166
167 [5555fe852c5555555555555555fe0000]
168 */
169 void ReadTItag(void)
170 {
171 // some hardcoded initial params
172 // when we read a TI tag we sample the zerocross line at 2Mhz
173 // TI tags modulate a 1 as 16 cycles of 123.2Khz
174 // TI tags modulate a 0 as 16 cycles of 134.2Khz
175 #define FSAMPLE 2000000
176 #define FREQLO 123200
177 #define FREQHI 134200
178
179 signed char *dest = (signed char *)BigBuf;
180 int n = sizeof(BigBuf);
181 // int *dest = GraphBuffer;
182 // int n = GraphTraceLen;
183
184 // 128 bit shift register [shift3:shift2:shift1:shift0]
185 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
186
187 int i, cycles=0, samples=0;
188 // how many sample points fit in 16 cycles of each frequency
189 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
190 // when to tell if we're close enough to one freq or another
191 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
192
193 // TI tags charge at 134.2Khz
194 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
195 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
196
197 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
198 // connects to SSP_DIN and the SSP_DOUT logic level controls
199 // whether we're modulating the antenna (high)
200 // or listening to the antenna (low)
201 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
202
203 // get TI tag data into the buffer
204 AcquireTiType();
205
206 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
207
208 for (i=0; i<n-1; i++) {
209 // count cycles by looking for lo to hi zero crossings
210 if ( (dest[i]<0) && (dest[i+1]>0) ) {
211 cycles++;
212 // after 16 cycles, measure the frequency
213 if (cycles>15) {
214 cycles=0;
215 samples=i-samples; // number of samples in these 16 cycles
216
217 // TI bits are coming to us lsb first so shift them
218 // right through our 128 bit right shift register
219 shift0 = (shift0>>1) | (shift1 << 31);
220 shift1 = (shift1>>1) | (shift2 << 31);
221 shift2 = (shift2>>1) | (shift3 << 31);
222 shift3 >>= 1;
223
224 // check if the cycles fall close to the number
225 // expected for either the low or high frequency
226 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
227 // low frequency represents a 1
228 shift3 |= (1<<31);
229 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
230 // high frequency represents a 0
231 } else {
232 // probably detected a gay waveform or noise
233 // use this as gaydar or discard shift register and start again
234 shift3 = shift2 = shift1 = shift0 = 0;
235 }
236 samples = i;
237
238 // for each bit we receive, test if we've detected a valid tag
239
240 // if we see 17 zeroes followed by 6 ones, we might have a tag
241 // remember the bits are backwards
242 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
243 // if start and end bytes match, we have a tag so break out of the loop
244 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
245 cycles = 0xF0B; //use this as a flag (ugly but whatever)
246 break;
247 }
248 }
249 }
250 }
251 }
252
253 // if flag is set we have a tag
254 if (cycles!=0xF0B) {
255 DbpString("Info: No valid tag detected.");
256 } else {
257 // put 64 bit data into shift1 and shift0
258 shift0 = (shift0>>24) | (shift1 << 8);
259 shift1 = (shift1>>24) | (shift2 << 8);
260
261 // align 16 bit crc into lower half of shift2
262 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
263
264 // if r/w tag, check ident match
265 if ( shift3&(1<<15) ) {
266 DbpString("Info: TI tag is rewriteable");
267 // only 15 bits compare, last bit of ident is not valid
268 if ( ((shift3>>16)^shift0)&0x7fff ) {
269 DbpString("Error: Ident mismatch!");
270 } else {
271 DbpString("Info: TI tag ident is valid");
272 }
273 } else {
274 DbpString("Info: TI tag is readonly");
275 }
276
277 // WARNING the order of the bytes in which we calc crc below needs checking
278 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
279 // bytes in reverse or something
280 // calculate CRC
281 uint32_t crc=0;
282
283 crc = update_crc16(crc, (shift0)&0xff);
284 crc = update_crc16(crc, (shift0>>8)&0xff);
285 crc = update_crc16(crc, (shift0>>16)&0xff);
286 crc = update_crc16(crc, (shift0>>24)&0xff);
287 crc = update_crc16(crc, (shift1)&0xff);
288 crc = update_crc16(crc, (shift1>>8)&0xff);
289 crc = update_crc16(crc, (shift1>>16)&0xff);
290 crc = update_crc16(crc, (shift1>>24)&0xff);
291
292 Dbprintf("Info: Tag data: %x%08x, crc=%x",
293 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
294 if (crc != (shift2&0xffff)) {
295 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
296 } else {
297 DbpString("Info: CRC is good");
298 }
299 }
300 }
301
302 void WriteTIbyte(uint8_t b)
303 {
304 int i = 0;
305
306 // modulate 8 bits out to the antenna
307 for (i=0; i<8; i++)
308 {
309 if (b&(1<<i)) {
310 // stop modulating antenna
311 LOW(GPIO_SSC_DOUT);
312 SpinDelayUs(1000);
313 // modulate antenna
314 HIGH(GPIO_SSC_DOUT);
315 SpinDelayUs(1000);
316 } else {
317 // stop modulating antenna
318 LOW(GPIO_SSC_DOUT);
319 SpinDelayUs(300);
320 // modulate antenna
321 HIGH(GPIO_SSC_DOUT);
322 SpinDelayUs(1700);
323 }
324 }
325 }
326
327 void AcquireTiType(void)
328 {
329 int i, j, n;
330 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
331 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
332 #define TIBUFLEN 1250
333
334 // clear buffer
335 memset(BigBuf,0,sizeof(BigBuf));
336
337 // Set up the synchronous serial port
338 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
339 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
346 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
347
348 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
349 // 48/2 = 24 MHz clock must be divided by 12
350 AT91C_BASE_SSC->SSC_CMR = 12;
351
352 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
353 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
354 AT91C_BASE_SSC->SSC_TCMR = 0;
355 AT91C_BASE_SSC->SSC_TFMR = 0;
356
357 LED_D_ON();
358
359 // modulate antenna
360 HIGH(GPIO_SSC_DOUT);
361
362 // Charge TI tag for 50ms.
363 SpinDelay(50);
364
365 // stop modulating antenna and listen
366 LOW(GPIO_SSC_DOUT);
367
368 LED_D_OFF();
369
370 i = 0;
371 for(;;) {
372 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
373 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
374 i++; if(i >= TIBUFLEN) break;
375 }
376 WDT_HIT();
377 }
378
379 // return stolen pin to SSP
380 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
381 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
382
383 char *dest = (char *)BigBuf;
384 n = TIBUFLEN*32;
385 // unpack buffer
386 for (i=TIBUFLEN-1; i>=0; i--) {
387 for (j=0; j<32; j++) {
388 if(BigBuf[i] & (1 << j)) {
389 dest[--n] = 1;
390 } else {
391 dest[--n] = -1;
392 }
393 }
394 }
395 }
396
397 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
398 // if crc provided, it will be written with the data verbatim (even if bogus)
399 // if not provided a valid crc will be computed from the data and written.
400 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
401 {
402 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
403 if(crc == 0) {
404 crc = update_crc16(crc, (idlo)&0xff);
405 crc = update_crc16(crc, (idlo>>8)&0xff);
406 crc = update_crc16(crc, (idlo>>16)&0xff);
407 crc = update_crc16(crc, (idlo>>24)&0xff);
408 crc = update_crc16(crc, (idhi)&0xff);
409 crc = update_crc16(crc, (idhi>>8)&0xff);
410 crc = update_crc16(crc, (idhi>>16)&0xff);
411 crc = update_crc16(crc, (idhi>>24)&0xff);
412 }
413 Dbprintf("Writing to tag: %x%08x, crc=%x",
414 (unsigned int) idhi, (unsigned int) idlo, crc);
415
416 // TI tags charge at 134.2Khz
417 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
418 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
419 // connects to SSP_DIN and the SSP_DOUT logic level controls
420 // whether we're modulating the antenna (high)
421 // or listening to the antenna (low)
422 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
423 LED_A_ON();
424
425 // steal this pin from the SSP and use it to control the modulation
426 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
427 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
428
429 // writing algorithm:
430 // a high bit consists of a field off for 1ms and field on for 1ms
431 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
432 // initiate a charge time of 50ms (field on) then immediately start writing bits
433 // start by writing 0xBB (keyword) and 0xEB (password)
434 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
435 // finally end with 0x0300 (write frame)
436 // all data is sent lsb firts
437 // finish with 15ms programming time
438
439 // modulate antenna
440 HIGH(GPIO_SSC_DOUT);
441 SpinDelay(50); // charge time
442
443 WriteTIbyte(0xbb); // keyword
444 WriteTIbyte(0xeb); // password
445 WriteTIbyte( (idlo )&0xff );
446 WriteTIbyte( (idlo>>8 )&0xff );
447 WriteTIbyte( (idlo>>16)&0xff );
448 WriteTIbyte( (idlo>>24)&0xff );
449 WriteTIbyte( (idhi )&0xff );
450 WriteTIbyte( (idhi>>8 )&0xff );
451 WriteTIbyte( (idhi>>16)&0xff );
452 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
453 WriteTIbyte( (crc )&0xff ); // crc lo
454 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
455 WriteTIbyte(0x00); // write frame lo
456 WriteTIbyte(0x03); // write frame hi
457 HIGH(GPIO_SSC_DOUT);
458 SpinDelay(50); // programming time
459
460 LED_A_OFF();
461
462 // get TI tag data into the buffer
463 AcquireTiType();
464
465 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
466 DbpString("Now use tiread to check");
467 }
468
469 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
470 {
471 int i;
472 uint8_t *tab = (uint8_t *)BigBuf;
473
474 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
475 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
476
477 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
478
479 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
480 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
481
482 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
483 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
484
485 i = 0;
486 for(;;) {
487 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
488 if(BUTTON_PRESS()) {
489 DbpString("Stopped");
490 return;
491 }
492 WDT_HIT();
493 }
494
495 if (ledcontrol)
496 LED_D_ON();
497
498 if(tab[i])
499 OPEN_COIL();
500 else
501 SHORT_COIL();
502
503 if (ledcontrol)
504 LED_D_OFF();
505
506 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
507 if(BUTTON_PRESS()) {
508 DbpString("Stopped");
509 return;
510 }
511 WDT_HIT();
512 }
513
514 i++;
515 if(i == period) {
516 i = 0;
517 if (gap) {
518 SHORT_COIL();
519 SpinDelayUs(gap);
520 }
521 }
522 }
523 }
524
525 #define DEBUG_FRAME_CONTENTS 1
526 void SimulateTagLowFrequencyBidir(int divisor, int t0)
527 {
528 }
529
530 // compose fc/8 fc/10 waveform
531 static void fc(int c, int *n) {
532 uint8_t *dest = (uint8_t *)BigBuf;
533 int idx;
534
535 // for when we want an fc8 pattern every 4 logical bits
536 if(c==0) {
537 dest[((*n)++)]=1;
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 }
546 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
547 if(c==8) {
548 for (idx=0; idx<6; idx++) {
549 dest[((*n)++)]=1;
550 dest[((*n)++)]=1;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 }
558 }
559
560 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
561 if(c==10) {
562 for (idx=0; idx<5; idx++) {
563 dest[((*n)++)]=1;
564 dest[((*n)++)]=1;
565 dest[((*n)++)]=1;
566 dest[((*n)++)]=0;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 dest[((*n)++)]=0;
572 dest[((*n)++)]=0;
573 }
574 }
575 }
576
577 // prepare a waveform pattern in the buffer based on the ID given then
578 // simulate a HID tag until the button is pressed
579 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
580 {
581 int n=0, i=0;
582 /*
583 HID tag bitstream format
584 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
585 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
586 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
587 A fc8 is inserted before every 4 bits
588 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
589 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
590 */
591
592 if (hi>0xFFF) {
593 DbpString("Tags can only have 44 bits.");
594 return;
595 }
596 fc(0,&n);
597 // special start of frame marker containing invalid bit sequences
598 fc(8, &n); fc(8, &n); // invalid
599 fc(8, &n); fc(10, &n); // logical 0
600 fc(10, &n); fc(10, &n); // invalid
601 fc(8, &n); fc(10, &n); // logical 0
602
603 WDT_HIT();
604 // manchester encode bits 43 to 32
605 for (i=11; i>=0; i--) {
606 if ((i%4)==3) fc(0,&n);
607 if ((hi>>i)&1) {
608 fc(10, &n); fc(8, &n); // low-high transition
609 } else {
610 fc(8, &n); fc(10, &n); // high-low transition
611 }
612 }
613
614 WDT_HIT();
615 // manchester encode bits 31 to 0
616 for (i=31; i>=0; i--) {
617 if ((i%4)==3) fc(0,&n);
618 if ((lo>>i)&1) {
619 fc(10, &n); fc(8, &n); // low-high transition
620 } else {
621 fc(8, &n); fc(10, &n); // high-low transition
622 }
623 }
624
625 if (ledcontrol)
626 LED_A_ON();
627 SimulateTagLowFrequency(n, 0, ledcontrol);
628
629 if (ledcontrol)
630 LED_A_OFF();
631 }
632
633 //translate wave to 11111100000 (1 for each short wave 0 for each long wave)
634 size_t fsk_demod(uint8_t * dest, size_t size)
635 {
636 uint32_t last_transition = 0;
637 uint32_t idx = 1;
638 uint32_t maxVal=0;
639 // // we don't care about actual value, only if it's more or less than a
640 // // threshold essentially we capture zero crossings for later analysis
641
642 // we do care about the actual value as sometimes near the center of the
643 // wave we may get static that changes direction of wave for one value
644 // if our value is too low it might affect the read. and if our tag or
645 // antenna is weak a setting too high might not see anything. [marshmellow]
646 if (size<100) return size;
647 for(idx=1; idx<100; idx++){
648 if(maxVal<dest[idx]) maxVal = dest[idx];
649 }
650 // set close to the top of the wave threshold with 13% margin for error
651 // less likely to get a false transition up there.
652 // (but have to be careful not to go too high and miss some short waves)
653 uint32_t threshold_value = (uint32_t)(maxVal*.87); idx=1;
654 //uint8_t threshold_value = 127;
655
656 // sync to first lo-hi transition, and threshold
657
658 // Need to threshold first sample
659 if(dest[0] < threshold_value) dest[0] = 0;
660 else dest[0] = 1;
661
662 size_t numBits = 0;
663 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
664 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
665 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
666 for(idx = 1; idx < size; idx++) {
667 // threshold current value
668 if (dest[idx] < threshold_value) dest[idx] = 0;
669 else dest[idx] = 1;
670
671 // Check for 0->1 transition
672 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
673 if (idx-last_transition<6){
674 //do nothing with extra garbage
675 } else if (idx-last_transition < 9) {
676 dest[numBits]=1;
677 } else {
678 dest[numBits]=0;
679 }
680 last_transition = idx;
681 numBits++;
682 }
683 }
684 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
685 }
686
687 uint32_t myround(float f)
688 {
689 if (f >= 2000) return 2000;//something bad happened
690 return (uint32_t) (f + (float)0.5);
691 }
692
693 //translate 11111100000 to 10
694 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t rfLen, uint8_t maxConsequtiveBits, uint8_t invert )// uint8_t h2l_crossing_value,uint8_t l2h_crossing_value,
695 {
696 uint8_t lastval=dest[0];
697 uint32_t idx=0;
698 size_t numBits=0;
699 uint32_t n=1;
700
701 for( idx=1; idx < size; idx++) {
702
703 if (dest[idx]==lastval) {
704 n++;
705 continue;
706 }
707 //if lastval was 1, we have a 1->0 crossing
708 if ( dest[idx-1]==1 ) {
709 n=myround((float)(n+1)/((float)(rfLen)/(float)8));
710 //n=(n+1) / h2l_crossing_value;
711 } else {// 0->1 crossing
712 n=myround((float)(n+1)/((float)(rfLen-2)/(float)10));
713 //n=(n+1) / l2h_crossing_value;
714 }
715 if (n == 0) n = 1;
716
717 if(n < maxConsequtiveBits) //Consecutive
718 {
719 if(invert==0){ //invert bits
720 memset(dest+numBits, dest[idx-1] , n);
721 }else{
722 memset(dest+numBits, dest[idx-1]^1 , n);
723 }
724 numBits += n;
725 }
726 n=0;
727 lastval=dest[idx];
728 }//end for
729 return numBits;
730 }
731 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
732 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
733 {
734 uint8_t *dest = (uint8_t *)BigBuf;
735
736 size_t size=0,idx=0; //, found=0;
737 uint32_t hi2=0, hi=0, lo=0;
738
739 // Configure to go in 125Khz listen mode
740 LFSetupFPGAForADC(95, true);
741
742 while(!BUTTON_PRESS()) {
743
744 WDT_HIT();
745 if (ledcontrol) LED_A_ON();
746
747 DoAcquisition125k_internal(-1,true);
748 size = sizeof(BigBuf);
749 if (size < 2000) continue;
750 // FSK demodulator
751 size = fsk_demod(dest, size);
752
753 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
754 // 1->0 : fc/8 in sets of 6 (RF/50 / 8 = 6.25)
755 // 0->1 : fc/10 in sets of 5 (RF/50 / 10= 5)
756 // do not invert
757 size = aggregate_bits(dest,size, 50,5,0); //6,5,5,0
758
759 WDT_HIT();
760
761 // final loop, go over previously decoded manchester data and decode into usable tag ID
762 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
763 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
764 int numshifts = 0;
765 idx = 0;
766 //one scan
767 uint8_t sameCardCount =0;
768 while( idx + sizeof(frame_marker_mask) < size) {
769 // search for a start of frame marker
770 if (sameCardCount>2) break; //only up to 2 valid sets of data for the same read of looping card data
771 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
772 { // frame marker found
773 idx+=sizeof(frame_marker_mask);
774 while(dest[idx] != dest[idx+1] && idx < size-2)
775 {
776 // Keep going until next frame marker (or error)
777 // Shift in a bit. Start by shifting high registers
778 hi2 = (hi2<<1)|(hi>>31);
779 hi = (hi<<1)|(lo>>31);
780 //Then, shift in a 0 or one into low
781 if (dest[idx] && !dest[idx+1]) // 1 0
782 lo=(lo<<1)|0;
783 else // 0 1
784 lo=(lo<<1)|
785 1;
786 numshifts++;
787 idx += 2;
788 }
789 //Dbprintf("Num shifts: %d ", numshifts);
790 // Hopefully, we read a tag and hit upon the next frame marker
791 if(idx + sizeof(frame_marker_mask) < size)
792 {
793 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
794 {
795 if (hi2 != 0){ //extra large HID tags
796 Dbprintf("TAG ID: %x%08x%08x (%d)",
797 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
798 }
799 else { //standard HID tags <38 bits
800 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
801 uint8_t bitlen = 0;
802 uint32_t fc = 0;
803 uint32_t cardnum = 0;
804 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
805 uint32_t lo2=0;
806 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
807 uint8_t idx3 = 1;
808 while(lo2>1){ //find last bit set to 1 (format len bit)
809 lo2=lo2>>1;
810 idx3++;
811 }
812 bitlen =idx3+19;
813 fc =0;
814 cardnum=0;
815 if(bitlen==26){
816 cardnum = (lo>>1)&0xFFFF;
817 fc = (lo>>17)&0xFF;
818 }
819 if(bitlen==37){
820 cardnum = (lo>>1)&0x7FFFF;
821 fc = ((hi&0xF)<<12)|(lo>>20);
822 }
823 if(bitlen==34){
824 cardnum = (lo>>1)&0xFFFF;
825 fc= ((hi&1)<<15)|(lo>>17);
826 }
827 if(bitlen==35){
828 cardnum = (lo>>1)&0xFFFFF;
829 fc = ((hi&1)<<11)|(lo>>21);
830 }
831 }
832 else { //if bit 38 is not set then 37 bit format is used
833 bitlen= 37;
834 fc =0;
835 cardnum=0;
836 if(bitlen==37){
837 cardnum = (lo>>1)&0x7FFFF;
838 fc = ((hi&0xF)<<12)|(lo>>20);
839 }
840 }
841 //Dbprintf("TAG ID: %x%08x (%d)",
842 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
843 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
844 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
845 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
846 }
847 sameCardCount++;
848 if (findone){
849 if (ledcontrol) LED_A_OFF();
850 return;
851 }
852 }
853 }
854 // reset
855 hi2 = hi = lo = 0;
856 numshifts = 0;
857 }else
858 {
859 idx++;
860 }
861 }
862 WDT_HIT();
863
864 }
865 DbpString("Stopped");
866 if (ledcontrol) LED_A_OFF();
867 }
868
869 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
870 {
871 uint32_t num = 0;
872 for(int i = 0 ; i < numbits ; i++)
873 {
874 num = (num << 1) | (*src);
875 src++;
876 }
877 return num;
878 }
879
880 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
881 {
882 uint8_t *dest = (uint8_t *)BigBuf;
883 size_t size=0, idx=0;
884 uint32_t code=0, code2=0;
885
886 // Configure to go in 125Khz listen mode
887 LFSetupFPGAForADC(95, true);
888
889 while(!BUTTON_PRESS()) {
890 WDT_HIT();
891 if (ledcontrol) LED_A_ON();
892 DoAcquisition125k_internal(-1,true);
893 size = sizeof(BigBuf);
894 //make sure buffer has data
895 if (size < 64) return;
896 //test samples are not just noise
897 uint8_t testMax=0;
898 for(idx=0;idx<64;idx++){
899 if (testMax<dest[idx]) testMax=dest[idx];
900 }
901 idx=0;
902 //if not just noise
903 if (testMax>170){
904 //Dbprintf("testMax: %d",testMax);
905 // FSK demodulator
906 size = fsk_demod(dest, size);
907 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
908 // 1->0 : fc/8 in sets of 7 (RF/64 / 8 = 8)
909 // 0->1 : fc/10 in sets of 6 (RF/64 / 10 = 6.4)
910 size = aggregate_bits(dest, size, 64, 13, 1); //13 max Consecutive should be ok as most 0s in row should be 10 for init seq - invert bits
911 WDT_HIT();
912 //Index map
913 //0 10 20 30 40 50 60
914 //| | | | | | |
915 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
916 //-----------------------------------------------------------------------------
917 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
918 //
919 //XSF(version)facility:codeone+codetwo
920 //Handle the data
921 uint8_t sameCardCount=0;
922 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
923 for( idx=0; idx < (size - 74); idx++) {
924 if (sameCardCount>2) break;
925 if ( memcmp(dest + idx, mask, sizeof(mask))==0) {
926 //frame marker found
927 if (!dest[idx+8] && dest[idx+17]==1 && dest[idx+26]==1 && dest[idx+35]==1 && dest[idx+44]==1 && dest[idx+53]==1){
928 //confirmed proper separator bits found
929 if(findone){ //only print binary if we are doing one
930 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
931 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
932 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
933 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
934 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
935 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
936 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
937 }
938 code = bytebits_to_byte(dest+idx,32);
939 code2 = bytebits_to_byte(dest+idx+32,32);
940 short version = bytebits_to_byte(dest+idx+27,8); //14,4
941 uint8_t facilitycode = bytebits_to_byte(dest+idx+19,8) ;
942 uint16_t number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
943
944 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,facilitycode,number,code,code2);
945 // if we're only looking for one tag
946 if (findone){
947 if (ledcontrol) LED_A_OFF();
948 //LED_A_OFF();
949 return;
950 }
951 sameCardCount++;
952 }
953 }
954 }
955 }
956 WDT_HIT();
957 }
958 DbpString("Stopped");
959 if (ledcontrol) LED_A_OFF();
960 }
961
962 /*------------------------------
963 * T5555/T5557/T5567 routines
964 *------------------------------
965 */
966
967 /* T55x7 configuration register definitions */
968 #define T55x7_POR_DELAY 0x00000001
969 #define T55x7_ST_TERMINATOR 0x00000008
970 #define T55x7_PWD 0x00000010
971 #define T55x7_MAXBLOCK_SHIFT 5
972 #define T55x7_AOR 0x00000200
973 #define T55x7_PSKCF_RF_2 0
974 #define T55x7_PSKCF_RF_4 0x00000400
975 #define T55x7_PSKCF_RF_8 0x00000800
976 #define T55x7_MODULATION_DIRECT 0
977 #define T55x7_MODULATION_PSK1 0x00001000
978 #define T55x7_MODULATION_PSK2 0x00002000
979 #define T55x7_MODULATION_PSK3 0x00003000
980 #define T55x7_MODULATION_FSK1 0x00004000
981 #define T55x7_MODULATION_FSK2 0x00005000
982 #define T55x7_MODULATION_FSK1a 0x00006000
983 #define T55x7_MODULATION_FSK2a 0x00007000
984 #define T55x7_MODULATION_MANCHESTER 0x00008000
985 #define T55x7_MODULATION_BIPHASE 0x00010000
986 #define T55x7_BITRATE_RF_8 0
987 #define T55x7_BITRATE_RF_16 0x00040000
988 #define T55x7_BITRATE_RF_32 0x00080000
989 #define T55x7_BITRATE_RF_40 0x000C0000
990 #define T55x7_BITRATE_RF_50 0x00100000
991 #define T55x7_BITRATE_RF_64 0x00140000
992 #define T55x7_BITRATE_RF_100 0x00180000
993 #define T55x7_BITRATE_RF_128 0x001C0000
994
995 /* T5555 (Q5) configuration register definitions */
996 #define T5555_ST_TERMINATOR 0x00000001
997 #define T5555_MAXBLOCK_SHIFT 0x00000001
998 #define T5555_MODULATION_MANCHESTER 0
999 #define T5555_MODULATION_PSK1 0x00000010
1000 #define T5555_MODULATION_PSK2 0x00000020
1001 #define T5555_MODULATION_PSK3 0x00000030
1002 #define T5555_MODULATION_FSK1 0x00000040
1003 #define T5555_MODULATION_FSK2 0x00000050
1004 #define T5555_MODULATION_BIPHASE 0x00000060
1005 #define T5555_MODULATION_DIRECT 0x00000070
1006 #define T5555_INVERT_OUTPUT 0x00000080
1007 #define T5555_PSK_RF_2 0
1008 #define T5555_PSK_RF_4 0x00000100
1009 #define T5555_PSK_RF_8 0x00000200
1010 #define T5555_USE_PWD 0x00000400
1011 #define T5555_USE_AOR 0x00000800
1012 #define T5555_BITRATE_SHIFT 12
1013 #define T5555_FAST_WRITE 0x00004000
1014 #define T5555_PAGE_SELECT 0x00008000
1015
1016 /*
1017 * Relevant times in microsecond
1018 * To compensate antenna falling times shorten the write times
1019 * and enlarge the gap ones.
1020 */
1021 #define START_GAP 250
1022 #define WRITE_GAP 160
1023 #define WRITE_0 144 // 192
1024 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
1025
1026 // Write one bit to card
1027 void T55xxWriteBit(int bit)
1028 {
1029 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1030 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1031 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1032 if (bit == 0)
1033 SpinDelayUs(WRITE_0);
1034 else
1035 SpinDelayUs(WRITE_1);
1036 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1037 SpinDelayUs(WRITE_GAP);
1038 }
1039
1040 // Write one card block in page 0, no lock
1041 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1042 {
1043 //unsigned int i; //enio adjustment 12/10/14
1044 uint32_t i;
1045
1046 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1047 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1048 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1049
1050 // Give it a bit of time for the resonant antenna to settle.
1051 // And for the tag to fully power up
1052 SpinDelay(150);
1053
1054 // Now start writting
1055 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1056 SpinDelayUs(START_GAP);
1057
1058 // Opcode
1059 T55xxWriteBit(1);
1060 T55xxWriteBit(0); //Page 0
1061 if (PwdMode == 1){
1062 // Pwd
1063 for (i = 0x80000000; i != 0; i >>= 1)
1064 T55xxWriteBit(Pwd & i);
1065 }
1066 // Lock bit
1067 T55xxWriteBit(0);
1068
1069 // Data
1070 for (i = 0x80000000; i != 0; i >>= 1)
1071 T55xxWriteBit(Data & i);
1072
1073 // Block
1074 for (i = 0x04; i != 0; i >>= 1)
1075 T55xxWriteBit(Block & i);
1076
1077 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1078 // so wait a little more)
1079 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1080 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1081 SpinDelay(20);
1082 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1083 }
1084
1085 // Read one card block in page 0
1086 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1087 {
1088 uint8_t *dest = (uint8_t *)BigBuf;
1089 //int m=0, i=0; //enio adjustment 12/10/14
1090 uint32_t m=0, i=0;
1091 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1092 m = sizeof(BigBuf);
1093 // Clear destination buffer before sending the command
1094 memset(dest, 128, m);
1095 // Connect the A/D to the peak-detected low-frequency path.
1096 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1097 // Now set up the SSC to get the ADC samples that are now streaming at us.
1098 FpgaSetupSsc();
1099
1100 LED_D_ON();
1101 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1102 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1103
1104 // Give it a bit of time for the resonant antenna to settle.
1105 // And for the tag to fully power up
1106 SpinDelay(150);
1107
1108 // Now start writting
1109 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1110 SpinDelayUs(START_GAP);
1111
1112 // Opcode
1113 T55xxWriteBit(1);
1114 T55xxWriteBit(0); //Page 0
1115 if (PwdMode == 1){
1116 // Pwd
1117 for (i = 0x80000000; i != 0; i >>= 1)
1118 T55xxWriteBit(Pwd & i);
1119 }
1120 // Lock bit
1121 T55xxWriteBit(0);
1122 // Block
1123 for (i = 0x04; i != 0; i >>= 1)
1124 T55xxWriteBit(Block & i);
1125
1126 // Turn field on to read the response
1127 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1128 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1129
1130 // Now do the acquisition
1131 i = 0;
1132 for(;;) {
1133 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1134 AT91C_BASE_SSC->SSC_THR = 0x43;
1135 }
1136 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1137 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1138 // we don't care about actual value, only if it's more or less than a
1139 // threshold essentially we capture zero crossings for later analysis
1140 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1141 i++;
1142 if (i >= m) break;
1143 }
1144 }
1145
1146 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1147 LED_D_OFF();
1148 DbpString("DONE!");
1149 }
1150
1151 // Read card traceability data (page 1)
1152 void T55xxReadTrace(void){
1153 uint8_t *dest = (uint8_t *)BigBuf;
1154 int m=0, i=0;
1155
1156 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1157 m = sizeof(BigBuf);
1158 // Clear destination buffer before sending the command
1159 memset(dest, 128, m);
1160 // Connect the A/D to the peak-detected low-frequency path.
1161 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1162 // Now set up the SSC to get the ADC samples that are now streaming at us.
1163 FpgaSetupSsc();
1164
1165 LED_D_ON();
1166 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1167 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1168
1169 // Give it a bit of time for the resonant antenna to settle.
1170 // And for the tag to fully power up
1171 SpinDelay(150);
1172
1173 // Now start writting
1174 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1175 SpinDelayUs(START_GAP);
1176
1177 // Opcode
1178 T55xxWriteBit(1);
1179 T55xxWriteBit(1); //Page 1
1180
1181 // Turn field on to read the response
1182 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1183 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1184
1185 // Now do the acquisition
1186 i = 0;
1187 for(;;) {
1188 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1189 AT91C_BASE_SSC->SSC_THR = 0x43;
1190 }
1191 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1192 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1193 i++;
1194 if (i >= m) break;
1195 }
1196 }
1197
1198 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1199 LED_D_OFF();
1200 DbpString("DONE!");
1201 }
1202
1203 /*-------------- Cloning routines -----------*/
1204 // Copy HID id to card and setup block 0 config
1205 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1206 {
1207 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1208 int last_block = 0;
1209
1210 if (longFMT){
1211 // Ensure no more than 84 bits supplied
1212 if (hi2>0xFFFFF) {
1213 DbpString("Tags can only have 84 bits.");
1214 return;
1215 }
1216 // Build the 6 data blocks for supplied 84bit ID
1217 last_block = 6;
1218 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1219 for (int i=0;i<4;i++) {
1220 if (hi2 & (1<<(19-i)))
1221 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1222 else
1223 data1 |= (1<<((3-i)*2)); // 0 -> 01
1224 }
1225
1226 data2 = 0;
1227 for (int i=0;i<16;i++) {
1228 if (hi2 & (1<<(15-i)))
1229 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1230 else
1231 data2 |= (1<<((15-i)*2)); // 0 -> 01
1232 }
1233
1234 data3 = 0;
1235 for (int i=0;i<16;i++) {
1236 if (hi & (1<<(31-i)))
1237 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1238 else
1239 data3 |= (1<<((15-i)*2)); // 0 -> 01
1240 }
1241
1242 data4 = 0;
1243 for (int i=0;i<16;i++) {
1244 if (hi & (1<<(15-i)))
1245 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1246 else
1247 data4 |= (1<<((15-i)*2)); // 0 -> 01
1248 }
1249
1250 data5 = 0;
1251 for (int i=0;i<16;i++) {
1252 if (lo & (1<<(31-i)))
1253 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1254 else
1255 data5 |= (1<<((15-i)*2)); // 0 -> 01
1256 }
1257
1258 data6 = 0;
1259 for (int i=0;i<16;i++) {
1260 if (lo & (1<<(15-i)))
1261 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1262 else
1263 data6 |= (1<<((15-i)*2)); // 0 -> 01
1264 }
1265 }
1266 else {
1267 // Ensure no more than 44 bits supplied
1268 if (hi>0xFFF) {
1269 DbpString("Tags can only have 44 bits.");
1270 return;
1271 }
1272
1273 // Build the 3 data blocks for supplied 44bit ID
1274 last_block = 3;
1275
1276 data1 = 0x1D000000; // load preamble
1277
1278 for (int i=0;i<12;i++) {
1279 if (hi & (1<<(11-i)))
1280 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1281 else
1282 data1 |= (1<<((11-i)*2)); // 0 -> 01
1283 }
1284
1285 data2 = 0;
1286 for (int i=0;i<16;i++) {
1287 if (lo & (1<<(31-i)))
1288 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1289 else
1290 data2 |= (1<<((15-i)*2)); // 0 -> 01
1291 }
1292
1293 data3 = 0;
1294 for (int i=0;i<16;i++) {
1295 if (lo & (1<<(15-i)))
1296 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1297 else
1298 data3 |= (1<<((15-i)*2)); // 0 -> 01
1299 }
1300 }
1301
1302 LED_D_ON();
1303 // Program the data blocks for supplied ID
1304 // and the block 0 for HID format
1305 T55xxWriteBlock(data1,1,0,0);
1306 T55xxWriteBlock(data2,2,0,0);
1307 T55xxWriteBlock(data3,3,0,0);
1308
1309 if (longFMT) { // if long format there are 6 blocks
1310 T55xxWriteBlock(data4,4,0,0);
1311 T55xxWriteBlock(data5,5,0,0);
1312 T55xxWriteBlock(data6,6,0,0);
1313 }
1314
1315 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1316 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1317 T55x7_MODULATION_FSK2a |
1318 last_block << T55x7_MAXBLOCK_SHIFT,
1319 0,0,0);
1320
1321 LED_D_OFF();
1322
1323 DbpString("DONE!");
1324 }
1325
1326 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1327 {
1328 int data1=0, data2=0; //up to six blocks for long format
1329
1330 data1 = hi; // load preamble
1331 data2 = lo;
1332
1333 LED_D_ON();
1334 // Program the data blocks for supplied ID
1335 // and the block 0 for HID format
1336 T55xxWriteBlock(data1,1,0,0);
1337 T55xxWriteBlock(data2,2,0,0);
1338
1339 //Config Block
1340 T55xxWriteBlock(0x00147040,0,0,0);
1341 LED_D_OFF();
1342
1343 DbpString("DONE!");
1344 }
1345
1346 // Define 9bit header for EM410x tags
1347 #define EM410X_HEADER 0x1FF
1348 #define EM410X_ID_LENGTH 40
1349
1350 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1351 {
1352 int i, id_bit;
1353 uint64_t id = EM410X_HEADER;
1354 uint64_t rev_id = 0; // reversed ID
1355 int c_parity[4]; // column parity
1356 int r_parity = 0; // row parity
1357 uint32_t clock = 0;
1358
1359 // Reverse ID bits given as parameter (for simpler operations)
1360 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1361 if (i < 32) {
1362 rev_id = (rev_id << 1) | (id_lo & 1);
1363 id_lo >>= 1;
1364 } else {
1365 rev_id = (rev_id << 1) | (id_hi & 1);
1366 id_hi >>= 1;
1367 }
1368 }
1369
1370 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1371 id_bit = rev_id & 1;
1372
1373 if (i % 4 == 0) {
1374 // Don't write row parity bit at start of parsing
1375 if (i)
1376 id = (id << 1) | r_parity;
1377 // Start counting parity for new row
1378 r_parity = id_bit;
1379 } else {
1380 // Count row parity
1381 r_parity ^= id_bit;
1382 }
1383
1384 // First elements in column?
1385 if (i < 4)
1386 // Fill out first elements
1387 c_parity[i] = id_bit;
1388 else
1389 // Count column parity
1390 c_parity[i % 4] ^= id_bit;
1391
1392 // Insert ID bit
1393 id = (id << 1) | id_bit;
1394 rev_id >>= 1;
1395 }
1396
1397 // Insert parity bit of last row
1398 id = (id << 1) | r_parity;
1399
1400 // Fill out column parity at the end of tag
1401 for (i = 0; i < 4; ++i)
1402 id = (id << 1) | c_parity[i];
1403
1404 // Add stop bit
1405 id <<= 1;
1406
1407 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1408 LED_D_ON();
1409
1410 // Write EM410x ID
1411 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1412 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1413
1414 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1415 if (card) {
1416 // Clock rate is stored in bits 8-15 of the card value
1417 clock = (card & 0xFF00) >> 8;
1418 Dbprintf("Clock rate: %d", clock);
1419 switch (clock)
1420 {
1421 case 32:
1422 clock = T55x7_BITRATE_RF_32;
1423 break;
1424 case 16:
1425 clock = T55x7_BITRATE_RF_16;
1426 break;
1427 case 0:
1428 // A value of 0 is assumed to be 64 for backwards-compatibility
1429 // Fall through...
1430 case 64:
1431 clock = T55x7_BITRATE_RF_64;
1432 break;
1433 default:
1434 Dbprintf("Invalid clock rate: %d", clock);
1435 return;
1436 }
1437
1438 // Writing configuration for T55x7 tag
1439 T55xxWriteBlock(clock |
1440 T55x7_MODULATION_MANCHESTER |
1441 2 << T55x7_MAXBLOCK_SHIFT,
1442 0, 0, 0);
1443 }
1444 else
1445 // Writing configuration for T5555(Q5) tag
1446 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1447 T5555_MODULATION_MANCHESTER |
1448 2 << T5555_MAXBLOCK_SHIFT,
1449 0, 0, 0);
1450
1451 LED_D_OFF();
1452 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1453 (uint32_t)(id >> 32), (uint32_t)id);
1454 }
1455
1456 // Clone Indala 64-bit tag by UID to T55x7
1457 void CopyIndala64toT55x7(int hi, int lo)
1458 {
1459
1460 //Program the 2 data blocks for supplied 64bit UID
1461 // and the block 0 for Indala64 format
1462 T55xxWriteBlock(hi,1,0,0);
1463 T55xxWriteBlock(lo,2,0,0);
1464 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1465 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1466 T55x7_MODULATION_PSK1 |
1467 2 << T55x7_MAXBLOCK_SHIFT,
1468 0, 0, 0);
1469 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1470 // T5567WriteBlock(0x603E1042,0);
1471
1472 DbpString("DONE!");
1473
1474 }
1475
1476 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1477 {
1478
1479 //Program the 7 data blocks for supplied 224bit UID
1480 // and the block 0 for Indala224 format
1481 T55xxWriteBlock(uid1,1,0,0);
1482 T55xxWriteBlock(uid2,2,0,0);
1483 T55xxWriteBlock(uid3,3,0,0);
1484 T55xxWriteBlock(uid4,4,0,0);
1485 T55xxWriteBlock(uid5,5,0,0);
1486 T55xxWriteBlock(uid6,6,0,0);
1487 T55xxWriteBlock(uid7,7,0,0);
1488 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1489 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1490 T55x7_MODULATION_PSK1 |
1491 7 << T55x7_MAXBLOCK_SHIFT,
1492 0,0,0);
1493 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1494 // T5567WriteBlock(0x603E10E2,0);
1495
1496 DbpString("DONE!");
1497
1498 }
1499
1500
1501 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1502 #define max(x,y) ( x<y ? y:x)
1503
1504 int DemodPCF7931(uint8_t **outBlocks) {
1505 uint8_t BitStream[256];
1506 uint8_t Blocks[8][16];
1507 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1508 int GraphTraceLen = sizeof(BigBuf);
1509 int i, j, lastval, bitidx, half_switch;
1510 int clock = 64;
1511 int tolerance = clock / 8;
1512 int pmc, block_done;
1513 int lc, warnings = 0;
1514 int num_blocks = 0;
1515 int lmin=128, lmax=128;
1516 uint8_t dir;
1517
1518 AcquireRawAdcSamples125k(0);
1519
1520 lmin = 64;
1521 lmax = 192;
1522
1523 i = 2;
1524
1525 /* Find first local max/min */
1526 if(GraphBuffer[1] > GraphBuffer[0]) {
1527 while(i < GraphTraceLen) {
1528 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1529 break;
1530 i++;
1531 }
1532 dir = 0;
1533 }
1534 else {
1535 while(i < GraphTraceLen) {
1536 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1537 break;
1538 i++;
1539 }
1540 dir = 1;
1541 }
1542
1543 lastval = i++;
1544 half_switch = 0;
1545 pmc = 0;
1546 block_done = 0;
1547
1548 for (bitidx = 0; i < GraphTraceLen; i++)
1549 {
1550 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1551 {
1552 lc = i - lastval;
1553 lastval = i;
1554
1555 // Switch depending on lc length:
1556 // Tolerance is 1/8 of clock rate (arbitrary)
1557 if (abs(lc-clock/4) < tolerance) {
1558 // 16T0
1559 if((i - pmc) == lc) { /* 16T0 was previous one */
1560 /* It's a PMC ! */
1561 i += (128+127+16+32+33+16)-1;
1562 lastval = i;
1563 pmc = 0;
1564 block_done = 1;
1565 }
1566 else {
1567 pmc = i;
1568 }
1569 } else if (abs(lc-clock/2) < tolerance) {
1570 // 32TO
1571 if((i - pmc) == lc) { /* 16T0 was previous one */
1572 /* It's a PMC ! */
1573 i += (128+127+16+32+33)-1;
1574 lastval = i;
1575 pmc = 0;
1576 block_done = 1;
1577 }
1578 else if(half_switch == 1) {
1579 BitStream[bitidx++] = 0;
1580 half_switch = 0;
1581 }
1582 else
1583 half_switch++;
1584 } else if (abs(lc-clock) < tolerance) {
1585 // 64TO
1586 BitStream[bitidx++] = 1;
1587 } else {
1588 // Error
1589 warnings++;
1590 if (warnings > 10)
1591 {
1592 Dbprintf("Error: too many detection errors, aborting.");
1593 return 0;
1594 }
1595 }
1596
1597 if(block_done == 1) {
1598 if(bitidx == 128) {
1599 for(j=0; j<16; j++) {
1600 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1601 64*BitStream[j*8+6]+
1602 32*BitStream[j*8+5]+
1603 16*BitStream[j*8+4]+
1604 8*BitStream[j*8+3]+
1605 4*BitStream[j*8+2]+
1606 2*BitStream[j*8+1]+
1607 BitStream[j*8];
1608 }
1609 num_blocks++;
1610 }
1611 bitidx = 0;
1612 block_done = 0;
1613 half_switch = 0;
1614 }
1615 if(i < GraphTraceLen)
1616 {
1617 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1618 else dir = 1;
1619 }
1620 }
1621 if(bitidx==255)
1622 bitidx=0;
1623 warnings = 0;
1624 if(num_blocks == 4) break;
1625 }
1626 memcpy(outBlocks, Blocks, 16*num_blocks);
1627 return num_blocks;
1628 }
1629
1630 int IsBlock0PCF7931(uint8_t *Block) {
1631 // Assume RFU means 0 :)
1632 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1633 return 1;
1634 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1635 return 1;
1636 return 0;
1637 }
1638
1639 int IsBlock1PCF7931(uint8_t *Block) {
1640 // Assume RFU means 0 :)
1641 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1642 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1643 return 1;
1644
1645 return 0;
1646 }
1647
1648 #define ALLOC 16
1649
1650 void ReadPCF7931() {
1651 uint8_t Blocks[8][17];
1652 uint8_t tmpBlocks[4][16];
1653 int i, j, ind, ind2, n;
1654 int num_blocks = 0;
1655 int max_blocks = 8;
1656 int ident = 0;
1657 int error = 0;
1658 int tries = 0;
1659
1660 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1661
1662 do {
1663 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1664 n = DemodPCF7931((uint8_t**)tmpBlocks);
1665 if(!n)
1666 error++;
1667 if(error==10 && num_blocks == 0) {
1668 Dbprintf("Error, no tag or bad tag");
1669 return;
1670 }
1671 else if (tries==20 || error==10) {
1672 Dbprintf("Error reading the tag");
1673 Dbprintf("Here is the partial content");
1674 goto end;
1675 }
1676
1677 for(i=0; i<n; i++)
1678 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1679 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1680 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1681 if(!ident) {
1682 for(i=0; i<n; i++) {
1683 if(IsBlock0PCF7931(tmpBlocks[i])) {
1684 // Found block 0 ?
1685 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1686 // Found block 1!
1687 // \o/
1688 ident = 1;
1689 memcpy(Blocks[0], tmpBlocks[i], 16);
1690 Blocks[0][ALLOC] = 1;
1691 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1692 Blocks[1][ALLOC] = 1;
1693 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1694 // Debug print
1695 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1696 num_blocks = 2;
1697 // Handle following blocks
1698 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1699 if(j==n) j=0;
1700 if(j==i) break;
1701 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1702 Blocks[ind2][ALLOC] = 1;
1703 }
1704 break;
1705 }
1706 }
1707 }
1708 }
1709 else {
1710 for(i=0; i<n; i++) { // Look for identical block in known blocks
1711 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1712 for(j=0; j<max_blocks; j++) {
1713 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1714 // Found an identical block
1715 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1716 if(ind2 < 0)
1717 ind2 = max_blocks;
1718 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1719 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1720 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1721 Blocks[ind2][ALLOC] = 1;
1722 num_blocks++;
1723 if(num_blocks == max_blocks) goto end;
1724 }
1725 }
1726 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1727 if(ind2 > max_blocks)
1728 ind2 = 0;
1729 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1730 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1731 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1732 Blocks[ind2][ALLOC] = 1;
1733 num_blocks++;
1734 if(num_blocks == max_blocks) goto end;
1735 }
1736 }
1737 }
1738 }
1739 }
1740 }
1741 }
1742 tries++;
1743 if (BUTTON_PRESS()) return;
1744 } while (num_blocks != max_blocks);
1745 end:
1746 Dbprintf("-----------------------------------------");
1747 Dbprintf("Memory content:");
1748 Dbprintf("-----------------------------------------");
1749 for(i=0; i<max_blocks; i++) {
1750 if(Blocks[i][ALLOC]==1)
1751 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1752 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1753 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1754 else
1755 Dbprintf("<missing block %d>", i);
1756 }
1757 Dbprintf("-----------------------------------------");
1758
1759 return ;
1760 }
1761
1762
1763 //-----------------------------------
1764 // EM4469 / EM4305 routines
1765 //-----------------------------------
1766 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1767 #define FWD_CMD_WRITE 0xA
1768 #define FWD_CMD_READ 0x9
1769 #define FWD_CMD_DISABLE 0x5
1770
1771
1772 uint8_t forwardLink_data[64]; //array of forwarded bits
1773 uint8_t * forward_ptr; //ptr for forward message preparation
1774 uint8_t fwd_bit_sz; //forwardlink bit counter
1775 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1776
1777 //====================================================================
1778 // prepares command bits
1779 // see EM4469 spec
1780 //====================================================================
1781 //--------------------------------------------------------------------
1782 uint8_t Prepare_Cmd( uint8_t cmd ) {
1783 //--------------------------------------------------------------------
1784
1785 *forward_ptr++ = 0; //start bit
1786 *forward_ptr++ = 0; //second pause for 4050 code
1787
1788 *forward_ptr++ = cmd;
1789 cmd >>= 1;
1790 *forward_ptr++ = cmd;
1791 cmd >>= 1;
1792 *forward_ptr++ = cmd;
1793 cmd >>= 1;
1794 *forward_ptr++ = cmd;
1795
1796 return 6; //return number of emited bits
1797 }
1798
1799 //====================================================================
1800 // prepares address bits
1801 // see EM4469 spec
1802 //====================================================================
1803
1804 //--------------------------------------------------------------------
1805 uint8_t Prepare_Addr( uint8_t addr ) {
1806 //--------------------------------------------------------------------
1807
1808 register uint8_t line_parity;
1809
1810 uint8_t i;
1811 line_parity = 0;
1812 for(i=0;i<6;i++) {
1813 *forward_ptr++ = addr;
1814 line_parity ^= addr;
1815 addr >>= 1;
1816 }
1817
1818 *forward_ptr++ = (line_parity & 1);
1819
1820 return 7; //return number of emited bits
1821 }
1822
1823 //====================================================================
1824 // prepares data bits intreleaved with parity bits
1825 // see EM4469 spec
1826 //====================================================================
1827
1828 //--------------------------------------------------------------------
1829 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1830 //--------------------------------------------------------------------
1831
1832 register uint8_t line_parity;
1833 register uint8_t column_parity;
1834 register uint8_t i, j;
1835 register uint16_t data;
1836
1837 data = data_low;
1838 column_parity = 0;
1839
1840 for(i=0; i<4; i++) {
1841 line_parity = 0;
1842 for(j=0; j<8; j++) {
1843 line_parity ^= data;
1844 column_parity ^= (data & 1) << j;
1845 *forward_ptr++ = data;
1846 data >>= 1;
1847 }
1848 *forward_ptr++ = line_parity;
1849 if(i == 1)
1850 data = data_hi;
1851 }
1852
1853 for(j=0; j<8; j++) {
1854 *forward_ptr++ = column_parity;
1855 column_parity >>= 1;
1856 }
1857 *forward_ptr = 0;
1858
1859 return 45; //return number of emited bits
1860 }
1861
1862 //====================================================================
1863 // Forward Link send function
1864 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1865 // fwd_bit_count set with number of bits to be sent
1866 //====================================================================
1867 void SendForward(uint8_t fwd_bit_count) {
1868
1869 fwd_write_ptr = forwardLink_data;
1870 fwd_bit_sz = fwd_bit_count;
1871
1872 LED_D_ON();
1873
1874 //Field on
1875 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1876 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1877 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1878
1879 // Give it a bit of time for the resonant antenna to settle.
1880 // And for the tag to fully power up
1881 SpinDelay(150);
1882
1883 // force 1st mod pulse (start gap must be longer for 4305)
1884 fwd_bit_sz--; //prepare next bit modulation
1885 fwd_write_ptr++;
1886 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1887 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1888 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1889 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1890 SpinDelayUs(16*8); //16 cycles on (8us each)
1891
1892 // now start writting
1893 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1894 if(((*fwd_write_ptr++) & 1) == 1)
1895 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1896 else {
1897 //These timings work for 4469/4269/4305 (with the 55*8 above)
1898 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1899 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1900 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1901 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1902 SpinDelayUs(9*8); //16 cycles on (8us each)
1903 }
1904 }
1905 }
1906
1907 void EM4xLogin(uint32_t Password) {
1908
1909 uint8_t fwd_bit_count;
1910
1911 forward_ptr = forwardLink_data;
1912 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1913 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1914
1915 SendForward(fwd_bit_count);
1916
1917 //Wait for command to complete
1918 SpinDelay(20);
1919
1920 }
1921
1922 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1923
1924 uint8_t fwd_bit_count;
1925 uint8_t *dest = (uint8_t *)BigBuf;
1926 int m=0, i=0;
1927
1928 //If password mode do login
1929 if (PwdMode == 1) EM4xLogin(Pwd);
1930
1931 forward_ptr = forwardLink_data;
1932 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1933 fwd_bit_count += Prepare_Addr( Address );
1934
1935 m = sizeof(BigBuf);
1936 // Clear destination buffer before sending the command
1937 memset(dest, 128, m);
1938 // Connect the A/D to the peak-detected low-frequency path.
1939 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1940 // Now set up the SSC to get the ADC samples that are now streaming at us.
1941 FpgaSetupSsc();
1942
1943 SendForward(fwd_bit_count);
1944
1945 // Now do the acquisition
1946 i = 0;
1947 for(;;) {
1948 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1949 AT91C_BASE_SSC->SSC_THR = 0x43;
1950 }
1951 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1952 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1953 i++;
1954 if (i >= m) break;
1955 }
1956 }
1957 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1958 LED_D_OFF();
1959 }
1960
1961 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1962
1963 uint8_t fwd_bit_count;
1964
1965 //If password mode do login
1966 if (PwdMode == 1) EM4xLogin(Pwd);
1967
1968 forward_ptr = forwardLink_data;
1969 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1970 fwd_bit_count += Prepare_Addr( Address );
1971 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1972
1973 SendForward(fwd_bit_count);
1974
1975 //Wait for write to complete
1976 SpinDelay(20);
1977 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1978 LED_D_OFF();
1979 }
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