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[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18
19 /**
20 * Does the sample acquisition. If threshold is specified, the actual sampling
21 * is not commenced until the threshold has been reached.
22 * @param trigger_threshold - the threshold
23 * @param silent - is true, now outputs are made. If false, dbprints the status
24 */
25 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
26 {
27 uint8_t *dest = (uint8_t *)BigBuf;
28 int n = sizeof(BigBuf);
29 int i;
30
31 memset(dest, 0, n);
32 i = 0;
33 for(;;) {
34 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
35 AT91C_BASE_SSC->SSC_THR = 0x43;
36 LED_D_ON();
37 }
38 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
39 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
40 LED_D_OFF();
41 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
42 continue;
43 else
44 trigger_threshold = -1;
45 if (++i >= n) break;
46 }
47 }
48 if(!silent)
49 {
50 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
51 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
52
53 }
54 }
55 /**
56 * Perform sample aquisition.
57 */
58 void DoAcquisition125k(int trigger_threshold)
59 {
60 DoAcquisition125k_internal(trigger_threshold, false);
61 }
62
63 /**
64 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
65 * if not already loaded, sets divisor and starts up the antenna.
66 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
67 * 0 or 95 ==> 125 KHz
68 *
69 **/
70 void LFSetupFPGAForADC(int divisor, bool lf_field)
71 {
72 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
73 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
74 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
75 else if (divisor == 0)
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
77 else
78 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
79
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
81
82 // Connect the A/D to the peak-detected low-frequency path.
83 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
84 // Give it a bit of time for the resonant antenna to settle.
85 SpinDelay(50);
86 // Now set up the SSC to get the ADC samples that are now streaming at us.
87 FpgaSetupSsc();
88 }
89 /**
90 * Initializes the FPGA, and acquires the samples.
91 **/
92 void AcquireRawAdcSamples125k(int divisor)
93 {
94 LFSetupFPGAForADC(divisor, true);
95 // Now call the acquisition routine
96 DoAcquisition125k_internal(-1,false);
97 }
98 /**
99 * Initializes the FPGA for snoop-mode, and acquires the samples.
100 **/
101
102 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
103 {
104 LFSetupFPGAForADC(divisor, false);
105 DoAcquisition125k(trigger_threshold);
106 }
107
108 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
109 {
110
111 /* Make sure the tag is reset */
112 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
114 SpinDelay(2500);
115
116
117 int divisor_used = 95; // 125 KHz
118 // see if 'h' was specified
119
120 if (command[strlen((char *) command) - 1] == 'h')
121 divisor_used = 88; // 134.8 KHz
122
123
124 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
126 // Give it a bit of time for the resonant antenna to settle.
127 SpinDelay(50);
128
129 // And a little more time for the tag to fully power up
130 SpinDelay(2000);
131
132 // Now set up the SSC to get the ADC samples that are now streaming at us.
133 FpgaSetupSsc();
134
135 // now modulate the reader field
136 while(*command != '\0' && *command != ' ') {
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
138 LED_D_OFF();
139 SpinDelayUs(delay_off);
140 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
141
142 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
143 LED_D_ON();
144 if(*(command++) == '0')
145 SpinDelayUs(period_0);
146 else
147 SpinDelayUs(period_1);
148 }
149 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
150 LED_D_OFF();
151 SpinDelayUs(delay_off);
152 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
153
154 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
155
156 // now do the read
157 DoAcquisition125k(-1);
158 }
159
160 /* blank r/w tag data stream
161 ...0000000000000000 01111111
162 1010101010101010101010101010101010101010101010101010101010101010
163 0011010010100001
164 01111111
165 101010101010101[0]000...
166
167 [5555fe852c5555555555555555fe0000]
168 */
169 void ReadTItag(void)
170 {
171 // some hardcoded initial params
172 // when we read a TI tag we sample the zerocross line at 2Mhz
173 // TI tags modulate a 1 as 16 cycles of 123.2Khz
174 // TI tags modulate a 0 as 16 cycles of 134.2Khz
175 #define FSAMPLE 2000000
176 #define FREQLO 123200
177 #define FREQHI 134200
178
179 signed char *dest = (signed char *)BigBuf;
180 int n = sizeof(BigBuf);
181 // int *dest = GraphBuffer;
182 // int n = GraphTraceLen;
183
184 // 128 bit shift register [shift3:shift2:shift1:shift0]
185 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
186
187 int i, cycles=0, samples=0;
188 // how many sample points fit in 16 cycles of each frequency
189 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
190 // when to tell if we're close enough to one freq or another
191 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
192
193 // TI tags charge at 134.2Khz
194 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
195 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
196
197 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
198 // connects to SSP_DIN and the SSP_DOUT logic level controls
199 // whether we're modulating the antenna (high)
200 // or listening to the antenna (low)
201 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
202
203 // get TI tag data into the buffer
204 AcquireTiType();
205
206 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
207
208 for (i=0; i<n-1; i++) {
209 // count cycles by looking for lo to hi zero crossings
210 if ( (dest[i]<0) && (dest[i+1]>0) ) {
211 cycles++;
212 // after 16 cycles, measure the frequency
213 if (cycles>15) {
214 cycles=0;
215 samples=i-samples; // number of samples in these 16 cycles
216
217 // TI bits are coming to us lsb first so shift them
218 // right through our 128 bit right shift register
219 shift0 = (shift0>>1) | (shift1 << 31);
220 shift1 = (shift1>>1) | (shift2 << 31);
221 shift2 = (shift2>>1) | (shift3 << 31);
222 shift3 >>= 1;
223
224 // check if the cycles fall close to the number
225 // expected for either the low or high frequency
226 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
227 // low frequency represents a 1
228 shift3 |= (1<<31);
229 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
230 // high frequency represents a 0
231 } else {
232 // probably detected a gay waveform or noise
233 // use this as gaydar or discard shift register and start again
234 shift3 = shift2 = shift1 = shift0 = 0;
235 }
236 samples = i;
237
238 // for each bit we receive, test if we've detected a valid tag
239
240 // if we see 17 zeroes followed by 6 ones, we might have a tag
241 // remember the bits are backwards
242 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
243 // if start and end bytes match, we have a tag so break out of the loop
244 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
245 cycles = 0xF0B; //use this as a flag (ugly but whatever)
246 break;
247 }
248 }
249 }
250 }
251 }
252
253 // if flag is set we have a tag
254 if (cycles!=0xF0B) {
255 DbpString("Info: No valid tag detected.");
256 } else {
257 // put 64 bit data into shift1 and shift0
258 shift0 = (shift0>>24) | (shift1 << 8);
259 shift1 = (shift1>>24) | (shift2 << 8);
260
261 // align 16 bit crc into lower half of shift2
262 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
263
264 // if r/w tag, check ident match
265 if ( shift3&(1<<15) ) {
266 DbpString("Info: TI tag is rewriteable");
267 // only 15 bits compare, last bit of ident is not valid
268 if ( ((shift3>>16)^shift0)&0x7fff ) {
269 DbpString("Error: Ident mismatch!");
270 } else {
271 DbpString("Info: TI tag ident is valid");
272 }
273 } else {
274 DbpString("Info: TI tag is readonly");
275 }
276
277 // WARNING the order of the bytes in which we calc crc below needs checking
278 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
279 // bytes in reverse or something
280 // calculate CRC
281 uint32_t crc=0;
282
283 crc = update_crc16(crc, (shift0)&0xff);
284 crc = update_crc16(crc, (shift0>>8)&0xff);
285 crc = update_crc16(crc, (shift0>>16)&0xff);
286 crc = update_crc16(crc, (shift0>>24)&0xff);
287 crc = update_crc16(crc, (shift1)&0xff);
288 crc = update_crc16(crc, (shift1>>8)&0xff);
289 crc = update_crc16(crc, (shift1>>16)&0xff);
290 crc = update_crc16(crc, (shift1>>24)&0xff);
291
292 Dbprintf("Info: Tag data: %x%08x, crc=%x",
293 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
294 if (crc != (shift2&0xffff)) {
295 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
296 } else {
297 DbpString("Info: CRC is good");
298 }
299 }
300 }
301
302 void WriteTIbyte(uint8_t b)
303 {
304 int i = 0;
305
306 // modulate 8 bits out to the antenna
307 for (i=0; i<8; i++)
308 {
309 if (b&(1<<i)) {
310 // stop modulating antenna
311 LOW(GPIO_SSC_DOUT);
312 SpinDelayUs(1000);
313 // modulate antenna
314 HIGH(GPIO_SSC_DOUT);
315 SpinDelayUs(1000);
316 } else {
317 // stop modulating antenna
318 LOW(GPIO_SSC_DOUT);
319 SpinDelayUs(300);
320 // modulate antenna
321 HIGH(GPIO_SSC_DOUT);
322 SpinDelayUs(1700);
323 }
324 }
325 }
326
327 void AcquireTiType(void)
328 {
329 int i, j, n;
330 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
331 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
332 #define TIBUFLEN 1250
333
334 // clear buffer
335 memset(BigBuf,0,sizeof(BigBuf));
336
337 // Set up the synchronous serial port
338 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
339 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
346 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
347
348 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
349 // 48/2 = 24 MHz clock must be divided by 12
350 AT91C_BASE_SSC->SSC_CMR = 12;
351
352 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
353 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
354 AT91C_BASE_SSC->SSC_TCMR = 0;
355 AT91C_BASE_SSC->SSC_TFMR = 0;
356
357 LED_D_ON();
358
359 // modulate antenna
360 HIGH(GPIO_SSC_DOUT);
361
362 // Charge TI tag for 50ms.
363 SpinDelay(50);
364
365 // stop modulating antenna and listen
366 LOW(GPIO_SSC_DOUT);
367
368 LED_D_OFF();
369
370 i = 0;
371 for(;;) {
372 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
373 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
374 i++; if(i >= TIBUFLEN) break;
375 }
376 WDT_HIT();
377 }
378
379 // return stolen pin to SSP
380 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
381 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
382
383 char *dest = (char *)BigBuf;
384 n = TIBUFLEN*32;
385 // unpack buffer
386 for (i=TIBUFLEN-1; i>=0; i--) {
387 for (j=0; j<32; j++) {
388 if(BigBuf[i] & (1 << j)) {
389 dest[--n] = 1;
390 } else {
391 dest[--n] = -1;
392 }
393 }
394 }
395 }
396
397 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
398 // if crc provided, it will be written with the data verbatim (even if bogus)
399 // if not provided a valid crc will be computed from the data and written.
400 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
401 {
402 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
403 if(crc == 0) {
404 crc = update_crc16(crc, (idlo)&0xff);
405 crc = update_crc16(crc, (idlo>>8)&0xff);
406 crc = update_crc16(crc, (idlo>>16)&0xff);
407 crc = update_crc16(crc, (idlo>>24)&0xff);
408 crc = update_crc16(crc, (idhi)&0xff);
409 crc = update_crc16(crc, (idhi>>8)&0xff);
410 crc = update_crc16(crc, (idhi>>16)&0xff);
411 crc = update_crc16(crc, (idhi>>24)&0xff);
412 }
413 Dbprintf("Writing to tag: %x%08x, crc=%x",
414 (unsigned int) idhi, (unsigned int) idlo, crc);
415
416 // TI tags charge at 134.2Khz
417 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
418 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
419 // connects to SSP_DIN and the SSP_DOUT logic level controls
420 // whether we're modulating the antenna (high)
421 // or listening to the antenna (low)
422 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
423 LED_A_ON();
424
425 // steal this pin from the SSP and use it to control the modulation
426 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
427 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
428
429 // writing algorithm:
430 // a high bit consists of a field off for 1ms and field on for 1ms
431 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
432 // initiate a charge time of 50ms (field on) then immediately start writing bits
433 // start by writing 0xBB (keyword) and 0xEB (password)
434 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
435 // finally end with 0x0300 (write frame)
436 // all data is sent lsb firts
437 // finish with 15ms programming time
438
439 // modulate antenna
440 HIGH(GPIO_SSC_DOUT);
441 SpinDelay(50); // charge time
442
443 WriteTIbyte(0xbb); // keyword
444 WriteTIbyte(0xeb); // password
445 WriteTIbyte( (idlo )&0xff );
446 WriteTIbyte( (idlo>>8 )&0xff );
447 WriteTIbyte( (idlo>>16)&0xff );
448 WriteTIbyte( (idlo>>24)&0xff );
449 WriteTIbyte( (idhi )&0xff );
450 WriteTIbyte( (idhi>>8 )&0xff );
451 WriteTIbyte( (idhi>>16)&0xff );
452 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
453 WriteTIbyte( (crc )&0xff ); // crc lo
454 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
455 WriteTIbyte(0x00); // write frame lo
456 WriteTIbyte(0x03); // write frame hi
457 HIGH(GPIO_SSC_DOUT);
458 SpinDelay(50); // programming time
459
460 LED_A_OFF();
461
462 // get TI tag data into the buffer
463 AcquireTiType();
464
465 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
466 DbpString("Now use tiread to check");
467 }
468
469 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
470 {
471 int i;
472 uint8_t *tab = (uint8_t *)BigBuf;
473
474 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
475 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
476
477 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
478
479 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
480 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
481
482 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
483 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
484
485 i = 0;
486 for(;;) {
487 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
488 if(BUTTON_PRESS()) {
489 DbpString("Stopped");
490 return;
491 }
492 WDT_HIT();
493 }
494
495 if (ledcontrol)
496 LED_D_ON();
497
498 if(tab[i])
499 OPEN_COIL();
500 else
501 SHORT_COIL();
502
503 if (ledcontrol)
504 LED_D_OFF();
505
506 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
507 if(BUTTON_PRESS()) {
508 DbpString("Stopped");
509 return;
510 }
511 WDT_HIT();
512 }
513
514 i++;
515 if(i == period) {
516 i = 0;
517 if (gap) {
518 SHORT_COIL();
519 SpinDelayUs(gap);
520 }
521 }
522 }
523 }
524
525 #define DEBUG_FRAME_CONTENTS 1
526 void SimulateTagLowFrequencyBidir(int divisor, int t0)
527 {
528 }
529
530 // compose fc/8 fc/10 waveform
531 static void fc(int c, int *n) {
532 uint8_t *dest = (uint8_t *)BigBuf;
533 int idx;
534
535 // for when we want an fc8 pattern every 4 logical bits
536 if(c==0) {
537 dest[((*n)++)]=1;
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 }
546 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
547 if(c==8) {
548 for (idx=0; idx<6; idx++) {
549 dest[((*n)++)]=1;
550 dest[((*n)++)]=1;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 }
558 }
559
560 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
561 if(c==10) {
562 for (idx=0; idx<5; idx++) {
563 dest[((*n)++)]=1;
564 dest[((*n)++)]=1;
565 dest[((*n)++)]=1;
566 dest[((*n)++)]=0;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 dest[((*n)++)]=0;
572 dest[((*n)++)]=0;
573 }
574 }
575 }
576
577 // prepare a waveform pattern in the buffer based on the ID given then
578 // simulate a HID tag until the button is pressed
579 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
580 {
581 int n=0, i=0;
582 /*
583 HID tag bitstream format
584 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
585 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
586 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
587 A fc8 is inserted before every 4 bits
588 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
589 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
590 */
591
592 if (hi>0xFFF) {
593 DbpString("Tags can only have 44 bits.");
594 return;
595 }
596 fc(0,&n);
597 // special start of frame marker containing invalid bit sequences
598 fc(8, &n); fc(8, &n); // invalid
599 fc(8, &n); fc(10, &n); // logical 0
600 fc(10, &n); fc(10, &n); // invalid
601 fc(8, &n); fc(10, &n); // logical 0
602
603 WDT_HIT();
604 // manchester encode bits 43 to 32
605 for (i=11; i>=0; i--) {
606 if ((i%4)==3) fc(0,&n);
607 if ((hi>>i)&1) {
608 fc(10, &n); fc(8, &n); // low-high transition
609 } else {
610 fc(8, &n); fc(10, &n); // high-low transition
611 }
612 }
613
614 WDT_HIT();
615 // manchester encode bits 31 to 0
616 for (i=31; i>=0; i--) {
617 if ((i%4)==3) fc(0,&n);
618 if ((lo>>i)&1) {
619 fc(10, &n); fc(8, &n); // low-high transition
620 } else {
621 fc(8, &n); fc(10, &n); // high-low transition
622 }
623 }
624
625 if (ledcontrol)
626 LED_A_ON();
627 SimulateTagLowFrequency(n, 0, ledcontrol);
628
629 if (ledcontrol)
630 LED_A_OFF();
631 }
632
633 size_t fsk_demod(uint8_t * dest, size_t size)
634 {
635 uint32_t last_transition = 0;
636 uint32_t idx = 1;
637 // we don't care about actual value, only if it's more or less than a
638 // threshold essentially we capture zero crossings for later analysis
639 uint8_t threshold_value = 127;
640
641 // sync to first lo-hi transition, and threshold
642
643 //Need to threshold first sample
644 if(dest[0] < threshold_value) dest[0] = 0;
645 else dest[0] = 1;
646
647 size_t numBits = 0;
648 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
649 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
650 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
651 for(idx = 1; idx < size; idx++) {
652 // threshold current value
653 if (dest[idx] < threshold_value) dest[idx] = 0;
654 else dest[idx] = 1;
655
656 // Check for 0->1 transition
657 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
658
659 if (idx-last_transition < 9) {
660 dest[numBits]=1;
661 } else {
662 dest[numBits]=0;
663 }
664 last_transition = idx;
665 numBits++;
666 }
667 }
668 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
669 }
670
671
672 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits, uint8_t invert )
673 {
674 uint8_t lastval=dest[0];
675 uint32_t idx=0;
676 size_t numBits=0;
677 uint32_t n=1;
678
679 for( idx=1; idx < size; idx++) {
680
681 if (dest[idx]==lastval) {
682 n++;
683 continue;
684 }
685 //if lastval was 1, we have a 1->0 crossing
686 if ( dest[idx-1]==1 ) {
687 n=(n+1) / h2l_crossing_value;
688 } else {// 0->1 crossing
689 n=(n+1) / l2h_crossing_value;
690 }
691 if (n == 0) n = 1;
692
693 if(n < maxConsequtiveBits) //Consecutive
694 {
695 if(invert==0){ //invert bits
696 memset(dest+numBits, dest[idx-1] , n);
697 }else{
698 memset(dest+numBits, dest[idx-1]^1 , n);
699 }
700
701 numBits += n;
702 }
703 n=0;
704 lastval=dest[idx];
705 }//end for
706 return numBits;
707 }
708 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
709 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
710 {
711 uint8_t *dest = (uint8_t *)BigBuf;
712
713 size_t size=0,idx=0; //, found=0;
714 uint32_t hi2=0, hi=0, lo=0;
715
716 // Configure to go in 125Khz listen mode
717 LFSetupFPGAForADC(95, true);
718
719 while(!BUTTON_PRESS()) {
720
721 WDT_HIT();
722 if (ledcontrol) LED_A_ON();
723
724 DoAcquisition125k_internal(-1,true);
725 size = sizeof(BigBuf);
726
727 // FSK demodulator
728 size = fsk_demod(dest, size);
729
730 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
731 // 1->0 : fc/8 in sets of 6 (RF/50 / 8 = 6.25)
732 // 0->1 : fc/10 in sets of 5 (RF/50 / 10= 5)
733 // do not invert
734 size = aggregate_bits(dest,size, 6,5,5,0);
735
736 WDT_HIT();
737
738 // final loop, go over previously decoded manchester data and decode into usable tag ID
739 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
740 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
741 int numshifts = 0;
742 idx = 0;
743 while( idx + sizeof(frame_marker_mask) < size) {
744 // search for a start of frame marker
745 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
746 { // frame marker found
747 idx+=sizeof(frame_marker_mask);
748 while(dest[idx] != dest[idx+1] && idx < size-2)
749 {
750 // Keep going until next frame marker (or error)
751 // Shift in a bit. Start by shifting high registers
752 hi2 = (hi2<<1)|(hi>>31);
753 hi = (hi<<1)|(lo>>31);
754 //Then, shift in a 0 or one into low
755 if (dest[idx] && !dest[idx+1]) // 1 0
756 lo=(lo<<1)|0;
757 else // 0 1
758 lo=(lo<<1)|
759 1;
760 numshifts++;
761 idx += 2;
762 }
763 //Dbprintf("Num shifts: %d ", numshifts);
764 // Hopefully, we read a tag and hit upon the next frame marker
765 if(idx + sizeof(frame_marker_mask) < size)
766 {
767 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
768 {
769 if (hi2 != 0){ //extra large HID tags
770 Dbprintf("TAG ID: %x%08x%08x (%d)",
771 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
772 }
773 else { //standard HID tags <38 bits
774 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
775 uint8_t bitlen = 0;
776 uint32_t fc = 0;
777 uint32_t cardnum = 0;
778 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
779 uint32_t lo2=0;
780 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
781 uint8_t idx3 = 1;
782 while(lo2>1){ //find last bit set to 1 (format len bit)
783 lo2=lo2>>1;
784 idx3++;
785 }
786 bitlen =idx3+19;
787 fc =0;
788 cardnum=0;
789 if(bitlen==26){
790 cardnum = (lo>>1)&0xFFFF;
791 fc = (lo>>17)&0xFF;
792 }
793 if(bitlen==37){
794 cardnum = (lo>>1)&0x7FFFF;
795 fc = ((hi&0xF)<<12)|(lo>>20);
796 }
797 if(bitlen==34){
798 cardnum = (lo>>1)&0xFFFF;
799 fc= ((hi&1)<<15)|(lo>>17);
800 }
801 if(bitlen==35){
802 cardnum = (lo>>1)&0xFFFFF;
803 fc = ((hi&1)<<11)|(lo>>21);
804 }
805 }
806 else { //if bit 38 is not set then 37 bit format is used
807 bitlen= 37;
808 fc =0;
809 cardnum=0;
810 if(bitlen==37){
811 cardnum = (lo>>1)&0x7FFFF;
812 fc = ((hi&0xF)<<12)|(lo>>20);
813 }
814 }
815 //Dbprintf("TAG ID: %x%08x (%d)",
816 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
817 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
818 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
819 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
820 }
821 if (findone){
822 if (ledcontrol) LED_A_OFF();
823 return;
824 }
825 }
826 }
827 // reset
828 hi2 = hi = lo = 0;
829 numshifts = 0;
830 }else
831 {
832 idx++;
833 }
834 }
835 WDT_HIT();
836
837 }
838 DbpString("Stopped");
839 if (ledcontrol) LED_A_OFF();
840 }
841
842 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
843 {
844 uint32_t num = 0;
845 for(int i = 0 ; i < numbits ; i++)
846 {
847 num = (num << 1) | (*src);
848 src++;
849 }
850 return num;
851 }
852
853 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
854 {
855 uint8_t *dest = (uint8_t *)BigBuf;
856 size_t size=0, idx=0;
857 uint32_t code=0, code2=0;
858
859 // Configure to go in 125Khz listen mode
860 LFSetupFPGAForADC(95, true);
861
862 while(!BUTTON_PRESS()) {
863 WDT_HIT();
864 if (ledcontrol) LED_A_ON();
865 DoAcquisition125k_internal(-1,true);
866 size = sizeof(BigBuf);
867
868 // FSK demodulator
869 size = fsk_demod(dest, size);
870 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
871 // 1->0 : fc/8 in sets of 7 (RF/64 / 8 = 8)
872 // 0->1 : fc/10 in sets of 6 (RF/64 / 10 = 6.4)
873 size = aggregate_bits(dest, size, 7,6,13,1); //13 max Consecutive should be ok as most 0s in row should be 10 for init seq - invert bits
874 WDT_HIT();
875 //Index map
876 //0 10 20 30 40 50 60
877 //| | | | | | |
878 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
879 //-----------------------------------------------------------------------------
880 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
881 //
882 //XSF(version)facility:codeone+codetwo
883 //Handle the data
884 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
885 for( idx=0; idx < (size - 64); idx++) {
886 if ( memcmp(dest + idx, mask, sizeof(mask))==0) {
887 //frame marker found
888 if(findone){ //only print binary if we are doing one
889 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
890 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
891 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
892 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
893 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
894 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
895 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
896 }
897 code = bytebits_to_byte(dest+idx,32);
898 code2 = bytebits_to_byte(dest+idx+32,32);
899 short version = bytebits_to_byte(dest+idx+28,8); //14,4
900 char facilitycode = bytebits_to_byte(dest+idx+19,8) ;
901 uint16_t number = (bytebits_to_byte(dest+idx+37,8)<<8)|(bytebits_to_byte(dest+idx+46,8)); //36,9
902
903 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,facilitycode,number,code,code2);
904 // if we're only looking for one tag
905 if (findone){
906 if (ledcontrol) LED_A_OFF();
907 //LED_A_OFF();
908 return;
909 }
910 }
911 }
912 WDT_HIT();
913 }
914 DbpString("Stopped");
915 if (ledcontrol) LED_A_OFF();
916 }
917
918 /*------------------------------
919 * T5555/T5557/T5567 routines
920 *------------------------------
921 */
922
923 /* T55x7 configuration register definitions */
924 #define T55x7_POR_DELAY 0x00000001
925 #define T55x7_ST_TERMINATOR 0x00000008
926 #define T55x7_PWD 0x00000010
927 #define T55x7_MAXBLOCK_SHIFT 5
928 #define T55x7_AOR 0x00000200
929 #define T55x7_PSKCF_RF_2 0
930 #define T55x7_PSKCF_RF_4 0x00000400
931 #define T55x7_PSKCF_RF_8 0x00000800
932 #define T55x7_MODULATION_DIRECT 0
933 #define T55x7_MODULATION_PSK1 0x00001000
934 #define T55x7_MODULATION_PSK2 0x00002000
935 #define T55x7_MODULATION_PSK3 0x00003000
936 #define T55x7_MODULATION_FSK1 0x00004000
937 #define T55x7_MODULATION_FSK2 0x00005000
938 #define T55x7_MODULATION_FSK1a 0x00006000
939 #define T55x7_MODULATION_FSK2a 0x00007000
940 #define T55x7_MODULATION_MANCHESTER 0x00008000
941 #define T55x7_MODULATION_BIPHASE 0x00010000
942 #define T55x7_BITRATE_RF_8 0
943 #define T55x7_BITRATE_RF_16 0x00040000
944 #define T55x7_BITRATE_RF_32 0x00080000
945 #define T55x7_BITRATE_RF_40 0x000C0000
946 #define T55x7_BITRATE_RF_50 0x00100000
947 #define T55x7_BITRATE_RF_64 0x00140000
948 #define T55x7_BITRATE_RF_100 0x00180000
949 #define T55x7_BITRATE_RF_128 0x001C0000
950
951 /* T5555 (Q5) configuration register definitions */
952 #define T5555_ST_TERMINATOR 0x00000001
953 #define T5555_MAXBLOCK_SHIFT 0x00000001
954 #define T5555_MODULATION_MANCHESTER 0
955 #define T5555_MODULATION_PSK1 0x00000010
956 #define T5555_MODULATION_PSK2 0x00000020
957 #define T5555_MODULATION_PSK3 0x00000030
958 #define T5555_MODULATION_FSK1 0x00000040
959 #define T5555_MODULATION_FSK2 0x00000050
960 #define T5555_MODULATION_BIPHASE 0x00000060
961 #define T5555_MODULATION_DIRECT 0x00000070
962 #define T5555_INVERT_OUTPUT 0x00000080
963 #define T5555_PSK_RF_2 0
964 #define T5555_PSK_RF_4 0x00000100
965 #define T5555_PSK_RF_8 0x00000200
966 #define T5555_USE_PWD 0x00000400
967 #define T5555_USE_AOR 0x00000800
968 #define T5555_BITRATE_SHIFT 12
969 #define T5555_FAST_WRITE 0x00004000
970 #define T5555_PAGE_SELECT 0x00008000
971
972 /*
973 * Relevant times in microsecond
974 * To compensate antenna falling times shorten the write times
975 * and enlarge the gap ones.
976 */
977 #define START_GAP 250
978 #define WRITE_GAP 160
979 #define WRITE_0 144 // 192
980 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
981
982 // Write one bit to card
983 void T55xxWriteBit(int bit)
984 {
985 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
986 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
987 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
988 if (bit == 0)
989 SpinDelayUs(WRITE_0);
990 else
991 SpinDelayUs(WRITE_1);
992 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
993 SpinDelayUs(WRITE_GAP);
994 }
995
996 // Write one card block in page 0, no lock
997 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
998 {
999 //unsigned int i; //enio adjustment 12/10/14
1000 uint32_t i;
1001
1002 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1003 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1004 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1005
1006 // Give it a bit of time for the resonant antenna to settle.
1007 // And for the tag to fully power up
1008 SpinDelay(150);
1009
1010 // Now start writting
1011 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1012 SpinDelayUs(START_GAP);
1013
1014 // Opcode
1015 T55xxWriteBit(1);
1016 T55xxWriteBit(0); //Page 0
1017 if (PwdMode == 1){
1018 // Pwd
1019 for (i = 0x80000000; i != 0; i >>= 1)
1020 T55xxWriteBit(Pwd & i);
1021 }
1022 // Lock bit
1023 T55xxWriteBit(0);
1024
1025 // Data
1026 for (i = 0x80000000; i != 0; i >>= 1)
1027 T55xxWriteBit(Data & i);
1028
1029 // Block
1030 for (i = 0x04; i != 0; i >>= 1)
1031 T55xxWriteBit(Block & i);
1032
1033 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1034 // so wait a little more)
1035 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1036 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1037 SpinDelay(20);
1038 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1039 }
1040
1041 // Read one card block in page 0
1042 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1043 {
1044 uint8_t *dest = (uint8_t *)BigBuf;
1045 //int m=0, i=0; //enio adjustment 12/10/14
1046 uint32_t m=0, i=0;
1047 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1048 m = sizeof(BigBuf);
1049 // Clear destination buffer before sending the command
1050 memset(dest, 128, m);
1051 // Connect the A/D to the peak-detected low-frequency path.
1052 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1053 // Now set up the SSC to get the ADC samples that are now streaming at us.
1054 FpgaSetupSsc();
1055
1056 LED_D_ON();
1057 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1058 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1059
1060 // Give it a bit of time for the resonant antenna to settle.
1061 // And for the tag to fully power up
1062 SpinDelay(150);
1063
1064 // Now start writting
1065 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1066 SpinDelayUs(START_GAP);
1067
1068 // Opcode
1069 T55xxWriteBit(1);
1070 T55xxWriteBit(0); //Page 0
1071 if (PwdMode == 1){
1072 // Pwd
1073 for (i = 0x80000000; i != 0; i >>= 1)
1074 T55xxWriteBit(Pwd & i);
1075 }
1076 // Lock bit
1077 T55xxWriteBit(0);
1078 // Block
1079 for (i = 0x04; i != 0; i >>= 1)
1080 T55xxWriteBit(Block & i);
1081
1082 // Turn field on to read the response
1083 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1084 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1085
1086 // Now do the acquisition
1087 i = 0;
1088 for(;;) {
1089 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1090 AT91C_BASE_SSC->SSC_THR = 0x43;
1091 }
1092 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1093 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1094 // we don't care about actual value, only if it's more or less than a
1095 // threshold essentially we capture zero crossings for later analysis
1096 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1097 i++;
1098 if (i >= m) break;
1099 }
1100 }
1101
1102 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1103 LED_D_OFF();
1104 DbpString("DONE!");
1105 }
1106
1107 // Read card traceability data (page 1)
1108 void T55xxReadTrace(void){
1109 uint8_t *dest = (uint8_t *)BigBuf;
1110 int m=0, i=0;
1111
1112 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1113 m = sizeof(BigBuf);
1114 // Clear destination buffer before sending the command
1115 memset(dest, 128, m);
1116 // Connect the A/D to the peak-detected low-frequency path.
1117 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1118 // Now set up the SSC to get the ADC samples that are now streaming at us.
1119 FpgaSetupSsc();
1120
1121 LED_D_ON();
1122 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1123 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1124
1125 // Give it a bit of time for the resonant antenna to settle.
1126 // And for the tag to fully power up
1127 SpinDelay(150);
1128
1129 // Now start writting
1130 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1131 SpinDelayUs(START_GAP);
1132
1133 // Opcode
1134 T55xxWriteBit(1);
1135 T55xxWriteBit(1); //Page 1
1136
1137 // Turn field on to read the response
1138 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1139 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1140
1141 // Now do the acquisition
1142 i = 0;
1143 for(;;) {
1144 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1145 AT91C_BASE_SSC->SSC_THR = 0x43;
1146 }
1147 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1148 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1149 i++;
1150 if (i >= m) break;
1151 }
1152 }
1153
1154 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1155 LED_D_OFF();
1156 DbpString("DONE!");
1157 }
1158
1159 /*-------------- Cloning routines -----------*/
1160 // Copy HID id to card and setup block 0 config
1161 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1162 {
1163 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1164 int last_block = 0;
1165
1166 if (longFMT){
1167 // Ensure no more than 84 bits supplied
1168 if (hi2>0xFFFFF) {
1169 DbpString("Tags can only have 84 bits.");
1170 return;
1171 }
1172 // Build the 6 data blocks for supplied 84bit ID
1173 last_block = 6;
1174 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1175 for (int i=0;i<4;i++) {
1176 if (hi2 & (1<<(19-i)))
1177 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1178 else
1179 data1 |= (1<<((3-i)*2)); // 0 -> 01
1180 }
1181
1182 data2 = 0;
1183 for (int i=0;i<16;i++) {
1184 if (hi2 & (1<<(15-i)))
1185 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1186 else
1187 data2 |= (1<<((15-i)*2)); // 0 -> 01
1188 }
1189
1190 data3 = 0;
1191 for (int i=0;i<16;i++) {
1192 if (hi & (1<<(31-i)))
1193 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1194 else
1195 data3 |= (1<<((15-i)*2)); // 0 -> 01
1196 }
1197
1198 data4 = 0;
1199 for (int i=0;i<16;i++) {
1200 if (hi & (1<<(15-i)))
1201 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1202 else
1203 data4 |= (1<<((15-i)*2)); // 0 -> 01
1204 }
1205
1206 data5 = 0;
1207 for (int i=0;i<16;i++) {
1208 if (lo & (1<<(31-i)))
1209 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1210 else
1211 data5 |= (1<<((15-i)*2)); // 0 -> 01
1212 }
1213
1214 data6 = 0;
1215 for (int i=0;i<16;i++) {
1216 if (lo & (1<<(15-i)))
1217 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1218 else
1219 data6 |= (1<<((15-i)*2)); // 0 -> 01
1220 }
1221 }
1222 else {
1223 // Ensure no more than 44 bits supplied
1224 if (hi>0xFFF) {
1225 DbpString("Tags can only have 44 bits.");
1226 return;
1227 }
1228
1229 // Build the 3 data blocks for supplied 44bit ID
1230 last_block = 3;
1231
1232 data1 = 0x1D000000; // load preamble
1233
1234 for (int i=0;i<12;i++) {
1235 if (hi & (1<<(11-i)))
1236 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1237 else
1238 data1 |= (1<<((11-i)*2)); // 0 -> 01
1239 }
1240
1241 data2 = 0;
1242 for (int i=0;i<16;i++) {
1243 if (lo & (1<<(31-i)))
1244 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1245 else
1246 data2 |= (1<<((15-i)*2)); // 0 -> 01
1247 }
1248
1249 data3 = 0;
1250 for (int i=0;i<16;i++) {
1251 if (lo & (1<<(15-i)))
1252 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1253 else
1254 data3 |= (1<<((15-i)*2)); // 0 -> 01
1255 }
1256 }
1257
1258 LED_D_ON();
1259 // Program the data blocks for supplied ID
1260 // and the block 0 for HID format
1261 T55xxWriteBlock(data1,1,0,0);
1262 T55xxWriteBlock(data2,2,0,0);
1263 T55xxWriteBlock(data3,3,0,0);
1264
1265 if (longFMT) { // if long format there are 6 blocks
1266 T55xxWriteBlock(data4,4,0,0);
1267 T55xxWriteBlock(data5,5,0,0);
1268 T55xxWriteBlock(data6,6,0,0);
1269 }
1270
1271 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1272 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1273 T55x7_MODULATION_FSK2a |
1274 last_block << T55x7_MAXBLOCK_SHIFT,
1275 0,0,0);
1276
1277 LED_D_OFF();
1278
1279 DbpString("DONE!");
1280 }
1281
1282 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1283 {
1284 int data1=0, data2=0; //up to six blocks for long format
1285
1286 data1 = hi; // load preamble
1287 data2 = lo;
1288
1289 LED_D_ON();
1290 // Program the data blocks for supplied ID
1291 // and the block 0 for HID format
1292 T55xxWriteBlock(data1,1,0,0);
1293 T55xxWriteBlock(data2,2,0,0);
1294
1295 //Config Block
1296 T55xxWriteBlock(0x00147040,0,0,0);
1297 LED_D_OFF();
1298
1299 DbpString("DONE!");
1300 }
1301
1302 // Define 9bit header for EM410x tags
1303 #define EM410X_HEADER 0x1FF
1304 #define EM410X_ID_LENGTH 40
1305
1306 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1307 {
1308 int i, id_bit;
1309 uint64_t id = EM410X_HEADER;
1310 uint64_t rev_id = 0; // reversed ID
1311 int c_parity[4]; // column parity
1312 int r_parity = 0; // row parity
1313 uint32_t clock = 0;
1314
1315 // Reverse ID bits given as parameter (for simpler operations)
1316 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1317 if (i < 32) {
1318 rev_id = (rev_id << 1) | (id_lo & 1);
1319 id_lo >>= 1;
1320 } else {
1321 rev_id = (rev_id << 1) | (id_hi & 1);
1322 id_hi >>= 1;
1323 }
1324 }
1325
1326 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1327 id_bit = rev_id & 1;
1328
1329 if (i % 4 == 0) {
1330 // Don't write row parity bit at start of parsing
1331 if (i)
1332 id = (id << 1) | r_parity;
1333 // Start counting parity for new row
1334 r_parity = id_bit;
1335 } else {
1336 // Count row parity
1337 r_parity ^= id_bit;
1338 }
1339
1340 // First elements in column?
1341 if (i < 4)
1342 // Fill out first elements
1343 c_parity[i] = id_bit;
1344 else
1345 // Count column parity
1346 c_parity[i % 4] ^= id_bit;
1347
1348 // Insert ID bit
1349 id = (id << 1) | id_bit;
1350 rev_id >>= 1;
1351 }
1352
1353 // Insert parity bit of last row
1354 id = (id << 1) | r_parity;
1355
1356 // Fill out column parity at the end of tag
1357 for (i = 0; i < 4; ++i)
1358 id = (id << 1) | c_parity[i];
1359
1360 // Add stop bit
1361 id <<= 1;
1362
1363 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1364 LED_D_ON();
1365
1366 // Write EM410x ID
1367 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1368 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1369
1370 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1371 if (card) {
1372 // Clock rate is stored in bits 8-15 of the card value
1373 clock = (card & 0xFF00) >> 8;
1374 Dbprintf("Clock rate: %d", clock);
1375 switch (clock)
1376 {
1377 case 32:
1378 clock = T55x7_BITRATE_RF_32;
1379 break;
1380 case 16:
1381 clock = T55x7_BITRATE_RF_16;
1382 break;
1383 case 0:
1384 // A value of 0 is assumed to be 64 for backwards-compatibility
1385 // Fall through...
1386 case 64:
1387 clock = T55x7_BITRATE_RF_64;
1388 break;
1389 default:
1390 Dbprintf("Invalid clock rate: %d", clock);
1391 return;
1392 }
1393
1394 // Writing configuration for T55x7 tag
1395 T55xxWriteBlock(clock |
1396 T55x7_MODULATION_MANCHESTER |
1397 2 << T55x7_MAXBLOCK_SHIFT,
1398 0, 0, 0);
1399 }
1400 else
1401 // Writing configuration for T5555(Q5) tag
1402 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1403 T5555_MODULATION_MANCHESTER |
1404 2 << T5555_MAXBLOCK_SHIFT,
1405 0, 0, 0);
1406
1407 LED_D_OFF();
1408 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1409 (uint32_t)(id >> 32), (uint32_t)id);
1410 }
1411
1412 // Clone Indala 64-bit tag by UID to T55x7
1413 void CopyIndala64toT55x7(int hi, int lo)
1414 {
1415
1416 //Program the 2 data blocks for supplied 64bit UID
1417 // and the block 0 for Indala64 format
1418 T55xxWriteBlock(hi,1,0,0);
1419 T55xxWriteBlock(lo,2,0,0);
1420 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1421 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1422 T55x7_MODULATION_PSK1 |
1423 2 << T55x7_MAXBLOCK_SHIFT,
1424 0, 0, 0);
1425 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1426 // T5567WriteBlock(0x603E1042,0);
1427
1428 DbpString("DONE!");
1429
1430 }
1431
1432 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1433 {
1434
1435 //Program the 7 data blocks for supplied 224bit UID
1436 // and the block 0 for Indala224 format
1437 T55xxWriteBlock(uid1,1,0,0);
1438 T55xxWriteBlock(uid2,2,0,0);
1439 T55xxWriteBlock(uid3,3,0,0);
1440 T55xxWriteBlock(uid4,4,0,0);
1441 T55xxWriteBlock(uid5,5,0,0);
1442 T55xxWriteBlock(uid6,6,0,0);
1443 T55xxWriteBlock(uid7,7,0,0);
1444 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1445 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1446 T55x7_MODULATION_PSK1 |
1447 7 << T55x7_MAXBLOCK_SHIFT,
1448 0,0,0);
1449 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1450 // T5567WriteBlock(0x603E10E2,0);
1451
1452 DbpString("DONE!");
1453
1454 }
1455
1456
1457 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1458 #define max(x,y) ( x<y ? y:x)
1459
1460 int DemodPCF7931(uint8_t **outBlocks) {
1461 uint8_t BitStream[256];
1462 uint8_t Blocks[8][16];
1463 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1464 int GraphTraceLen = sizeof(BigBuf);
1465 int i, j, lastval, bitidx, half_switch;
1466 int clock = 64;
1467 int tolerance = clock / 8;
1468 int pmc, block_done;
1469 int lc, warnings = 0;
1470 int num_blocks = 0;
1471 int lmin=128, lmax=128;
1472 uint8_t dir;
1473
1474 AcquireRawAdcSamples125k(0);
1475
1476 lmin = 64;
1477 lmax = 192;
1478
1479 i = 2;
1480
1481 /* Find first local max/min */
1482 if(GraphBuffer[1] > GraphBuffer[0]) {
1483 while(i < GraphTraceLen) {
1484 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1485 break;
1486 i++;
1487 }
1488 dir = 0;
1489 }
1490 else {
1491 while(i < GraphTraceLen) {
1492 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1493 break;
1494 i++;
1495 }
1496 dir = 1;
1497 }
1498
1499 lastval = i++;
1500 half_switch = 0;
1501 pmc = 0;
1502 block_done = 0;
1503
1504 for (bitidx = 0; i < GraphTraceLen; i++)
1505 {
1506 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1507 {
1508 lc = i - lastval;
1509 lastval = i;
1510
1511 // Switch depending on lc length:
1512 // Tolerance is 1/8 of clock rate (arbitrary)
1513 if (abs(lc-clock/4) < tolerance) {
1514 // 16T0
1515 if((i - pmc) == lc) { /* 16T0 was previous one */
1516 /* It's a PMC ! */
1517 i += (128+127+16+32+33+16)-1;
1518 lastval = i;
1519 pmc = 0;
1520 block_done = 1;
1521 }
1522 else {
1523 pmc = i;
1524 }
1525 } else if (abs(lc-clock/2) < tolerance) {
1526 // 32TO
1527 if((i - pmc) == lc) { /* 16T0 was previous one */
1528 /* It's a PMC ! */
1529 i += (128+127+16+32+33)-1;
1530 lastval = i;
1531 pmc = 0;
1532 block_done = 1;
1533 }
1534 else if(half_switch == 1) {
1535 BitStream[bitidx++] = 0;
1536 half_switch = 0;
1537 }
1538 else
1539 half_switch++;
1540 } else if (abs(lc-clock) < tolerance) {
1541 // 64TO
1542 BitStream[bitidx++] = 1;
1543 } else {
1544 // Error
1545 warnings++;
1546 if (warnings > 10)
1547 {
1548 Dbprintf("Error: too many detection errors, aborting.");
1549 return 0;
1550 }
1551 }
1552
1553 if(block_done == 1) {
1554 if(bitidx == 128) {
1555 for(j=0; j<16; j++) {
1556 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1557 64*BitStream[j*8+6]+
1558 32*BitStream[j*8+5]+
1559 16*BitStream[j*8+4]+
1560 8*BitStream[j*8+3]+
1561 4*BitStream[j*8+2]+
1562 2*BitStream[j*8+1]+
1563 BitStream[j*8];
1564 }
1565 num_blocks++;
1566 }
1567 bitidx = 0;
1568 block_done = 0;
1569 half_switch = 0;
1570 }
1571 if(i < GraphTraceLen)
1572 {
1573 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1574 else dir = 1;
1575 }
1576 }
1577 if(bitidx==255)
1578 bitidx=0;
1579 warnings = 0;
1580 if(num_blocks == 4) break;
1581 }
1582 memcpy(outBlocks, Blocks, 16*num_blocks);
1583 return num_blocks;
1584 }
1585
1586 int IsBlock0PCF7931(uint8_t *Block) {
1587 // Assume RFU means 0 :)
1588 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1589 return 1;
1590 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1591 return 1;
1592 return 0;
1593 }
1594
1595 int IsBlock1PCF7931(uint8_t *Block) {
1596 // Assume RFU means 0 :)
1597 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1598 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1599 return 1;
1600
1601 return 0;
1602 }
1603
1604 #define ALLOC 16
1605
1606 void ReadPCF7931() {
1607 uint8_t Blocks[8][17];
1608 uint8_t tmpBlocks[4][16];
1609 int i, j, ind, ind2, n;
1610 int num_blocks = 0;
1611 int max_blocks = 8;
1612 int ident = 0;
1613 int error = 0;
1614 int tries = 0;
1615
1616 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1617
1618 do {
1619 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1620 n = DemodPCF7931((uint8_t**)tmpBlocks);
1621 if(!n)
1622 error++;
1623 if(error==10 && num_blocks == 0) {
1624 Dbprintf("Error, no tag or bad tag");
1625 return;
1626 }
1627 else if (tries==20 || error==10) {
1628 Dbprintf("Error reading the tag");
1629 Dbprintf("Here is the partial content");
1630 goto end;
1631 }
1632
1633 for(i=0; i<n; i++)
1634 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1635 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1636 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1637 if(!ident) {
1638 for(i=0; i<n; i++) {
1639 if(IsBlock0PCF7931(tmpBlocks[i])) {
1640 // Found block 0 ?
1641 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1642 // Found block 1!
1643 // \o/
1644 ident = 1;
1645 memcpy(Blocks[0], tmpBlocks[i], 16);
1646 Blocks[0][ALLOC] = 1;
1647 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1648 Blocks[1][ALLOC] = 1;
1649 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1650 // Debug print
1651 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1652 num_blocks = 2;
1653 // Handle following blocks
1654 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1655 if(j==n) j=0;
1656 if(j==i) break;
1657 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1658 Blocks[ind2][ALLOC] = 1;
1659 }
1660 break;
1661 }
1662 }
1663 }
1664 }
1665 else {
1666 for(i=0; i<n; i++) { // Look for identical block in known blocks
1667 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1668 for(j=0; j<max_blocks; j++) {
1669 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1670 // Found an identical block
1671 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1672 if(ind2 < 0)
1673 ind2 = max_blocks;
1674 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1675 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1676 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1677 Blocks[ind2][ALLOC] = 1;
1678 num_blocks++;
1679 if(num_blocks == max_blocks) goto end;
1680 }
1681 }
1682 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1683 if(ind2 > max_blocks)
1684 ind2 = 0;
1685 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1686 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1687 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1688 Blocks[ind2][ALLOC] = 1;
1689 num_blocks++;
1690 if(num_blocks == max_blocks) goto end;
1691 }
1692 }
1693 }
1694 }
1695 }
1696 }
1697 }
1698 tries++;
1699 if (BUTTON_PRESS()) return;
1700 } while (num_blocks != max_blocks);
1701 end:
1702 Dbprintf("-----------------------------------------");
1703 Dbprintf("Memory content:");
1704 Dbprintf("-----------------------------------------");
1705 for(i=0; i<max_blocks; i++) {
1706 if(Blocks[i][ALLOC]==1)
1707 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1708 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1709 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1710 else
1711 Dbprintf("<missing block %d>", i);
1712 }
1713 Dbprintf("-----------------------------------------");
1714
1715 return ;
1716 }
1717
1718
1719 //-----------------------------------
1720 // EM4469 / EM4305 routines
1721 //-----------------------------------
1722 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1723 #define FWD_CMD_WRITE 0xA
1724 #define FWD_CMD_READ 0x9
1725 #define FWD_CMD_DISABLE 0x5
1726
1727
1728 uint8_t forwardLink_data[64]; //array of forwarded bits
1729 uint8_t * forward_ptr; //ptr for forward message preparation
1730 uint8_t fwd_bit_sz; //forwardlink bit counter
1731 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1732
1733 //====================================================================
1734 // prepares command bits
1735 // see EM4469 spec
1736 //====================================================================
1737 //--------------------------------------------------------------------
1738 uint8_t Prepare_Cmd( uint8_t cmd ) {
1739 //--------------------------------------------------------------------
1740
1741 *forward_ptr++ = 0; //start bit
1742 *forward_ptr++ = 0; //second pause for 4050 code
1743
1744 *forward_ptr++ = cmd;
1745 cmd >>= 1;
1746 *forward_ptr++ = cmd;
1747 cmd >>= 1;
1748 *forward_ptr++ = cmd;
1749 cmd >>= 1;
1750 *forward_ptr++ = cmd;
1751
1752 return 6; //return number of emited bits
1753 }
1754
1755 //====================================================================
1756 // prepares address bits
1757 // see EM4469 spec
1758 //====================================================================
1759
1760 //--------------------------------------------------------------------
1761 uint8_t Prepare_Addr( uint8_t addr ) {
1762 //--------------------------------------------------------------------
1763
1764 register uint8_t line_parity;
1765
1766 uint8_t i;
1767 line_parity = 0;
1768 for(i=0;i<6;i++) {
1769 *forward_ptr++ = addr;
1770 line_parity ^= addr;
1771 addr >>= 1;
1772 }
1773
1774 *forward_ptr++ = (line_parity & 1);
1775
1776 return 7; //return number of emited bits
1777 }
1778
1779 //====================================================================
1780 // prepares data bits intreleaved with parity bits
1781 // see EM4469 spec
1782 //====================================================================
1783
1784 //--------------------------------------------------------------------
1785 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1786 //--------------------------------------------------------------------
1787
1788 register uint8_t line_parity;
1789 register uint8_t column_parity;
1790 register uint8_t i, j;
1791 register uint16_t data;
1792
1793 data = data_low;
1794 column_parity = 0;
1795
1796 for(i=0; i<4; i++) {
1797 line_parity = 0;
1798 for(j=0; j<8; j++) {
1799 line_parity ^= data;
1800 column_parity ^= (data & 1) << j;
1801 *forward_ptr++ = data;
1802 data >>= 1;
1803 }
1804 *forward_ptr++ = line_parity;
1805 if(i == 1)
1806 data = data_hi;
1807 }
1808
1809 for(j=0; j<8; j++) {
1810 *forward_ptr++ = column_parity;
1811 column_parity >>= 1;
1812 }
1813 *forward_ptr = 0;
1814
1815 return 45; //return number of emited bits
1816 }
1817
1818 //====================================================================
1819 // Forward Link send function
1820 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1821 // fwd_bit_count set with number of bits to be sent
1822 //====================================================================
1823 void SendForward(uint8_t fwd_bit_count) {
1824
1825 fwd_write_ptr = forwardLink_data;
1826 fwd_bit_sz = fwd_bit_count;
1827
1828 LED_D_ON();
1829
1830 //Field on
1831 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1832 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1833 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1834
1835 // Give it a bit of time for the resonant antenna to settle.
1836 // And for the tag to fully power up
1837 SpinDelay(150);
1838
1839 // force 1st mod pulse (start gap must be longer for 4305)
1840 fwd_bit_sz--; //prepare next bit modulation
1841 fwd_write_ptr++;
1842 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1843 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1844 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1845 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1846 SpinDelayUs(16*8); //16 cycles on (8us each)
1847
1848 // now start writting
1849 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1850 if(((*fwd_write_ptr++) & 1) == 1)
1851 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1852 else {
1853 //These timings work for 4469/4269/4305 (with the 55*8 above)
1854 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1855 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1856 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1857 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1858 SpinDelayUs(9*8); //16 cycles on (8us each)
1859 }
1860 }
1861 }
1862
1863 void EM4xLogin(uint32_t Password) {
1864
1865 uint8_t fwd_bit_count;
1866
1867 forward_ptr = forwardLink_data;
1868 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1869 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1870
1871 SendForward(fwd_bit_count);
1872
1873 //Wait for command to complete
1874 SpinDelay(20);
1875
1876 }
1877
1878 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1879
1880 uint8_t fwd_bit_count;
1881 uint8_t *dest = (uint8_t *)BigBuf;
1882 int m=0, i=0;
1883
1884 //If password mode do login
1885 if (PwdMode == 1) EM4xLogin(Pwd);
1886
1887 forward_ptr = forwardLink_data;
1888 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1889 fwd_bit_count += Prepare_Addr( Address );
1890
1891 m = sizeof(BigBuf);
1892 // Clear destination buffer before sending the command
1893 memset(dest, 128, m);
1894 // Connect the A/D to the peak-detected low-frequency path.
1895 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1896 // Now set up the SSC to get the ADC samples that are now streaming at us.
1897 FpgaSetupSsc();
1898
1899 SendForward(fwd_bit_count);
1900
1901 // Now do the acquisition
1902 i = 0;
1903 for(;;) {
1904 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1905 AT91C_BASE_SSC->SSC_THR = 0x43;
1906 }
1907 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1908 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1909 i++;
1910 if (i >= m) break;
1911 }
1912 }
1913 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1914 LED_D_OFF();
1915 }
1916
1917 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1918
1919 uint8_t fwd_bit_count;
1920
1921 //If password mode do login
1922 if (PwdMode == 1) EM4xLogin(Pwd);
1923
1924 forward_ptr = forwardLink_data;
1925 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1926 fwd_bit_count += Prepare_Addr( Address );
1927 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1928
1929 SendForward(fwd_bit_count);
1930
1931 //Wait for write to complete
1932 SpinDelay(20);
1933 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1934 LED_D_OFF();
1935 }
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