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1 //-----------------------------------------------------------------------------
2 // Miscellaneous routines for low frequency tag operations.
3 // Tags supported here so far are Texas Instruments (TI), HID
4 // Also routines for raw mode reading/simulating of LF waveform
5 //
6 //-----------------------------------------------------------------------------
7 #include <proxmark3.h>
8 #include "apps.h"
9 #include "../common/crc16.c"
10
11 void AcquireRawAdcSamples125k(BOOL at134khz)
12 {
13 if(at134khz) {
14 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
15 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
16 } else {
17 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
18 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
19 }
20
21 // Connect the A/D to the peak-detected low-frequency path.
22 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
23
24 // Give it a bit of time for the resonant antenna to settle.
25 SpinDelay(50);
26
27 // Now set up the SSC to get the ADC samples that are now streaming at us.
28 FpgaSetupSsc();
29
30 // Now call the acquisition routine
31 DoAcquisition125k(at134khz);
32 }
33
34 // split into two routines so we can avoid timing issues after sending commands //
35 void DoAcquisition125k(BOOL at134khz)
36 {
37 BYTE *dest = (BYTE *)BigBuf;
38 int n = sizeof(BigBuf);
39 int i;
40
41 memset(dest,0,n);
42 i = 0;
43 for(;;) {
44 if(SSC_STATUS & (SSC_STATUS_TX_READY)) {
45 SSC_TRANSMIT_HOLDING = 0x43;
46 LED_D_ON();
47 }
48 if(SSC_STATUS & (SSC_STATUS_RX_READY)) {
49 dest[i] = (BYTE)SSC_RECEIVE_HOLDING;
50 i++;
51 LED_D_OFF();
52 if(i >= n) {
53 break;
54 }
55 }
56 }
57 DbpIntegers(dest[0], dest[1], at134khz);
58 }
59
60 void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYTE *command)
61 {
62 BOOL at134khz;
63
64 // see if 'h' was specified
65 if(command[strlen((char *) command) - 1] == 'h')
66 at134khz= TRUE;
67 else
68 at134khz= FALSE;
69
70 if(at134khz) {
71 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
72 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
73 } else {
74 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
75 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
76 }
77
78 // Give it a bit of time for the resonant antenna to settle.
79 SpinDelay(50);
80
81 // Now set up the SSC to get the ADC samples that are now streaming at us.
82 FpgaSetupSsc();
83
84 // now modulate the reader field
85 while(*command != '\0' && *command != ' ')
86 {
87 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
88 LED_D_OFF();
89 SpinDelayUs(delay_off);
90 if(at134khz) {
91 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
92 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
93 } else {
94 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
95 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
96 }
97 LED_D_ON();
98 if(*(command++) == '0')
99 SpinDelayUs(period_0);
100 else
101 SpinDelayUs(period_1);
102 }
103 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
104 LED_D_OFF();
105 SpinDelayUs(delay_off);
106 if(at134khz) {
107 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
108 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
109 } else {
110 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
111 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
112 }
113
114 // now do the read
115 DoAcquisition125k(at134khz);
116 }
117
118 void AcquireTiType(void)
119 {
120 int i;
121 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
122 // each sample is 1 bit stuffed into a DWORD so we need 1250 DWORDS
123 int n = 1250;
124
125 // clear buffer
126 memset(BigBuf,0,sizeof(BigBuf));
127
128 // Set up the synchronous serial port
129 PIO_DISABLE = (1<<GPIO_SSC_DIN);
130 PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN);
131
132 // steal this pin from the SSP and use it to control the modulation
133 PIO_ENABLE = (1<<GPIO_SSC_DOUT);
134 PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);
135
136 SSC_CONTROL = SSC_CONTROL_RESET;
137 SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;
138
139 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
140 // 48/2 = 24 MHz clock must be divided by 12
141 SSC_CLOCK_DIVISOR = 12;
142
143 SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);
144 SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;
145 SSC_TRANSMIT_CLOCK_MODE = 0;
146 SSC_TRANSMIT_FRAME_MODE = 0;
147
148 LED_D_ON();
149
150 // modulate antenna
151 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
152
153 // Charge TI tag for 50ms.
154 SpinDelay(50);
155
156 // stop modulating antenna and listen
157 PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
158
159 LED_D_OFF();
160
161 i = 0;
162 for(;;) {
163 if(SSC_STATUS & SSC_STATUS_RX_READY) {
164 BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer
165 i++; if(i >= n) return;
166 }
167 WDT_HIT();
168 }
169
170 // return stolen pin to SSP
171 PIO_DISABLE = (1<<GPIO_SSC_DOUT);
172 PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);
173 }
174
175 void ReadTItag()
176 {
177 }
178
179 void WriteTIbyte(BYTE b)
180 {
181 int i = 0;
182
183 // modulate 8 bits out to the antenna
184 for (i=0; i<8; i++)
185 {
186 if (b&(1<<i)) {
187 // stop modulating antenna
188 PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
189 SpinDelayUs(1000);
190 // modulate antenna
191 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
192 SpinDelayUs(1000);
193 } else {
194 // stop modulating antenna
195 PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);
196 SpinDelayUs(300);
197 // modulate antenna
198 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
199 SpinDelayUs(1700);
200 }
201 }
202 }
203
204 void AcquireRawBitsTI(void)
205 {
206 // TI tags charge at 134.2Khz
207 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
208
209 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
210 // connects to SSP_DIN and the SSP_DOUT logic level controls
211 // whether we're modulating the antenna (high)
212 // or listening to the antenna (low)
213 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
214
215 // get TI tag data into the buffer
216 AcquireTiType();
217
218 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
219 }
220
221 // this is a dummy function to get around
222 // a possible flash bug in the bootloader
223 // delete once you've added more code.
224 void DummyDummyDummy(void)
225 {
226 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
227 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
228 AcquireTiType();
229 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
230 }
231
232 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
233 // if crc provided, it will be written with the data verbatim (even if bogus)
234 // if not provided a valid crc will be computed from the data and written.
235 void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)
236 {
237
238 // WARNING the order of the bytes in which we calc crc below needs checking
239 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
240 // bytes in reverse or something
241
242 if(crc == 0) {
243 crc = update_crc16(crc, (idlo)&0xff);
244 crc = update_crc16(crc, (idlo>>8)&0xff);
245 crc = update_crc16(crc, (idlo>>16)&0xff);
246 crc = update_crc16(crc, (idlo>>24)&0xff);
247 crc = update_crc16(crc, (idhi)&0xff);
248 crc = update_crc16(crc, (idhi>>8)&0xff);
249 crc = update_crc16(crc, (idhi>>16)&0xff);
250 crc = update_crc16(crc, (idhi>>24)&0xff);
251 }
252 DbpString("Writing the following data to tag:");
253 DbpIntegers(idhi, idlo, crc);
254
255 // TI tags charge at 134.2Khz
256 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
257 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
258 // connects to SSP_DIN and the SSP_DOUT logic level controls
259 // whether we're modulating the antenna (high)
260 // or listening to the antenna (low)
261 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
262 LED_A_ON();
263
264 // steal this pin from the SSP and use it to control the modulation
265 PIO_ENABLE = (1<<GPIO_SSC_DOUT);
266 PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);
267
268 // writing algorithm:
269 // a high bit consists of a field off for 1ms and field on for 1ms
270 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
271 // initiate a charge time of 50ms (field on) then immediately start writing bits
272 // start by writing 0xBB (keyword) and 0xEB (password)
273 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
274 // finally end with 0x0300 (write frame)
275 // all data is sent lsb firts
276 // finish with 15ms programming time
277
278 // modulate antenna
279 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
280 SpinDelay(50); // charge time
281
282 WriteTIbyte(0xbb); // keyword
283 WriteTIbyte(0xeb); // password
284 WriteTIbyte( (idlo )&0xff );
285 WriteTIbyte( (idlo>>8 )&0xff );
286 WriteTIbyte( (idlo>>16)&0xff );
287 WriteTIbyte( (idlo>>24)&0xff );
288 WriteTIbyte( (idhi )&0xff );
289 WriteTIbyte( (idhi>>8 )&0xff );
290 WriteTIbyte( (idhi>>16)&0xff );
291 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
292 WriteTIbyte( (crc )&0xff ); // crc lo
293 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
294 WriteTIbyte(0x00); // write frame lo
295 WriteTIbyte(0x03); // write frame hi
296 PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);
297 SpinDelay(50); // programming time
298
299 LED_A_OFF();
300
301 // get TI tag data into the buffer
302 AcquireTiType();
303
304 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
305 DbpString("Now use tibits and tidemod");
306 }
307
308 void SimulateTagLowFrequency(int period, int ledcontrol)
309 {
310 int i;
311 BYTE *tab = (BYTE *)BigBuf;
312
313 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);
314
315 PIO_ENABLE = (1 << GPIO_SSC_DOUT) | (1 << GPIO_SSC_CLK);
316
317 PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);
318 PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);
319
320 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
321 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
322
323 i = 0;
324 for(;;) {
325 while(!(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK))) {
326 if(BUTTON_PRESS()) {
327 DbpString("Stopped");
328 return;
329 }
330 WDT_HIT();
331 }
332
333 if (ledcontrol)
334 LED_D_ON();
335
336 if(tab[i])
337 OPEN_COIL();
338 else
339 SHORT_COIL();
340
341 if (ledcontrol)
342 LED_D_OFF();
343
344 while(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK)) {
345 if(BUTTON_PRESS()) {
346 DbpString("Stopped");
347 return;
348 }
349 WDT_HIT();
350 }
351
352 i++;
353 if(i == period) i = 0;
354 }
355 }
356
357 // compose fc/8 fc/10 waveform
358 static void fc(int c, int *n) {
359 BYTE *dest = (BYTE *)BigBuf;
360 int idx;
361
362 // for when we want an fc8 pattern every 4 logical bits
363 if(c==0) {
364 dest[((*n)++)]=1;
365 dest[((*n)++)]=1;
366 dest[((*n)++)]=0;
367 dest[((*n)++)]=0;
368 dest[((*n)++)]=0;
369 dest[((*n)++)]=0;
370 dest[((*n)++)]=0;
371 dest[((*n)++)]=0;
372 }
373 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
374 if(c==8) {
375 for (idx=0; idx<6; idx++) {
376 dest[((*n)++)]=1;
377 dest[((*n)++)]=1;
378 dest[((*n)++)]=0;
379 dest[((*n)++)]=0;
380 dest[((*n)++)]=0;
381 dest[((*n)++)]=0;
382 dest[((*n)++)]=0;
383 dest[((*n)++)]=0;
384 }
385 }
386
387 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
388 if(c==10) {
389 for (idx=0; idx<5; idx++) {
390 dest[((*n)++)]=1;
391 dest[((*n)++)]=1;
392 dest[((*n)++)]=1;
393 dest[((*n)++)]=0;
394 dest[((*n)++)]=0;
395 dest[((*n)++)]=0;
396 dest[((*n)++)]=0;
397 dest[((*n)++)]=0;
398 dest[((*n)++)]=0;
399 dest[((*n)++)]=0;
400 }
401 }
402 }
403
404 // prepare a waveform pattern in the buffer based on the ID given then
405 // simulate a HID tag until the button is pressed
406 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
407 {
408 int n=0, i=0;
409 /*
410 HID tag bitstream format
411 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
412 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
413 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
414 A fc8 is inserted before every 4 bits
415 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
416 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
417 */
418
419 if (hi>0xFFF) {
420 DbpString("Tags can only have 44 bits.");
421 return;
422 }
423 fc(0,&n);
424 // special start of frame marker containing invalid bit sequences
425 fc(8, &n); fc(8, &n); // invalid
426 fc(8, &n); fc(10, &n); // logical 0
427 fc(10, &n); fc(10, &n); // invalid
428 fc(8, &n); fc(10, &n); // logical 0
429
430 WDT_HIT();
431 // manchester encode bits 43 to 32
432 for (i=11; i>=0; i--) {
433 if ((i%4)==3) fc(0,&n);
434 if ((hi>>i)&1) {
435 fc(10, &n); fc(8, &n); // low-high transition
436 } else {
437 fc(8, &n); fc(10, &n); // high-low transition
438 }
439 }
440
441 WDT_HIT();
442 // manchester encode bits 31 to 0
443 for (i=31; i>=0; i--) {
444 if ((i%4)==3) fc(0,&n);
445 if ((lo>>i)&1) {
446 fc(10, &n); fc(8, &n); // low-high transition
447 } else {
448 fc(8, &n); fc(10, &n); // high-low transition
449 }
450 }
451
452 if (ledcontrol)
453 LED_A_ON();
454 SimulateTagLowFrequency(n, ledcontrol);
455
456 if (ledcontrol)
457 LED_A_OFF();
458 }
459
460
461 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
462 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
463 {
464 BYTE *dest = (BYTE *)BigBuf;
465 int m=0, n=0, i=0, idx=0, found=0, lastval=0;
466 DWORD hi=0, lo=0;
467
468 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
469 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
470
471 // Connect the A/D to the peak-detected low-frequency path.
472 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
473
474 // Give it a bit of time for the resonant antenna to settle.
475 SpinDelay(50);
476
477 // Now set up the SSC to get the ADC samples that are now streaming at us.
478 FpgaSetupSsc();
479
480 for(;;) {
481 WDT_HIT();
482 if (ledcontrol)
483 LED_A_ON();
484 if(BUTTON_PRESS()) {
485 DbpString("Stopped");
486 if (ledcontrol)
487 LED_A_OFF();
488 return;
489 }
490
491 i = 0;
492 m = sizeof(BigBuf);
493 memset(dest,128,m);
494 for(;;) {
495 if(SSC_STATUS & (SSC_STATUS_TX_READY)) {
496 SSC_TRANSMIT_HOLDING = 0x43;
497 if (ledcontrol)
498 LED_D_ON();
499 }
500 if(SSC_STATUS & (SSC_STATUS_RX_READY)) {
501 dest[i] = (BYTE)SSC_RECEIVE_HOLDING;
502 // we don't care about actual value, only if it's more or less than a
503 // threshold essentially we capture zero crossings for later analysis
504 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
505 i++;
506 if (ledcontrol)
507 LED_D_OFF();
508 if(i >= m) {
509 break;
510 }
511 }
512 }
513
514 // FSK demodulator
515
516 // sync to first lo-hi transition
517 for( idx=1; idx<m; idx++) {
518 if (dest[idx-1]<dest[idx])
519 lastval=idx;
520 break;
521 }
522 WDT_HIT();
523
524 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
525 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
526 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
527 for( i=0; idx<m; idx++) {
528 if (dest[idx-1]<dest[idx]) {
529 dest[i]=idx-lastval;
530 if (dest[i] <= 8) {
531 dest[i]=1;
532 } else {
533 dest[i]=0;
534 }
535
536 lastval=idx;
537 i++;
538 }
539 }
540 m=i;
541 WDT_HIT();
542
543 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
544 lastval=dest[0];
545 idx=0;
546 i=0;
547 n=0;
548 for( idx=0; idx<m; idx++) {
549 if (dest[idx]==lastval) {
550 n++;
551 } else {
552 // a bit time is five fc/10 or six fc/8 cycles so figure out how many bits a pattern width represents,
553 // an extra fc/8 pattern preceeds every 4 bits (about 200 cycles) just to complicate things but it gets
554 // swallowed up by rounding
555 // expected results are 1 or 2 bits, any more and it's an invalid manchester encoding
556 // special start of frame markers use invalid manchester states (no transitions) by using sequences
557 // like 111000
558 if (dest[idx-1]) {
559 n=(n+1)/6; // fc/8 in sets of 6
560 } else {
561 n=(n+1)/5; // fc/10 in sets of 5
562 }
563 switch (n) { // stuff appropriate bits in buffer
564 case 0:
565 case 1: // one bit
566 dest[i++]=dest[idx-1];
567 break;
568 case 2: // two bits
569 dest[i++]=dest[idx-1];
570 dest[i++]=dest[idx-1];
571 break;
572 case 3: // 3 bit start of frame markers
573 dest[i++]=dest[idx-1];
574 dest[i++]=dest[idx-1];
575 dest[i++]=dest[idx-1];
576 break;
577 // When a logic 0 is immediately followed by the start of the next transmisson
578 // (special pattern) a pattern of 4 bit duration lengths is created.
579 case 4:
580 dest[i++]=dest[idx-1];
581 dest[i++]=dest[idx-1];
582 dest[i++]=dest[idx-1];
583 dest[i++]=dest[idx-1];
584 break;
585 default: // this shouldn't happen, don't stuff any bits
586 break;
587 }
588 n=0;
589 lastval=dest[idx];
590 }
591 }
592 m=i;
593 WDT_HIT();
594
595 // final loop, go over previously decoded manchester data and decode into usable tag ID
596 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
597 for( idx=0; idx<m-6; idx++) {
598 // search for a start of frame marker
599 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
600 {
601 found=1;
602 idx+=6;
603 if (found && (hi|lo)) {
604 DbpString("TAG ID");
605 DbpIntegers(hi, lo, (lo>>1)&0xffff);
606 /* if we're only looking for one tag */
607 if (findone)
608 {
609 *high = hi;
610 *low = lo;
611 return;
612 }
613 hi=0;
614 lo=0;
615 found=0;
616 }
617 }
618 if (found) {
619 if (dest[idx] && (!dest[idx+1]) ) {
620 hi=(hi<<1)|(lo>>31);
621 lo=(lo<<1)|0;
622 } else if ( (!dest[idx]) && dest[idx+1]) {
623 hi=(hi<<1)|(lo>>31);
624 lo=(lo<<1)|1;
625 } else {
626 found=0;
627 hi=0;
628 lo=0;
629 }
630 idx++;
631 }
632 if ( dest[idx] && dest[idx+1] && dest[idx+2] && (!dest[idx+3]) && (!dest[idx+4]) && (!dest[idx+5]) )
633 {
634 found=1;
635 idx+=6;
636 if (found && (hi|lo)) {
637 DbpString("TAG ID");
638 DbpIntegers(hi, lo, (lo>>1)&0xffff);
639 /* if we're only looking for one tag */
640 if (findone)
641 {
642 *high = hi;
643 *low = lo;
644 return;
645 }
646 hi=0;
647 lo=0;
648 found=0;
649 }
650 }
651 }
652 WDT_HIT();
653 }
654 }
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