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1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17
18
19 /**
20 * Does the sample acquisition. If threshold is specified, the actual sampling
21 * is not commenced until the threshold has been reached.
22 * @param trigger_threshold - the threshold
23 * @param silent - is true, now outputs are made. If false, dbprints the status
24 */
25 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
26 {
27 uint8_t *dest = (uint8_t *)BigBuf;
28 int n = sizeof(BigBuf);
29 int i;
30
31 memset(dest, 0, n);
32 i = 0;
33 for(;;) {
34 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
35 AT91C_BASE_SSC->SSC_THR = 0x43;
36 LED_D_ON();
37 }
38 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
39 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
40 LED_D_OFF();
41 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
42 continue;
43 else
44 trigger_threshold = -1;
45 if (++i >= n) break;
46 }
47 }
48 if(!silent)
49 {
50 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
51 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
52
53 }
54 }
55 /**
56 * Perform sample aquisition.
57 */
58 void DoAcquisition125k(int trigger_threshold)
59 {
60 DoAcquisition125k_internal(trigger_threshold, false);
61 }
62
63 /**
64 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
65 * if not already loaded, sets divisor and starts up the antenna.
66 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
67 * 0 or 95 ==> 125 KHz
68 *
69 **/
70 void LFSetupFPGAForADC(int divisor, bool lf_field)
71 {
72 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
73 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
74 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
75 else if (divisor == 0)
76 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
77 else
78 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
79
80 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
81
82 // Connect the A/D to the peak-detected low-frequency path.
83 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
84 // Give it a bit of time for the resonant antenna to settle.
85 SpinDelay(50);
86 // Now set up the SSC to get the ADC samples that are now streaming at us.
87 FpgaSetupSsc();
88 }
89 /**
90 * Initializes the FPGA, and acquires the samples.
91 **/
92 void AcquireRawAdcSamples125k(int divisor)
93 {
94 LFSetupFPGAForADC(divisor, true);
95 // Now call the acquisition routine
96 DoAcquisition125k_internal(-1,false);
97 }
98 /**
99 * Initializes the FPGA for snoop-mode, and acquires the samples.
100 **/
101
102 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
103 {
104 LFSetupFPGAForADC(divisor, false);
105 DoAcquisition125k(trigger_threshold);
106 }
107
108 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
109 {
110
111 /* Make sure the tag is reset */
112 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
113 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
114 SpinDelay(2500);
115
116
117 int divisor_used = 95; // 125 KHz
118 // see if 'h' was specified
119
120 if (command[strlen((char *) command) - 1] == 'h')
121 divisor_used = 88; // 134.8 KHz
122
123
124 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
125 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
126 // Give it a bit of time for the resonant antenna to settle.
127 SpinDelay(50);
128
129 // And a little more time for the tag to fully power up
130 SpinDelay(2000);
131
132 // Now set up the SSC to get the ADC samples that are now streaming at us.
133 FpgaSetupSsc();
134
135 // now modulate the reader field
136 while(*command != '\0' && *command != ' ') {
137 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
138 LED_D_OFF();
139 SpinDelayUs(delay_off);
140 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
141
142 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
143 LED_D_ON();
144 if(*(command++) == '0')
145 SpinDelayUs(period_0);
146 else
147 SpinDelayUs(period_1);
148 }
149 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
150 LED_D_OFF();
151 SpinDelayUs(delay_off);
152 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
153
154 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
155
156 // now do the read
157 DoAcquisition125k(-1);
158 }
159
160 /* blank r/w tag data stream
161 ...0000000000000000 01111111
162 1010101010101010101010101010101010101010101010101010101010101010
163 0011010010100001
164 01111111
165 101010101010101[0]000...
166
167 [5555fe852c5555555555555555fe0000]
168 */
169 void ReadTItag(void)
170 {
171 // some hardcoded initial params
172 // when we read a TI tag we sample the zerocross line at 2Mhz
173 // TI tags modulate a 1 as 16 cycles of 123.2Khz
174 // TI tags modulate a 0 as 16 cycles of 134.2Khz
175 #define FSAMPLE 2000000
176 #define FREQLO 123200
177 #define FREQHI 134200
178
179 signed char *dest = (signed char *)BigBuf;
180 int n = sizeof(BigBuf);
181 // int *dest = GraphBuffer;
182 // int n = GraphTraceLen;
183
184 // 128 bit shift register [shift3:shift2:shift1:shift0]
185 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
186
187 int i, cycles=0, samples=0;
188 // how many sample points fit in 16 cycles of each frequency
189 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
190 // when to tell if we're close enough to one freq or another
191 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
192
193 // TI tags charge at 134.2Khz
194 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
195 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
196
197 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
198 // connects to SSP_DIN and the SSP_DOUT logic level controls
199 // whether we're modulating the antenna (high)
200 // or listening to the antenna (low)
201 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
202
203 // get TI tag data into the buffer
204 AcquireTiType();
205
206 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
207
208 for (i=0; i<n-1; i++) {
209 // count cycles by looking for lo to hi zero crossings
210 if ( (dest[i]<0) && (dest[i+1]>0) ) {
211 cycles++;
212 // after 16 cycles, measure the frequency
213 if (cycles>15) {
214 cycles=0;
215 samples=i-samples; // number of samples in these 16 cycles
216
217 // TI bits are coming to us lsb first so shift them
218 // right through our 128 bit right shift register
219 shift0 = (shift0>>1) | (shift1 << 31);
220 shift1 = (shift1>>1) | (shift2 << 31);
221 shift2 = (shift2>>1) | (shift3 << 31);
222 shift3 >>= 1;
223
224 // check if the cycles fall close to the number
225 // expected for either the low or high frequency
226 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
227 // low frequency represents a 1
228 shift3 |= (1<<31);
229 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
230 // high frequency represents a 0
231 } else {
232 // probably detected a gay waveform or noise
233 // use this as gaydar or discard shift register and start again
234 shift3 = shift2 = shift1 = shift0 = 0;
235 }
236 samples = i;
237
238 // for each bit we receive, test if we've detected a valid tag
239
240 // if we see 17 zeroes followed by 6 ones, we might have a tag
241 // remember the bits are backwards
242 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
243 // if start and end bytes match, we have a tag so break out of the loop
244 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
245 cycles = 0xF0B; //use this as a flag (ugly but whatever)
246 break;
247 }
248 }
249 }
250 }
251 }
252
253 // if flag is set we have a tag
254 if (cycles!=0xF0B) {
255 DbpString("Info: No valid tag detected.");
256 } else {
257 // put 64 bit data into shift1 and shift0
258 shift0 = (shift0>>24) | (shift1 << 8);
259 shift1 = (shift1>>24) | (shift2 << 8);
260
261 // align 16 bit crc into lower half of shift2
262 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
263
264 // if r/w tag, check ident match
265 if ( shift3&(1<<15) ) {
266 DbpString("Info: TI tag is rewriteable");
267 // only 15 bits compare, last bit of ident is not valid
268 if ( ((shift3>>16)^shift0)&0x7fff ) {
269 DbpString("Error: Ident mismatch!");
270 } else {
271 DbpString("Info: TI tag ident is valid");
272 }
273 } else {
274 DbpString("Info: TI tag is readonly");
275 }
276
277 // WARNING the order of the bytes in which we calc crc below needs checking
278 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
279 // bytes in reverse or something
280 // calculate CRC
281 uint32_t crc=0;
282
283 crc = update_crc16(crc, (shift0)&0xff);
284 crc = update_crc16(crc, (shift0>>8)&0xff);
285 crc = update_crc16(crc, (shift0>>16)&0xff);
286 crc = update_crc16(crc, (shift0>>24)&0xff);
287 crc = update_crc16(crc, (shift1)&0xff);
288 crc = update_crc16(crc, (shift1>>8)&0xff);
289 crc = update_crc16(crc, (shift1>>16)&0xff);
290 crc = update_crc16(crc, (shift1>>24)&0xff);
291
292 Dbprintf("Info: Tag data: %x%08x, crc=%x",
293 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
294 if (crc != (shift2&0xffff)) {
295 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
296 } else {
297 DbpString("Info: CRC is good");
298 }
299 }
300 }
301
302 void WriteTIbyte(uint8_t b)
303 {
304 int i = 0;
305
306 // modulate 8 bits out to the antenna
307 for (i=0; i<8; i++)
308 {
309 if (b&(1<<i)) {
310 // stop modulating antenna
311 LOW(GPIO_SSC_DOUT);
312 SpinDelayUs(1000);
313 // modulate antenna
314 HIGH(GPIO_SSC_DOUT);
315 SpinDelayUs(1000);
316 } else {
317 // stop modulating antenna
318 LOW(GPIO_SSC_DOUT);
319 SpinDelayUs(300);
320 // modulate antenna
321 HIGH(GPIO_SSC_DOUT);
322 SpinDelayUs(1700);
323 }
324 }
325 }
326
327 void AcquireTiType(void)
328 {
329 int i, j, n;
330 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
331 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
332 #define TIBUFLEN 1250
333
334 // clear buffer
335 memset(BigBuf,0,sizeof(BigBuf));
336
337 // Set up the synchronous serial port
338 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
339 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
340
341 // steal this pin from the SSP and use it to control the modulation
342 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
343 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
344
345 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
346 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
347
348 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
349 // 48/2 = 24 MHz clock must be divided by 12
350 AT91C_BASE_SSC->SSC_CMR = 12;
351
352 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
353 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
354 AT91C_BASE_SSC->SSC_TCMR = 0;
355 AT91C_BASE_SSC->SSC_TFMR = 0;
356
357 LED_D_ON();
358
359 // modulate antenna
360 HIGH(GPIO_SSC_DOUT);
361
362 // Charge TI tag for 50ms.
363 SpinDelay(50);
364
365 // stop modulating antenna and listen
366 LOW(GPIO_SSC_DOUT);
367
368 LED_D_OFF();
369
370 i = 0;
371 for(;;) {
372 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
373 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
374 i++; if(i >= TIBUFLEN) break;
375 }
376 WDT_HIT();
377 }
378
379 // return stolen pin to SSP
380 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
381 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
382
383 char *dest = (char *)BigBuf;
384 n = TIBUFLEN*32;
385 // unpack buffer
386 for (i=TIBUFLEN-1; i>=0; i--) {
387 for (j=0; j<32; j++) {
388 if(BigBuf[i] & (1 << j)) {
389 dest[--n] = 1;
390 } else {
391 dest[--n] = -1;
392 }
393 }
394 }
395 }
396
397 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
398 // if crc provided, it will be written with the data verbatim (even if bogus)
399 // if not provided a valid crc will be computed from the data and written.
400 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
401 {
402 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
403 if(crc == 0) {
404 crc = update_crc16(crc, (idlo)&0xff);
405 crc = update_crc16(crc, (idlo>>8)&0xff);
406 crc = update_crc16(crc, (idlo>>16)&0xff);
407 crc = update_crc16(crc, (idlo>>24)&0xff);
408 crc = update_crc16(crc, (idhi)&0xff);
409 crc = update_crc16(crc, (idhi>>8)&0xff);
410 crc = update_crc16(crc, (idhi>>16)&0xff);
411 crc = update_crc16(crc, (idhi>>24)&0xff);
412 }
413 Dbprintf("Writing to tag: %x%08x, crc=%x",
414 (unsigned int) idhi, (unsigned int) idlo, crc);
415
416 // TI tags charge at 134.2Khz
417 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
418 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
419 // connects to SSP_DIN and the SSP_DOUT logic level controls
420 // whether we're modulating the antenna (high)
421 // or listening to the antenna (low)
422 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
423 LED_A_ON();
424
425 // steal this pin from the SSP and use it to control the modulation
426 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
427 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
428
429 // writing algorithm:
430 // a high bit consists of a field off for 1ms and field on for 1ms
431 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
432 // initiate a charge time of 50ms (field on) then immediately start writing bits
433 // start by writing 0xBB (keyword) and 0xEB (password)
434 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
435 // finally end with 0x0300 (write frame)
436 // all data is sent lsb firts
437 // finish with 15ms programming time
438
439 // modulate antenna
440 HIGH(GPIO_SSC_DOUT);
441 SpinDelay(50); // charge time
442
443 WriteTIbyte(0xbb); // keyword
444 WriteTIbyte(0xeb); // password
445 WriteTIbyte( (idlo )&0xff );
446 WriteTIbyte( (idlo>>8 )&0xff );
447 WriteTIbyte( (idlo>>16)&0xff );
448 WriteTIbyte( (idlo>>24)&0xff );
449 WriteTIbyte( (idhi )&0xff );
450 WriteTIbyte( (idhi>>8 )&0xff );
451 WriteTIbyte( (idhi>>16)&0xff );
452 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
453 WriteTIbyte( (crc )&0xff ); // crc lo
454 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
455 WriteTIbyte(0x00); // write frame lo
456 WriteTIbyte(0x03); // write frame hi
457 HIGH(GPIO_SSC_DOUT);
458 SpinDelay(50); // programming time
459
460 LED_A_OFF();
461
462 // get TI tag data into the buffer
463 AcquireTiType();
464
465 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
466 DbpString("Now use tiread to check");
467 }
468
469 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
470 {
471 int i;
472 uint8_t *tab = (uint8_t *)BigBuf;
473
474 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
475 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
476
477 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
478
479 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
480 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
481
482 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
483 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
484
485 i = 0;
486 for(;;) {
487 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
488 if(BUTTON_PRESS()) {
489 DbpString("Stopped");
490 return;
491 }
492 WDT_HIT();
493 }
494
495 if (ledcontrol)
496 LED_D_ON();
497
498 if(tab[i])
499 OPEN_COIL();
500 else
501 SHORT_COIL();
502
503 if (ledcontrol)
504 LED_D_OFF();
505
506 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
507 if(BUTTON_PRESS()) {
508 DbpString("Stopped");
509 return;
510 }
511 WDT_HIT();
512 }
513
514 i++;
515 if(i == period) {
516 i = 0;
517 if (gap) {
518 SHORT_COIL();
519 SpinDelayUs(gap);
520 }
521 }
522 }
523 }
524
525 #define DEBUG_FRAME_CONTENTS 1
526 void SimulateTagLowFrequencyBidir(int divisor, int t0)
527 {
528 }
529
530 // compose fc/8 fc/10 waveform
531 static void fc(int c, int *n) {
532 uint8_t *dest = (uint8_t *)BigBuf;
533 int idx;
534
535 // for when we want an fc8 pattern every 4 logical bits
536 if(c==0) {
537 dest[((*n)++)]=1;
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=0;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 }
546 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
547 if(c==8) {
548 for (idx=0; idx<6; idx++) {
549 dest[((*n)++)]=1;
550 dest[((*n)++)]=1;
551 dest[((*n)++)]=0;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 }
558 }
559
560 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
561 if(c==10) {
562 for (idx=0; idx<5; idx++) {
563 dest[((*n)++)]=1;
564 dest[((*n)++)]=1;
565 dest[((*n)++)]=1;
566 dest[((*n)++)]=0;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 dest[((*n)++)]=0;
572 dest[((*n)++)]=0;
573 }
574 }
575 }
576
577 // prepare a waveform pattern in the buffer based on the ID given then
578 // simulate a HID tag until the button is pressed
579 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
580 {
581 int n=0, i=0;
582 /*
583 HID tag bitstream format
584 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
585 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
586 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
587 A fc8 is inserted before every 4 bits
588 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
589 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
590 */
591
592 if (hi>0xFFF) {
593 DbpString("Tags can only have 44 bits.");
594 return;
595 }
596 fc(0,&n);
597 // special start of frame marker containing invalid bit sequences
598 fc(8, &n); fc(8, &n); // invalid
599 fc(8, &n); fc(10, &n); // logical 0
600 fc(10, &n); fc(10, &n); // invalid
601 fc(8, &n); fc(10, &n); // logical 0
602
603 WDT_HIT();
604 // manchester encode bits 43 to 32
605 for (i=11; i>=0; i--) {
606 if ((i%4)==3) fc(0,&n);
607 if ((hi>>i)&1) {
608 fc(10, &n); fc(8, &n); // low-high transition
609 } else {
610 fc(8, &n); fc(10, &n); // high-low transition
611 }
612 }
613
614 WDT_HIT();
615 // manchester encode bits 31 to 0
616 for (i=31; i>=0; i--) {
617 if ((i%4)==3) fc(0,&n);
618 if ((lo>>i)&1) {
619 fc(10, &n); fc(8, &n); // low-high transition
620 } else {
621 fc(8, &n); fc(10, &n); // high-low transition
622 }
623 }
624
625 if (ledcontrol)
626 LED_A_ON();
627 SimulateTagLowFrequency(n, 0, ledcontrol);
628
629 if (ledcontrol)
630 LED_A_OFF();
631 }
632
633 size_t fsk_demod(uint8_t * dest, size_t size)
634 {
635 uint32_t last_transition = 0;
636 uint32_t idx = 1;
637
638 // we don't care about actual value, only if it's more or less than a
639 // threshold essentially we capture zero crossings for later analysis
640 uint8_t threshold_value = 127;
641
642 // sync to first lo-hi transition, and threshold
643
644 //Need to threshold first sample
645 if(dest[0] < threshold_value) dest[0] = 0;
646 else dest[0] = 1;
647
648 size_t numBits = 0;
649 // count cycles between consecutive lo-hi transitions, there should be either 8 (fc/8)
650 // or 10 (fc/10) cycles but in practice due to noise etc we may end up with with anywhere
651 // between 7 to 11 cycles so fuzz it by treat anything <9 as 8 and anything else as 10
652 for(idx = 1; idx < size; idx++) {
653 // threshold current value
654 if (dest[idx] < threshold_value) dest[idx] = 0;
655 else dest[idx] = 1;
656
657 // Check for 0->1 transition
658 if (dest[idx-1] < dest[idx]) { // 0 -> 1 transition
659
660 if (idx-last_transition < 9) {
661 dest[numBits]=1;
662 } else {
663 dest[numBits]=0;
664 }
665 last_transition = idx;
666 numBits++;
667 }
668 }
669 return numBits; //Actually, it returns the number of bytes, but each byte represents a bit: 1 or 0
670 }
671
672
673 size_t aggregate_bits(uint8_t *dest,size_t size, uint8_t h2l_crossing_value,uint8_t l2h_crossing_value, uint8_t maxConsequtiveBits )
674 {
675 uint8_t lastval=dest[0];
676 uint32_t idx=0;
677 size_t numBits=0;
678 uint32_t n=1;
679
680 for( idx=1; idx < size; idx++) {
681
682 if (dest[idx]==lastval) {
683 n++;
684 continue;
685 }
686 //if lastval was 1, we have a 1->0 crossing
687 if ( dest[idx-1] ) {
688 n=(n+1) / h2l_crossing_value;
689 } else {// 0->1 crossing
690 n=(n+1) / l2h_crossing_value;
691 }
692 if (n == 0) n = 1;
693
694 if(n < maxConsequtiveBits)
695 {
696 memset(dest+numBits, dest[idx-1] , n);
697 numBits += n;
698 }
699 n=0;
700 lastval=dest[idx];
701 }//end for
702
703 return numBits;
704
705 }
706 // loop to capture raw HID waveform then FSK demodulate the TAG ID from it
707 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
708 {
709 uint8_t *dest = (uint8_t *)BigBuf;
710
711 size_t size=0,idx=0; //, found=0;
712 uint32_t hi2=0, hi=0, lo=0;
713
714 // Configure to go in 125Khz listen mode
715 LFSetupFPGAForADC(95, true);
716
717 while(!BUTTON_PRESS()) {
718
719 WDT_HIT();
720 if (ledcontrol) LED_A_ON();
721
722 DoAcquisition125k_internal(-1,true);
723 size = sizeof(BigBuf);
724
725 // FSK demodulator
726 size = fsk_demod(dest, size);
727
728 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
729 // 1->0 : fc/8 in sets of 6
730 // 0->1 : fc/10 in sets of 5
731 size = aggregate_bits(dest,size, 6,5,5);
732
733 WDT_HIT();
734
735 // final loop, go over previously decoded manchester data and decode into usable tag ID
736 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
737 uint8_t frame_marker_mask[] = {1,1,1,0,0,0};
738 int numshifts = 0;
739 idx = 0;
740 while( idx + sizeof(frame_marker_mask) < size) {
741 // search for a start of frame marker
742 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
743 { // frame marker found
744 idx+=sizeof(frame_marker_mask);
745
746 while(dest[idx] != dest[idx+1] && idx < size-2)
747 {
748 // Keep going until next frame marker (or error)
749 // Shift in a bit. Start by shifting high registers
750 hi2 = (hi2<<1)|(hi>>31);
751 hi = (hi<<1)|(lo>>31);
752 //Then, shift in a 0 or one into low
753 if (dest[idx] && !dest[idx+1]) // 1 0
754 lo=(lo<<1)|0;
755 else // 0 1
756 lo=(lo<<1)|
757 1;
758 numshifts++;
759 idx += 2;
760 }
761
762 //Dbprintf("Num shifts: %d ", numshifts);
763 // Hopefully, we read a tag and hit upon the next frame marker
764 if(idx + sizeof(frame_marker_mask) < size)
765 {
766 if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
767 {
768 if (hi2 != 0){ //should be large enough for the largest HID tags
769 Dbprintf("TAG ID: %x%08x%08x (%d)",
770 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
771 }
772 else { //standard bits
773 //Dbprintf("TAG ID: %x%08x (%d)",
774 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
775 uint8_t bitlen = 0;
776 uint32_t fc = 0;
777 uint32_t cardnum = 0;
778
779 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
780 uint32_t lo2=0;
781 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
782 uint8_t idx3 = 1;
783 while(lo2>1){ //find last bit set to 1 (format len bit)
784 lo2=lo2>>1;
785 idx3++;
786 }
787 bitlen =idx3+19;
788 fc =0;
789 cardnum=0;
790 if(bitlen==26){
791 cardnum = (lo>>1)&0xFFFF;
792 fc = (lo>>17)&0xFF;
793 }
794 if(bitlen==37){
795 cardnum = (lo>>1)&0x7FFFF;
796 fc = ((hi&0xF)<<12)|(lo>>20);
797 }
798 if(bitlen==34){
799 cardnum = (lo>>1)&0xFFFF;
800 fc= ((hi&1)<<15)|(lo>>17);
801 }
802 if(bitlen==35){
803 cardnum = (lo>>1)&0xFFFFF;
804 fc = ((hi&1)<<11)|(lo>>21);
805 }
806 //Dbprintf("Format Len: %d bit - FC: %d - Card: %d",(unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
807 }
808 else { //if bit 38 is not set then 37 bit format is used
809 bitlen= 37;
810 fc =0;
811 cardnum=0;
812 if(bitlen==37){
813 cardnum = (lo>>1)&0x7FFFF;
814 fc = ((hi&0xF)<<12)|(lo>>20);
815 }
816 }
817 //Dbprintf("TAG ID: %x%08x (%d)",
818 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
819
820 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
821 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
822 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
823 }
824 }
825
826 }
827
828 // reset
829 hi2 = hi = lo = 0;
830 numshifts = 0;
831 }else
832 {
833 idx++;
834 }
835 }
836 WDT_HIT();
837
838 }
839 DbpString("Stopped");
840 if (ledcontrol) LED_A_OFF();
841 }
842
843 uint32_t bytebits_to_byte(uint8_t* src, int numbits)
844 {
845 uint32_t num = 0;
846 for(int i = 0 ; i < numbits ; i++)
847 {
848 num = (num << 1) | (*src);
849 src++;
850 }
851 return num;
852 }
853
854
855 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
856 {
857 uint8_t *dest = (uint8_t *)BigBuf;
858
859 size_t size=0, idx=0;
860 uint32_t code=0, code2=0;
861
862 // Configure to go in 125Khz listen mode
863 LFSetupFPGAForADC(95, true);
864
865 while(!BUTTON_PRESS()) {
866
867
868 WDT_HIT();
869 if (ledcontrol) LED_A_ON();
870
871 DoAcquisition125k_internal(-1,true);
872 size = sizeof(BigBuf);
873
874 // FSK demodulator
875 size = fsk_demod(dest, size);
876
877 // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
878 // 1->0 : fc/8 in sets of 7
879 // 0->1 : fc/10 in sets of 6
880 size = aggregate_bits(dest, size, 7,6,13);
881
882 WDT_HIT();
883
884 //Handle the data
885 uint8_t mask[] = {0,0,0,0,0,0,0,0,0,1};
886 for( idx=0; idx < size - 64; idx++) {
887
888 if ( memcmp(dest + idx, mask, sizeof(mask)) ) continue;
889 Dbprintf("%b",bytebits_to_byte(dest+idx,32));
890 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7]);
891 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+8], dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15]);
892 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+16],dest[idx+17],dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23]);
893 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+24],dest[idx+25],dest[idx+26],dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31]);
894 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35],dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39]);
895 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44],dest[idx+45],dest[idx+46],dest[idx+47]);
896 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53],dest[idx+54],dest[idx+55]);
897 Dbprintf("%d%d%d%d%d%d%d%d",dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
898
899 code = bytebits_to_byte(dest+idx,32);
900 code2 = bytebits_to_byte(dest+idx+32,32);
901
902 short version = bytebits_to_byte(dest+idx+28,8); //14,4
903 char facilitycode = bytebits_to_byte(dest+idx+19,8) ;
904 uint16_t number = (bytebits_to_byte(dest+idx+37,8)<<8)|(bytebits_to_byte(dest+idx+46,8)); //36,9
905
906 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,facilitycode,number,code,code2);
907 if (ledcontrol) LED_D_OFF();
908
909 // if we're only looking for one tag
910 if (findone){
911 LED_A_OFF();
912 return;
913 }
914 }
915 WDT_HIT();
916 }
917 DbpString("Stopped");
918 if (ledcontrol) LED_A_OFF();
919 }
920
921 /*------------------------------
922 * T5555/T5557/T5567 routines
923 *------------------------------
924 */
925
926 /* T55x7 configuration register definitions */
927 #define T55x7_POR_DELAY 0x00000001
928 #define T55x7_ST_TERMINATOR 0x00000008
929 #define T55x7_PWD 0x00000010
930 #define T55x7_MAXBLOCK_SHIFT 5
931 #define T55x7_AOR 0x00000200
932 #define T55x7_PSKCF_RF_2 0
933 #define T55x7_PSKCF_RF_4 0x00000400
934 #define T55x7_PSKCF_RF_8 0x00000800
935 #define T55x7_MODULATION_DIRECT 0
936 #define T55x7_MODULATION_PSK1 0x00001000
937 #define T55x7_MODULATION_PSK2 0x00002000
938 #define T55x7_MODULATION_PSK3 0x00003000
939 #define T55x7_MODULATION_FSK1 0x00004000
940 #define T55x7_MODULATION_FSK2 0x00005000
941 #define T55x7_MODULATION_FSK1a 0x00006000
942 #define T55x7_MODULATION_FSK2a 0x00007000
943 #define T55x7_MODULATION_MANCHESTER 0x00008000
944 #define T55x7_MODULATION_BIPHASE 0x00010000
945 #define T55x7_BITRATE_RF_8 0
946 #define T55x7_BITRATE_RF_16 0x00040000
947 #define T55x7_BITRATE_RF_32 0x00080000
948 #define T55x7_BITRATE_RF_40 0x000C0000
949 #define T55x7_BITRATE_RF_50 0x00100000
950 #define T55x7_BITRATE_RF_64 0x00140000
951 #define T55x7_BITRATE_RF_100 0x00180000
952 #define T55x7_BITRATE_RF_128 0x001C0000
953
954 /* T5555 (Q5) configuration register definitions */
955 #define T5555_ST_TERMINATOR 0x00000001
956 #define T5555_MAXBLOCK_SHIFT 0x00000001
957 #define T5555_MODULATION_MANCHESTER 0
958 #define T5555_MODULATION_PSK1 0x00000010
959 #define T5555_MODULATION_PSK2 0x00000020
960 #define T5555_MODULATION_PSK3 0x00000030
961 #define T5555_MODULATION_FSK1 0x00000040
962 #define T5555_MODULATION_FSK2 0x00000050
963 #define T5555_MODULATION_BIPHASE 0x00000060
964 #define T5555_MODULATION_DIRECT 0x00000070
965 #define T5555_INVERT_OUTPUT 0x00000080
966 #define T5555_PSK_RF_2 0
967 #define T5555_PSK_RF_4 0x00000100
968 #define T5555_PSK_RF_8 0x00000200
969 #define T5555_USE_PWD 0x00000400
970 #define T5555_USE_AOR 0x00000800
971 #define T5555_BITRATE_SHIFT 12
972 #define T5555_FAST_WRITE 0x00004000
973 #define T5555_PAGE_SELECT 0x00008000
974
975 /*
976 * Relevant times in microsecond
977 * To compensate antenna falling times shorten the write times
978 * and enlarge the gap ones.
979 */
980 #define START_GAP 250
981 #define WRITE_GAP 160
982 #define WRITE_0 144 // 192
983 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
984
985 // Write one bit to card
986 void T55xxWriteBit(int bit)
987 {
988 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
989 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
990 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
991 if (bit == 0)
992 SpinDelayUs(WRITE_0);
993 else
994 SpinDelayUs(WRITE_1);
995 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
996 SpinDelayUs(WRITE_GAP);
997 }
998
999 // Write one card block in page 0, no lock
1000 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1001 {
1002 //unsigned int i; //enio adjustment 12/10/14
1003 uint32_t i;
1004
1005 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1006 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1007 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1008
1009 // Give it a bit of time for the resonant antenna to settle.
1010 // And for the tag to fully power up
1011 SpinDelay(150);
1012
1013 // Now start writting
1014 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1015 SpinDelayUs(START_GAP);
1016
1017 // Opcode
1018 T55xxWriteBit(1);
1019 T55xxWriteBit(0); //Page 0
1020 if (PwdMode == 1){
1021 // Pwd
1022 for (i = 0x80000000; i != 0; i >>= 1)
1023 T55xxWriteBit(Pwd & i);
1024 }
1025 // Lock bit
1026 T55xxWriteBit(0);
1027
1028 // Data
1029 for (i = 0x80000000; i != 0; i >>= 1)
1030 T55xxWriteBit(Data & i);
1031
1032 // Block
1033 for (i = 0x04; i != 0; i >>= 1)
1034 T55xxWriteBit(Block & i);
1035
1036 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1037 // so wait a little more)
1038 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1039 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1040 SpinDelay(20);
1041 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1042 }
1043
1044 // Read one card block in page 0
1045 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1046 {
1047 uint8_t *dest = (uint8_t *)BigBuf;
1048 //int m=0, i=0; //enio adjustment 12/10/14
1049 uint32_t m=0, i=0;
1050 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1051 m = sizeof(BigBuf);
1052 // Clear destination buffer before sending the command
1053 memset(dest, 128, m);
1054 // Connect the A/D to the peak-detected low-frequency path.
1055 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1056 // Now set up the SSC to get the ADC samples that are now streaming at us.
1057 FpgaSetupSsc();
1058
1059 LED_D_ON();
1060 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1061 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1062
1063 // Give it a bit of time for the resonant antenna to settle.
1064 // And for the tag to fully power up
1065 SpinDelay(150);
1066
1067 // Now start writting
1068 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1069 SpinDelayUs(START_GAP);
1070
1071 // Opcode
1072 T55xxWriteBit(1);
1073 T55xxWriteBit(0); //Page 0
1074 if (PwdMode == 1){
1075 // Pwd
1076 for (i = 0x80000000; i != 0; i >>= 1)
1077 T55xxWriteBit(Pwd & i);
1078 }
1079 // Lock bit
1080 T55xxWriteBit(0);
1081 // Block
1082 for (i = 0x04; i != 0; i >>= 1)
1083 T55xxWriteBit(Block & i);
1084
1085 // Turn field on to read the response
1086 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1087 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1088
1089 // Now do the acquisition
1090 i = 0;
1091 for(;;) {
1092 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1093 AT91C_BASE_SSC->SSC_THR = 0x43;
1094 }
1095 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1096 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1097 // we don't care about actual value, only if it's more or less than a
1098 // threshold essentially we capture zero crossings for later analysis
1099 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1100 i++;
1101 if (i >= m) break;
1102 }
1103 }
1104
1105 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1106 LED_D_OFF();
1107 DbpString("DONE!");
1108 }
1109
1110 // Read card traceability data (page 1)
1111 void T55xxReadTrace(void){
1112 uint8_t *dest = (uint8_t *)BigBuf;
1113 int m=0, i=0;
1114
1115 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1116 m = sizeof(BigBuf);
1117 // Clear destination buffer before sending the command
1118 memset(dest, 128, m);
1119 // Connect the A/D to the peak-detected low-frequency path.
1120 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1121 // Now set up the SSC to get the ADC samples that are now streaming at us.
1122 FpgaSetupSsc();
1123
1124 LED_D_ON();
1125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1127
1128 // Give it a bit of time for the resonant antenna to settle.
1129 // And for the tag to fully power up
1130 SpinDelay(150);
1131
1132 // Now start writting
1133 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1134 SpinDelayUs(START_GAP);
1135
1136 // Opcode
1137 T55xxWriteBit(1);
1138 T55xxWriteBit(1); //Page 1
1139
1140 // Turn field on to read the response
1141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1142 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1143
1144 // Now do the acquisition
1145 i = 0;
1146 for(;;) {
1147 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1148 AT91C_BASE_SSC->SSC_THR = 0x43;
1149 }
1150 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1151 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1152 i++;
1153 if (i >= m) break;
1154 }
1155 }
1156
1157 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1158 LED_D_OFF();
1159 DbpString("DONE!");
1160 }
1161
1162 /*-------------- Cloning routines -----------*/
1163 // Copy HID id to card and setup block 0 config
1164 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1165 {
1166 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1167 int last_block = 0;
1168
1169 if (longFMT){
1170 // Ensure no more than 84 bits supplied
1171 if (hi2>0xFFFFF) {
1172 DbpString("Tags can only have 84 bits.");
1173 return;
1174 }
1175 // Build the 6 data blocks for supplied 84bit ID
1176 last_block = 6;
1177 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1178 for (int i=0;i<4;i++) {
1179 if (hi2 & (1<<(19-i)))
1180 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1181 else
1182 data1 |= (1<<((3-i)*2)); // 0 -> 01
1183 }
1184
1185 data2 = 0;
1186 for (int i=0;i<16;i++) {
1187 if (hi2 & (1<<(15-i)))
1188 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1189 else
1190 data2 |= (1<<((15-i)*2)); // 0 -> 01
1191 }
1192
1193 data3 = 0;
1194 for (int i=0;i<16;i++) {
1195 if (hi & (1<<(31-i)))
1196 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1197 else
1198 data3 |= (1<<((15-i)*2)); // 0 -> 01
1199 }
1200
1201 data4 = 0;
1202 for (int i=0;i<16;i++) {
1203 if (hi & (1<<(15-i)))
1204 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1205 else
1206 data4 |= (1<<((15-i)*2)); // 0 -> 01
1207 }
1208
1209 data5 = 0;
1210 for (int i=0;i<16;i++) {
1211 if (lo & (1<<(31-i)))
1212 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1213 else
1214 data5 |= (1<<((15-i)*2)); // 0 -> 01
1215 }
1216
1217 data6 = 0;
1218 for (int i=0;i<16;i++) {
1219 if (lo & (1<<(15-i)))
1220 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1221 else
1222 data6 |= (1<<((15-i)*2)); // 0 -> 01
1223 }
1224 }
1225 else {
1226 // Ensure no more than 44 bits supplied
1227 if (hi>0xFFF) {
1228 DbpString("Tags can only have 44 bits.");
1229 return;
1230 }
1231
1232 // Build the 3 data blocks for supplied 44bit ID
1233 last_block = 3;
1234
1235 data1 = 0x1D000000; // load preamble
1236
1237 for (int i=0;i<12;i++) {
1238 if (hi & (1<<(11-i)))
1239 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1240 else
1241 data1 |= (1<<((11-i)*2)); // 0 -> 01
1242 }
1243
1244 data2 = 0;
1245 for (int i=0;i<16;i++) {
1246 if (lo & (1<<(31-i)))
1247 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1248 else
1249 data2 |= (1<<((15-i)*2)); // 0 -> 01
1250 }
1251
1252 data3 = 0;
1253 for (int i=0;i<16;i++) {
1254 if (lo & (1<<(15-i)))
1255 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1256 else
1257 data3 |= (1<<((15-i)*2)); // 0 -> 01
1258 }
1259 }
1260
1261 LED_D_ON();
1262 // Program the data blocks for supplied ID
1263 // and the block 0 for HID format
1264 T55xxWriteBlock(data1,1,0,0);
1265 T55xxWriteBlock(data2,2,0,0);
1266 T55xxWriteBlock(data3,3,0,0);
1267
1268 if (longFMT) { // if long format there are 6 blocks
1269 T55xxWriteBlock(data4,4,0,0);
1270 T55xxWriteBlock(data5,5,0,0);
1271 T55xxWriteBlock(data6,6,0,0);
1272 }
1273
1274 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1275 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1276 T55x7_MODULATION_FSK2a |
1277 last_block << T55x7_MAXBLOCK_SHIFT,
1278 0,0,0);
1279
1280 LED_D_OFF();
1281
1282 DbpString("DONE!");
1283 }
1284
1285 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1286 {
1287 int data1=0, data2=0; //up to six blocks for long format
1288
1289 data1 = hi; // load preamble
1290 data2 = lo;
1291
1292 LED_D_ON();
1293 // Program the data blocks for supplied ID
1294 // and the block 0 for HID format
1295 T55xxWriteBlock(data1,1,0,0);
1296 T55xxWriteBlock(data2,2,0,0);
1297
1298 //Config Block
1299 T55xxWriteBlock(0x00147040,0,0,0);
1300 LED_D_OFF();
1301
1302 DbpString("DONE!");
1303 }
1304
1305 // Define 9bit header for EM410x tags
1306 #define EM410X_HEADER 0x1FF
1307 #define EM410X_ID_LENGTH 40
1308
1309 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1310 {
1311 int i, id_bit;
1312 uint64_t id = EM410X_HEADER;
1313 uint64_t rev_id = 0; // reversed ID
1314 int c_parity[4]; // column parity
1315 int r_parity = 0; // row parity
1316 uint32_t clock = 0;
1317
1318 // Reverse ID bits given as parameter (for simpler operations)
1319 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1320 if (i < 32) {
1321 rev_id = (rev_id << 1) | (id_lo & 1);
1322 id_lo >>= 1;
1323 } else {
1324 rev_id = (rev_id << 1) | (id_hi & 1);
1325 id_hi >>= 1;
1326 }
1327 }
1328
1329 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1330 id_bit = rev_id & 1;
1331
1332 if (i % 4 == 0) {
1333 // Don't write row parity bit at start of parsing
1334 if (i)
1335 id = (id << 1) | r_parity;
1336 // Start counting parity for new row
1337 r_parity = id_bit;
1338 } else {
1339 // Count row parity
1340 r_parity ^= id_bit;
1341 }
1342
1343 // First elements in column?
1344 if (i < 4)
1345 // Fill out first elements
1346 c_parity[i] = id_bit;
1347 else
1348 // Count column parity
1349 c_parity[i % 4] ^= id_bit;
1350
1351 // Insert ID bit
1352 id = (id << 1) | id_bit;
1353 rev_id >>= 1;
1354 }
1355
1356 // Insert parity bit of last row
1357 id = (id << 1) | r_parity;
1358
1359 // Fill out column parity at the end of tag
1360 for (i = 0; i < 4; ++i)
1361 id = (id << 1) | c_parity[i];
1362
1363 // Add stop bit
1364 id <<= 1;
1365
1366 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1367 LED_D_ON();
1368
1369 // Write EM410x ID
1370 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1371 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1372
1373 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1374 if (card) {
1375 // Clock rate is stored in bits 8-15 of the card value
1376 clock = (card & 0xFF00) >> 8;
1377 Dbprintf("Clock rate: %d", clock);
1378 switch (clock)
1379 {
1380 case 32:
1381 clock = T55x7_BITRATE_RF_32;
1382 break;
1383 case 16:
1384 clock = T55x7_BITRATE_RF_16;
1385 break;
1386 case 0:
1387 // A value of 0 is assumed to be 64 for backwards-compatibility
1388 // Fall through...
1389 case 64:
1390 clock = T55x7_BITRATE_RF_64;
1391 break;
1392 default:
1393 Dbprintf("Invalid clock rate: %d", clock);
1394 return;
1395 }
1396
1397 // Writing configuration for T55x7 tag
1398 T55xxWriteBlock(clock |
1399 T55x7_MODULATION_MANCHESTER |
1400 2 << T55x7_MAXBLOCK_SHIFT,
1401 0, 0, 0);
1402 }
1403 else
1404 // Writing configuration for T5555(Q5) tag
1405 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1406 T5555_MODULATION_MANCHESTER |
1407 2 << T5555_MAXBLOCK_SHIFT,
1408 0, 0, 0);
1409
1410 LED_D_OFF();
1411 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1412 (uint32_t)(id >> 32), (uint32_t)id);
1413 }
1414
1415 // Clone Indala 64-bit tag by UID to T55x7
1416 void CopyIndala64toT55x7(int hi, int lo)
1417 {
1418
1419 //Program the 2 data blocks for supplied 64bit UID
1420 // and the block 0 for Indala64 format
1421 T55xxWriteBlock(hi,1,0,0);
1422 T55xxWriteBlock(lo,2,0,0);
1423 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1424 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1425 T55x7_MODULATION_PSK1 |
1426 2 << T55x7_MAXBLOCK_SHIFT,
1427 0, 0, 0);
1428 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1429 // T5567WriteBlock(0x603E1042,0);
1430
1431 DbpString("DONE!");
1432
1433 }
1434
1435 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1436 {
1437
1438 //Program the 7 data blocks for supplied 224bit UID
1439 // and the block 0 for Indala224 format
1440 T55xxWriteBlock(uid1,1,0,0);
1441 T55xxWriteBlock(uid2,2,0,0);
1442 T55xxWriteBlock(uid3,3,0,0);
1443 T55xxWriteBlock(uid4,4,0,0);
1444 T55xxWriteBlock(uid5,5,0,0);
1445 T55xxWriteBlock(uid6,6,0,0);
1446 T55xxWriteBlock(uid7,7,0,0);
1447 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1448 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1449 T55x7_MODULATION_PSK1 |
1450 7 << T55x7_MAXBLOCK_SHIFT,
1451 0,0,0);
1452 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1453 // T5567WriteBlock(0x603E10E2,0);
1454
1455 DbpString("DONE!");
1456
1457 }
1458
1459
1460 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1461 #define max(x,y) ( x<y ? y:x)
1462
1463 int DemodPCF7931(uint8_t **outBlocks) {
1464 uint8_t BitStream[256];
1465 uint8_t Blocks[8][16];
1466 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1467 int GraphTraceLen = sizeof(BigBuf);
1468 int i, j, lastval, bitidx, half_switch;
1469 int clock = 64;
1470 int tolerance = clock / 8;
1471 int pmc, block_done;
1472 int lc, warnings = 0;
1473 int num_blocks = 0;
1474 int lmin=128, lmax=128;
1475 uint8_t dir;
1476
1477 AcquireRawAdcSamples125k(0);
1478
1479 lmin = 64;
1480 lmax = 192;
1481
1482 i = 2;
1483
1484 /* Find first local max/min */
1485 if(GraphBuffer[1] > GraphBuffer[0]) {
1486 while(i < GraphTraceLen) {
1487 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1488 break;
1489 i++;
1490 }
1491 dir = 0;
1492 }
1493 else {
1494 while(i < GraphTraceLen) {
1495 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1496 break;
1497 i++;
1498 }
1499 dir = 1;
1500 }
1501
1502 lastval = i++;
1503 half_switch = 0;
1504 pmc = 0;
1505 block_done = 0;
1506
1507 for (bitidx = 0; i < GraphTraceLen; i++)
1508 {
1509 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1510 {
1511 lc = i - lastval;
1512 lastval = i;
1513
1514 // Switch depending on lc length:
1515 // Tolerance is 1/8 of clock rate (arbitrary)
1516 if (abs(lc-clock/4) < tolerance) {
1517 // 16T0
1518 if((i - pmc) == lc) { /* 16T0 was previous one */
1519 /* It's a PMC ! */
1520 i += (128+127+16+32+33+16)-1;
1521 lastval = i;
1522 pmc = 0;
1523 block_done = 1;
1524 }
1525 else {
1526 pmc = i;
1527 }
1528 } else if (abs(lc-clock/2) < tolerance) {
1529 // 32TO
1530 if((i - pmc) == lc) { /* 16T0 was previous one */
1531 /* It's a PMC ! */
1532 i += (128+127+16+32+33)-1;
1533 lastval = i;
1534 pmc = 0;
1535 block_done = 1;
1536 }
1537 else if(half_switch == 1) {
1538 BitStream[bitidx++] = 0;
1539 half_switch = 0;
1540 }
1541 else
1542 half_switch++;
1543 } else if (abs(lc-clock) < tolerance) {
1544 // 64TO
1545 BitStream[bitidx++] = 1;
1546 } else {
1547 // Error
1548 warnings++;
1549 if (warnings > 10)
1550 {
1551 Dbprintf("Error: too many detection errors, aborting.");
1552 return 0;
1553 }
1554 }
1555
1556 if(block_done == 1) {
1557 if(bitidx == 128) {
1558 for(j=0; j<16; j++) {
1559 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1560 64*BitStream[j*8+6]+
1561 32*BitStream[j*8+5]+
1562 16*BitStream[j*8+4]+
1563 8*BitStream[j*8+3]+
1564 4*BitStream[j*8+2]+
1565 2*BitStream[j*8+1]+
1566 BitStream[j*8];
1567 }
1568 num_blocks++;
1569 }
1570 bitidx = 0;
1571 block_done = 0;
1572 half_switch = 0;
1573 }
1574 if(i < GraphTraceLen)
1575 {
1576 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1577 else dir = 1;
1578 }
1579 }
1580 if(bitidx==255)
1581 bitidx=0;
1582 warnings = 0;
1583 if(num_blocks == 4) break;
1584 }
1585 memcpy(outBlocks, Blocks, 16*num_blocks);
1586 return num_blocks;
1587 }
1588
1589 int IsBlock0PCF7931(uint8_t *Block) {
1590 // Assume RFU means 0 :)
1591 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1592 return 1;
1593 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1594 return 1;
1595 return 0;
1596 }
1597
1598 int IsBlock1PCF7931(uint8_t *Block) {
1599 // Assume RFU means 0 :)
1600 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1601 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1602 return 1;
1603
1604 return 0;
1605 }
1606
1607 #define ALLOC 16
1608
1609 void ReadPCF7931() {
1610 uint8_t Blocks[8][17];
1611 uint8_t tmpBlocks[4][16];
1612 int i, j, ind, ind2, n;
1613 int num_blocks = 0;
1614 int max_blocks = 8;
1615 int ident = 0;
1616 int error = 0;
1617 int tries = 0;
1618
1619 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1620
1621 do {
1622 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1623 n = DemodPCF7931((uint8_t**)tmpBlocks);
1624 if(!n)
1625 error++;
1626 if(error==10 && num_blocks == 0) {
1627 Dbprintf("Error, no tag or bad tag");
1628 return;
1629 }
1630 else if (tries==20 || error==10) {
1631 Dbprintf("Error reading the tag");
1632 Dbprintf("Here is the partial content");
1633 goto end;
1634 }
1635
1636 for(i=0; i<n; i++)
1637 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1638 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1639 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1640 if(!ident) {
1641 for(i=0; i<n; i++) {
1642 if(IsBlock0PCF7931(tmpBlocks[i])) {
1643 // Found block 0 ?
1644 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1645 // Found block 1!
1646 // \o/
1647 ident = 1;
1648 memcpy(Blocks[0], tmpBlocks[i], 16);
1649 Blocks[0][ALLOC] = 1;
1650 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1651 Blocks[1][ALLOC] = 1;
1652 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1653 // Debug print
1654 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1655 num_blocks = 2;
1656 // Handle following blocks
1657 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1658 if(j==n) j=0;
1659 if(j==i) break;
1660 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1661 Blocks[ind2][ALLOC] = 1;
1662 }
1663 break;
1664 }
1665 }
1666 }
1667 }
1668 else {
1669 for(i=0; i<n; i++) { // Look for identical block in known blocks
1670 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1671 for(j=0; j<max_blocks; j++) {
1672 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1673 // Found an identical block
1674 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1675 if(ind2 < 0)
1676 ind2 = max_blocks;
1677 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1678 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1679 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1680 Blocks[ind2][ALLOC] = 1;
1681 num_blocks++;
1682 if(num_blocks == max_blocks) goto end;
1683 }
1684 }
1685 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1686 if(ind2 > max_blocks)
1687 ind2 = 0;
1688 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1689 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1690 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1691 Blocks[ind2][ALLOC] = 1;
1692 num_blocks++;
1693 if(num_blocks == max_blocks) goto end;
1694 }
1695 }
1696 }
1697 }
1698 }
1699 }
1700 }
1701 tries++;
1702 if (BUTTON_PRESS()) return;
1703 } while (num_blocks != max_blocks);
1704 end:
1705 Dbprintf("-----------------------------------------");
1706 Dbprintf("Memory content:");
1707 Dbprintf("-----------------------------------------");
1708 for(i=0; i<max_blocks; i++) {
1709 if(Blocks[i][ALLOC]==1)
1710 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1711 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1712 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1713 else
1714 Dbprintf("<missing block %d>", i);
1715 }
1716 Dbprintf("-----------------------------------------");
1717
1718 return ;
1719 }
1720
1721
1722 //-----------------------------------
1723 // EM4469 / EM4305 routines
1724 //-----------------------------------
1725 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1726 #define FWD_CMD_WRITE 0xA
1727 #define FWD_CMD_READ 0x9
1728 #define FWD_CMD_DISABLE 0x5
1729
1730
1731 uint8_t forwardLink_data[64]; //array of forwarded bits
1732 uint8_t * forward_ptr; //ptr for forward message preparation
1733 uint8_t fwd_bit_sz; //forwardlink bit counter
1734 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1735
1736 //====================================================================
1737 // prepares command bits
1738 // see EM4469 spec
1739 //====================================================================
1740 //--------------------------------------------------------------------
1741 uint8_t Prepare_Cmd( uint8_t cmd ) {
1742 //--------------------------------------------------------------------
1743
1744 *forward_ptr++ = 0; //start bit
1745 *forward_ptr++ = 0; //second pause for 4050 code
1746
1747 *forward_ptr++ = cmd;
1748 cmd >>= 1;
1749 *forward_ptr++ = cmd;
1750 cmd >>= 1;
1751 *forward_ptr++ = cmd;
1752 cmd >>= 1;
1753 *forward_ptr++ = cmd;
1754
1755 return 6; //return number of emited bits
1756 }
1757
1758 //====================================================================
1759 // prepares address bits
1760 // see EM4469 spec
1761 //====================================================================
1762
1763 //--------------------------------------------------------------------
1764 uint8_t Prepare_Addr( uint8_t addr ) {
1765 //--------------------------------------------------------------------
1766
1767 register uint8_t line_parity;
1768
1769 uint8_t i;
1770 line_parity = 0;
1771 for(i=0;i<6;i++) {
1772 *forward_ptr++ = addr;
1773 line_parity ^= addr;
1774 addr >>= 1;
1775 }
1776
1777 *forward_ptr++ = (line_parity & 1);
1778
1779 return 7; //return number of emited bits
1780 }
1781
1782 //====================================================================
1783 // prepares data bits intreleaved with parity bits
1784 // see EM4469 spec
1785 //====================================================================
1786
1787 //--------------------------------------------------------------------
1788 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1789 //--------------------------------------------------------------------
1790
1791 register uint8_t line_parity;
1792 register uint8_t column_parity;
1793 register uint8_t i, j;
1794 register uint16_t data;
1795
1796 data = data_low;
1797 column_parity = 0;
1798
1799 for(i=0; i<4; i++) {
1800 line_parity = 0;
1801 for(j=0; j<8; j++) {
1802 line_parity ^= data;
1803 column_parity ^= (data & 1) << j;
1804 *forward_ptr++ = data;
1805 data >>= 1;
1806 }
1807 *forward_ptr++ = line_parity;
1808 if(i == 1)
1809 data = data_hi;
1810 }
1811
1812 for(j=0; j<8; j++) {
1813 *forward_ptr++ = column_parity;
1814 column_parity >>= 1;
1815 }
1816 *forward_ptr = 0;
1817
1818 return 45; //return number of emited bits
1819 }
1820
1821 //====================================================================
1822 // Forward Link send function
1823 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1824 // fwd_bit_count set with number of bits to be sent
1825 //====================================================================
1826 void SendForward(uint8_t fwd_bit_count) {
1827
1828 fwd_write_ptr = forwardLink_data;
1829 fwd_bit_sz = fwd_bit_count;
1830
1831 LED_D_ON();
1832
1833 //Field on
1834 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1835 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1836 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1837
1838 // Give it a bit of time for the resonant antenna to settle.
1839 // And for the tag to fully power up
1840 SpinDelay(150);
1841
1842 // force 1st mod pulse (start gap must be longer for 4305)
1843 fwd_bit_sz--; //prepare next bit modulation
1844 fwd_write_ptr++;
1845 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1846 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1847 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1848 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1849 SpinDelayUs(16*8); //16 cycles on (8us each)
1850
1851 // now start writting
1852 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1853 if(((*fwd_write_ptr++) & 1) == 1)
1854 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1855 else {
1856 //These timings work for 4469/4269/4305 (with the 55*8 above)
1857 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1858 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1859 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1860 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1861 SpinDelayUs(9*8); //16 cycles on (8us each)
1862 }
1863 }
1864 }
1865
1866 void EM4xLogin(uint32_t Password) {
1867
1868 uint8_t fwd_bit_count;
1869
1870 forward_ptr = forwardLink_data;
1871 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1872 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1873
1874 SendForward(fwd_bit_count);
1875
1876 //Wait for command to complete
1877 SpinDelay(20);
1878
1879 }
1880
1881 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1882
1883 uint8_t fwd_bit_count;
1884 uint8_t *dest = (uint8_t *)BigBuf;
1885 int m=0, i=0;
1886
1887 //If password mode do login
1888 if (PwdMode == 1) EM4xLogin(Pwd);
1889
1890 forward_ptr = forwardLink_data;
1891 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1892 fwd_bit_count += Prepare_Addr( Address );
1893
1894 m = sizeof(BigBuf);
1895 // Clear destination buffer before sending the command
1896 memset(dest, 128, m);
1897 // Connect the A/D to the peak-detected low-frequency path.
1898 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1899 // Now set up the SSC to get the ADC samples that are now streaming at us.
1900 FpgaSetupSsc();
1901
1902 SendForward(fwd_bit_count);
1903
1904 // Now do the acquisition
1905 i = 0;
1906 for(;;) {
1907 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1908 AT91C_BASE_SSC->SSC_THR = 0x43;
1909 }
1910 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1911 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1912 i++;
1913 if (i >= m) break;
1914 }
1915 }
1916 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1917 LED_D_OFF();
1918 }
1919
1920 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1921
1922 uint8_t fwd_bit_count;
1923
1924 //If password mode do login
1925 if (PwdMode == 1) EM4xLogin(Pwd);
1926
1927 forward_ptr = forwardLink_data;
1928 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1929 fwd_bit_count += Prepare_Addr( Address );
1930 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1931
1932 SendForward(fwd_bit_count);
1933
1934 //Wait for write to complete
1935 SpinDelay(20);
1936 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1937 LED_D_OFF();
1938 }
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