git.zerfleddert.de Git - proxmark3-svn/blob - fpga/hi_read_rx_xcorr.v

   1 //-----------------------------------------------------------------------------
   2 //
   3 // Jonathan Westhues, April 2006
   4 //-----------------------------------------------------------------------------
   5
   6 module hi_read_rx_xcorr(
   7     pck0, ck_1356meg, ck_1356megb,
   8     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   9     adc_d, adc_clk,
  10     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  11     cross_hi, cross_lo,
  12     dbg,
  13     snoop
  14 );
  15     input pck0, ck_1356meg, ck_1356megb;
  16     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  17     input [7:0] adc_d;
  18     output adc_clk;
  19     input ssp_dout;
  20     output ssp_frame, ssp_din, ssp_clk;
  21     input cross_hi, cross_lo;
  22     output dbg;
  23     input snoop;
  24
  25 // Carrier is steady on through this, unless we're snooping.
  26 assign pwr_hi = ck_1356megb & (~snoop);
  27 assign pwr_oe1 = 1'b0;
  28 assign pwr_oe3 = 1'b0;
  29 assign pwr_oe4 = 1'b0;
  30
  31 wire adc_clk = ck_1356megb;
  32
  33 // When we're a reader, we just need to do the BPSK demod; but when we're an
  34 // eavesdropper, we also need to pick out the commands sent by the reader,
  35 // using AM. Do this the same way that we do it for the simulated tag.
  36 reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
  37 reg [11:0] has_been_low_for;
  38 always @(negedge adc_clk)
  39 begin
  40     if(& adc_d[7:0]) after_hysteresis <= 1'b1;
  41     else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
  42
  43     if(after_hysteresis)
  44     begin
  45         has_been_low_for <= 7'b0;
  46     end
  47     else
  48     begin
  49         if(has_been_low_for == 12'd4095)
  50         begin
  51             has_been_low_for <= 12'd0;
  52             after_hysteresis <= 1'b1;
  53         end
  54         else
  55             has_been_low_for <= has_been_low_for + 1;
  56     end
  57 end
  58
  59 // Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,
  60 // so we need a 6-bit counter.
  61 reg [5:0] corr_i_cnt;
  62 // And a couple of registers in which to accumulate the correlations.
  63 // we would add at most 32 times adc_d, the result can be held in 13 bits.
  64 // Need one additional bit because it can be negative as well
  65 reg signed [13:0] corr_i_accum;
  66 reg signed [13:0] corr_q_accum;
  67 reg signed [7:0] corr_i_out;
  68 reg signed [7:0] corr_q_out;
  69 // clock and frame signal for communication to ARM
  70 reg ssp_clk;
  71 reg ssp_frame;
  72
  73
  74
  75 // ADC data appears on the rising edge, so sample it on the falling edge
  76 always @(negedge adc_clk)
  77 begin
  78     corr_i_cnt <= corr_i_cnt + 1;
  79
  80     // These are the correlators: we correlate against in-phase and quadrature
  81     // versions of our reference signal, and keep the (signed) result to
  82     // send out later over the SSP.
  83     if(corr_i_cnt == 7'd0)
  84     begin
  85         if(snoop)
  86         begin
  87                         // 7 most significant bits of tag signal (signed), 1 bit reader signal:
  88             corr_i_out <= {corr_i_accum[13:7], after_hysteresis_prev_prev};
  89             corr_q_out <= {corr_q_accum[13:7], after_hysteresis_prev};
  90                         after_hysteresis_prev_prev <= after_hysteresis;
  91         end
  92         else
  93         begin
  94             // 8 most significant bits of tag signal
  95             corr_i_out <= corr_i_accum[13:6];
  96             corr_q_out <= corr_q_accum[13:6];
  97         end
  98
  99         corr_i_accum <= adc_d;
 100         corr_q_accum <= adc_d;
 101     end
 102     else
 103     begin
 104         if(corr_i_cnt[3])
 105             corr_i_accum <= corr_i_accum - adc_d;
 106         else
 107             corr_i_accum <= corr_i_accum + adc_d;
 108
 109         if(corr_i_cnt[3] == corr_i_cnt[2])                      // phase shifted by pi/2
 110             corr_q_accum <= corr_q_accum + adc_d;
 111         else
 112             corr_q_accum <= corr_q_accum - adc_d;
 113
 114     end
 115
 116     // The logic in hi_simulate.v reports 4 samples per bit. We report two
 117     // (I, Q) pairs per bit, so we should do 2 samples per pair.
 118     if(corr_i_cnt == 6'd31)
 119         after_hysteresis_prev <= after_hysteresis;
 120
 121     // Then the result from last time is serialized and send out to the ARM.
 122     // We get one report each cycle, and each report is 16 bits, so the
 123     // ssp_clk should be the adc_clk divided by 64/16 = 4.
 124
 125     if(corr_i_cnt[1:0] == 2'b10)
 126         ssp_clk <= 1'b0;
 127
 128     if(corr_i_cnt[1:0] == 2'b00)
 129     begin
 130         ssp_clk <= 1'b1;
 131         // Don't shift if we just loaded new data, obviously.
 132         if(corr_i_cnt != 7'd0)
 133         begin
 134             corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
 135             corr_q_out[7:1] <= corr_q_out[6:0];
 136         end
 137     end
 138
 139         // set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
 140         // (send two frames with 8 Bits each)
 141     if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
 142         ssp_frame = 1'b1;
 143     else
 144         ssp_frame = 1'b0;
 145
 146 end
 147
 148 assign ssp_din = corr_i_out[7];
 149
 150 assign dbg = corr_i_cnt[3];
 151
 152 // Unused.
 153 assign pwr_lo = 1'b0;
 154 assign pwr_oe2 = 1'b0;
 155
 156 endmodule