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1 //-----------------------------------------------------------------------------
2 // Jonathan Westhues, split Nov 2006
3 //
4 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
5 // at your option, any later version. See the LICENSE.txt file for the text of
6 // the license.
7 //-----------------------------------------------------------------------------
8 // Routines to support ISO 14443B. This includes both the reader software and
9 // the `fake tag' modes.
10 //-----------------------------------------------------------------------------
11
12 #include "proxmark3.h"
13 #include "apps.h"
14 #include "util.h"
15 #include "string.h"
16
17 #include "iso14443crc.h"
18
19 #define RECEIVE_SAMPLES_TIMEOUT 2000
20 #define ISO14443B_DMA_BUFFER_SIZE 256
21
22 //=============================================================================
23 // An ISO 14443 Type B tag. We listen for commands from the reader, using
24 // a UART kind of thing that's implemented in software. When we get a
25 // frame (i.e., a group of bytes between SOF and EOF), we check the CRC.
26 // If it's good, then we can do something appropriate with it, and send
27 // a response.
28 //=============================================================================
29
30 //-----------------------------------------------------------------------------
31 // Code up a string of octets at layer 2 (including CRC, we don't generate
32 // that here) so that they can be transmitted to the reader. Doesn't transmit
33 // them yet, just leaves them ready to send in ToSend[].
34 //-----------------------------------------------------------------------------
35 static void CodeIso14443bAsTag(const uint8_t *cmd, int len)
36 {
37 int i;
38
39 ToSendReset();
40
41 // Transmit a burst of ones, as the initial thing that lets the
42 // reader get phase sync. This (TR1) must be > 80/fs, per spec,
43 // but tag that I've tried (a Paypass) exceeds that by a fair bit,
44 // so I will too.
45 for(i = 0; i < 20; i++) {
46 ToSendStuffBit(1);
47 ToSendStuffBit(1);
48 ToSendStuffBit(1);
49 ToSendStuffBit(1);
50 }
51
52 // Send SOF.
53 for(i = 0; i < 10; i++) {
54 ToSendStuffBit(0);
55 ToSendStuffBit(0);
56 ToSendStuffBit(0);
57 ToSendStuffBit(0);
58 }
59 for(i = 0; i < 2; i++) {
60 ToSendStuffBit(1);
61 ToSendStuffBit(1);
62 ToSendStuffBit(1);
63 ToSendStuffBit(1);
64 }
65
66 for(i = 0; i < len; i++) {
67 int j;
68 uint8_t b = cmd[i];
69
70 // Start bit
71 ToSendStuffBit(0);
72 ToSendStuffBit(0);
73 ToSendStuffBit(0);
74 ToSendStuffBit(0);
75
76 // Data bits
77 for(j = 0; j < 8; j++) {
78 if(b & 1) {
79 ToSendStuffBit(1);
80 ToSendStuffBit(1);
81 ToSendStuffBit(1);
82 ToSendStuffBit(1);
83 } else {
84 ToSendStuffBit(0);
85 ToSendStuffBit(0);
86 ToSendStuffBit(0);
87 ToSendStuffBit(0);
88 }
89 b >>= 1;
90 }
91
92 // Stop bit
93 ToSendStuffBit(1);
94 ToSendStuffBit(1);
95 ToSendStuffBit(1);
96 ToSendStuffBit(1);
97 }
98
99 // Send EOF.
100 for(i = 0; i < 10; i++) {
101 ToSendStuffBit(0);
102 ToSendStuffBit(0);
103 ToSendStuffBit(0);
104 ToSendStuffBit(0);
105 }
106 for(i = 0; i < 2; i++) {
107 ToSendStuffBit(1);
108 ToSendStuffBit(1);
109 ToSendStuffBit(1);
110 ToSendStuffBit(1);
111 }
112
113 // Convert from last byte pos to length
114 ToSendMax++;
115 }
116
117 //-----------------------------------------------------------------------------
118 // The software UART that receives commands from the reader, and its state
119 // variables.
120 //-----------------------------------------------------------------------------
121 static struct {
122 enum {
123 STATE_UNSYNCD,
124 STATE_GOT_FALLING_EDGE_OF_SOF,
125 STATE_AWAITING_START_BIT,
126 STATE_RECEIVING_DATA
127 } state;
128 uint16_t shiftReg;
129 int bitCnt;
130 int byteCnt;
131 int byteCntMax;
132 int posCnt;
133 uint8_t *output;
134 } Uart;
135
136 /* Receive & handle a bit coming from the reader.
137 *
138 * This function is called 4 times per bit (every 2 subcarrier cycles).
139 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 2,36us
140 *
141 * LED handling:
142 * LED A -> ON once we have received the SOF and are expecting the rest.
143 * LED A -> OFF once we have received EOF or are in error state or unsynced
144 *
145 * Returns: true if we received a EOF
146 * false if we are still waiting for some more
147 */
148 static RAMFUNC int Handle14443bUartBit(uint8_t bit)
149 {
150 switch(Uart.state) {
151 case STATE_UNSYNCD:
152 if(!bit) {
153 // we went low, so this could be the beginning
154 // of an SOF
155 Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
156 Uart.posCnt = 0;
157 Uart.bitCnt = 0;
158 }
159 break;
160
161 case STATE_GOT_FALLING_EDGE_OF_SOF:
162 Uart.posCnt++;
163 if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
164 if(bit) {
165 if(Uart.bitCnt > 9) {
166 // we've seen enough consecutive
167 // zeros that it's a valid SOF
168 Uart.posCnt = 0;
169 Uart.byteCnt = 0;
170 Uart.state = STATE_AWAITING_START_BIT;
171 LED_A_ON(); // Indicate we got a valid SOF
172 } else {
173 // didn't stay down long enough
174 // before going high, error
175 Uart.state = STATE_UNSYNCD;
176 }
177 } else {
178 // do nothing, keep waiting
179 }
180 Uart.bitCnt++;
181 }
182 if(Uart.posCnt >= 4) Uart.posCnt = 0;
183 if(Uart.bitCnt > 12) {
184 // Give up if we see too many zeros without
185 // a one, too.
186 LED_A_OFF();
187 Uart.state = STATE_UNSYNCD;
188 }
189 break;
190
191 case STATE_AWAITING_START_BIT:
192 Uart.posCnt++;
193 if(bit) {
194 if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
195 // stayed high for too long between
196 // characters, error
197 Uart.state = STATE_UNSYNCD;
198 }
199 } else {
200 // falling edge, this starts the data byte
201 Uart.posCnt = 0;
202 Uart.bitCnt = 0;
203 Uart.shiftReg = 0;
204 Uart.state = STATE_RECEIVING_DATA;
205 }
206 break;
207
208 case STATE_RECEIVING_DATA:
209 Uart.posCnt++;
210 if(Uart.posCnt == 2) {
211 // time to sample a bit
212 Uart.shiftReg >>= 1;
213 if(bit) {
214 Uart.shiftReg |= 0x200;
215 }
216 Uart.bitCnt++;
217 }
218 if(Uart.posCnt >= 4) {
219 Uart.posCnt = 0;
220 }
221 if(Uart.bitCnt == 10) {
222 if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
223 {
224 // this is a data byte, with correct
225 // start and stop bits
226 Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
227 Uart.byteCnt++;
228
229 if(Uart.byteCnt >= Uart.byteCntMax) {
230 // Buffer overflowed, give up
231 LED_A_OFF();
232 Uart.state = STATE_UNSYNCD;
233 } else {
234 // so get the next byte now
235 Uart.posCnt = 0;
236 Uart.state = STATE_AWAITING_START_BIT;
237 }
238 } else if (Uart.shiftReg == 0x000) {
239 // this is an EOF byte
240 LED_A_OFF(); // Finished receiving
241 Uart.state = STATE_UNSYNCD;
242 if (Uart.byteCnt != 0) {
243 return TRUE;
244 }
245 } else {
246 // this is an error
247 LED_A_OFF();
248 Uart.state = STATE_UNSYNCD;
249 }
250 }
251 break;
252
253 default:
254 LED_A_OFF();
255 Uart.state = STATE_UNSYNCD;
256 break;
257 }
258
259 return FALSE;
260 }
261
262
263 static void UartReset()
264 {
265 Uart.byteCntMax = MAX_FRAME_SIZE;
266 Uart.state = STATE_UNSYNCD;
267 Uart.byteCnt = 0;
268 Uart.bitCnt = 0;
269 }
270
271
272 static void UartInit(uint8_t *data)
273 {
274 Uart.output = data;
275 UartReset();
276 }
277
278
279 //-----------------------------------------------------------------------------
280 // Receive a command (from the reader to us, where we are the simulated tag),
281 // and store it in the given buffer, up to the given maximum length. Keeps
282 // spinning, waiting for a well-framed command, until either we get one
283 // (returns TRUE) or someone presses the pushbutton on the board (FALSE).
284 //
285 // Assume that we're called with the SSC (to the FPGA) and ADC path set
286 // correctly.
287 //-----------------------------------------------------------------------------
288 static int GetIso14443bCommandFromReader(uint8_t *received, uint16_t *len)
289 {
290 // Set FPGA mode to "simulated ISO 14443B tag", no modulation (listen
291 // only, since we are receiving, not transmitting).
292 // Signal field is off with the appropriate LED
293 LED_D_OFF();
294 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
295
296 // Now run a `software UART' on the stream of incoming samples.
297 UartInit(received);
298
299 for(;;) {
300 WDT_HIT();
301
302 if(BUTTON_PRESS()) return FALSE;
303
304 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
305 uint8_t b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
306 for(uint8_t mask = 0x80; mask != 0x00; mask >>= 1) {
307 if(Handle14443bUartBit(b & mask)) {
308 *len = Uart.byteCnt;
309 return TRUE;
310 }
311 }
312 }
313 }
314
315 return FALSE;
316 }
317
318 //-----------------------------------------------------------------------------
319 // Main loop of simulated tag: receive commands from reader, decide what
320 // response to send, and send it.
321 //-----------------------------------------------------------------------------
322 void SimulateIso14443bTag(void)
323 {
324 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
325 BigBuf_free();
326
327 // the only commands we understand is REQB, AFI=0, Select All, N=0:
328 static const uint8_t cmd1[] = { 0x05, 0x00, 0x08, 0x39, 0x73 };
329 // ... and REQB, AFI=0, Normal Request, N=0:
330 static const uint8_t cmd2[] = { 0x05, 0x00, 0x00, 0x71, 0xFF };
331
332 // ... and we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
333 // supports only 106kBit/s in both directions, max frame size = 32Bytes,
334 // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
335 static const uint8_t response1[] = {
336 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
337 0x00, 0x21, 0x85, 0x5e, 0xd7
338 };
339
340 clear_trace();
341 set_tracing(TRUE);
342
343 const uint8_t *resp;
344 uint8_t *respCode;
345 uint16_t respLen, respCodeLen;
346 uint16_t len;
347 uint16_t cmdsRecvd = 0;
348
349
350 // allocate command receive buffer
351 uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
352
353 // prepare the (only one) tag answer:
354 CodeIso14443bAsTag(response1, sizeof(response1));
355
356 uint8_t *resp1Code = BigBuf_malloc(ToSendMax);
357 memcpy(resp1Code, ToSend, ToSendMax);
358 uint16_t resp1CodeLen = ToSendMax;
359
360 // We need to listen to the high-frequency, peak-detected path.
361 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
362 FpgaSetupSsc();
363
364 cmdsRecvd = 0;
365
366 for(;;) {
367
368 if(!GetIso14443bCommandFromReader(receivedCmd, &len)) {
369 Dbprintf("button pressed, received %d commands", cmdsRecvd);
370 break;
371 }
372
373 if (tracing) {
374 uint8_t parity[MAX_PARITY_SIZE];
375 LogTrace(receivedCmd, len, 0, 0, parity, TRUE);
376 }
377
378 // Good, look at the command now.
379 if ( (len == sizeof(cmd1) && memcmp(receivedCmd, cmd1, len) == 0)
380 || (len == sizeof(cmd2) && memcmp(receivedCmd, cmd2, len) == 0) ) {
381 resp = response1;
382 respLen = sizeof(response1);
383 respCode = resp1Code;
384 respCodeLen = resp1CodeLen;
385 } else {
386 Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
387 // And print whether the CRC fails, just for good measure
388 uint8_t b1, b2;
389 ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
390 if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1]) {
391 // Not so good, try again.
392 DbpString("+++CRC fail");
393 } else {
394 DbpString("CRC passes");
395 }
396 break;
397 }
398
399 cmdsRecvd++;
400
401 if(cmdsRecvd > 0x30) {
402 DbpString("many commands later...");
403 break;
404 }
405
406 if(respCodeLen <= 0) continue;
407
408 // Modulate BPSK
409 // Signal field is off with the appropriate LED
410 LED_D_OFF();
411 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
412 AT91C_BASE_SSC->SSC_THR = 0xff;
413 FpgaSetupSsc();
414
415 uint8_t c;
416 // clear receiving shift register and holding register
417 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
418 c = AT91C_BASE_SSC->SSC_RHR; (void) c;
419 while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
420 c = AT91C_BASE_SSC->SSC_RHR; (void) c;
421
422 // Clear TXRDY:
423 AT91C_BASE_SSC->SSC_THR = 0x00;
424
425 // Transmit the response.
426 uint16_t FpgaSendQueueDelay = 0;
427 uint16_t i = 0;
428 for(;i < respCodeLen; ) {
429 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
430 AT91C_BASE_SSC->SSC_THR = respCode[i++];
431 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
432 }
433 if(BUTTON_PRESS()) break;
434 }
435
436 // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
437 uint8_t fpga_queued_bits = FpgaSendQueueDelay >> 3;
438 for (i = 0; i <= fpga_queued_bits/8 + 1; ) {
439 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
440 AT91C_BASE_SSC->SSC_THR = 0x00;
441 FpgaSendQueueDelay = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
442 i++;
443 }
444 }
445
446 // trace the response:
447 if (tracing) {
448 uint8_t parity[MAX_PARITY_SIZE];
449 LogTrace(resp, respLen, 0, 0, parity, FALSE);
450 }
451
452 }
453 }
454
455 //=============================================================================
456 // An ISO 14443 Type B reader. We take layer two commands, code them
457 // appropriately, and then send them to the tag. We then listen for the
458 // tag's response, which we leave in the buffer to be demodulated on the
459 // PC side.
460 //=============================================================================
461
462 static struct {
463 enum {
464 DEMOD_UNSYNCD,
465 DEMOD_PHASE_REF_TRAINING,
466 DEMOD_AWAITING_FALLING_EDGE_OF_SOF,
467 DEMOD_GOT_FALLING_EDGE_OF_SOF,
468 DEMOD_AWAITING_START_BIT,
469 DEMOD_RECEIVING_DATA
470 } state;
471 int bitCount;
472 int posCount;
473 int thisBit;
474 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
475 int metric;
476 int metricN;
477 */
478 uint16_t shiftReg;
479 uint8_t *output;
480 int len;
481 int sumI;
482 int sumQ;
483 } Demod;
484
485 /*
486 * Handles reception of a bit from the tag
487 *
488 * This function is called 2 times per bit (every 4 subcarrier cycles).
489 * Subcarrier frequency fs is 848kHz, 1/fs = 1,18us, i.e. function is called every 4,72us
490 *
491 * LED handling:
492 * LED C -> ON once we have received the SOF and are expecting the rest.
493 * LED C -> OFF once we have received EOF or are unsynced
494 *
495 * Returns: true if we received a EOF
496 * false if we are still waiting for some more
497 *
498 */
499 static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
500 {
501 int v;
502
503 // The soft decision on the bit uses an estimate of just the
504 // quadrant of the reference angle, not the exact angle.
505 #define MAKE_SOFT_DECISION() { \
506 if(Demod.sumI > 0) { \
507 v = ci; \
508 } else { \
509 v = -ci; \
510 } \
511 if(Demod.sumQ > 0) { \
512 v += cq; \
513 } else { \
514 v -= cq; \
515 } \
516 }
517
518 #define SUBCARRIER_DETECT_THRESHOLD 8
519
520 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
521 /* #define CHECK_FOR_SUBCARRIER() { \
522 v = ci; \
523 if(v < 0) v = -v; \
524 if(cq > 0) { \
525 v += cq; \
526 } else { \
527 v -= cq; \
528 } \
529 }
530 */
531 // Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
532 #define CHECK_FOR_SUBCARRIER() { \
533 if(ci < 0) { \
534 if(cq < 0) { /* ci < 0, cq < 0 */ \
535 if (cq < ci) { \
536 v = -cq - (ci >> 1); \
537 } else { \
538 v = -ci - (cq >> 1); \
539 } \
540 } else { /* ci < 0, cq >= 0 */ \
541 if (cq < -ci) { \
542 v = -ci + (cq >> 1); \
543 } else { \
544 v = cq - (ci >> 1); \
545 } \
546 } \
547 } else { \
548 if(cq < 0) { /* ci >= 0, cq < 0 */ \
549 if (-cq < ci) { \
550 v = ci - (cq >> 1); \
551 } else { \
552 v = -cq + (ci >> 1); \
553 } \
554 } else { /* ci >= 0, cq >= 0 */ \
555 if (cq < ci) { \
556 v = ci + (cq >> 1); \
557 } else { \
558 v = cq + (ci >> 1); \
559 } \
560 } \
561 } \
562 }
563
564 switch(Demod.state) {
565 case DEMOD_UNSYNCD:
566 CHECK_FOR_SUBCARRIER();
567 if(v > SUBCARRIER_DETECT_THRESHOLD) { // subcarrier detected
568 Demod.state = DEMOD_PHASE_REF_TRAINING;
569 Demod.sumI = ci;
570 Demod.sumQ = cq;
571 Demod.posCount = 1;
572 }
573 break;
574
575 case DEMOD_PHASE_REF_TRAINING:
576 if(Demod.posCount < 8) {
577 CHECK_FOR_SUBCARRIER();
578 if (v > SUBCARRIER_DETECT_THRESHOLD) {
579 // set the reference phase (will code a logic '1') by averaging over 32 1/fs.
580 // note: synchronization time > 80 1/fs
581 Demod.sumI += ci;
582 Demod.sumQ += cq;
583 Demod.posCount++;
584 } else { // subcarrier lost
585 Demod.state = DEMOD_UNSYNCD;
586 }
587 } else {
588 Demod.state = DEMOD_AWAITING_FALLING_EDGE_OF_SOF;
589 }
590 break;
591
592 case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
593 MAKE_SOFT_DECISION();
594 if(v < 0) { // logic '0' detected
595 Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
596 Demod.posCount = 0; // start of SOF sequence
597 } else {
598 if(Demod.posCount > 200/4) { // maximum length of TR1 = 200 1/fs
599 Demod.state = DEMOD_UNSYNCD;
600 }
601 }
602 Demod.posCount++;
603 break;
604
605 case DEMOD_GOT_FALLING_EDGE_OF_SOF:
606 Demod.posCount++;
607 MAKE_SOFT_DECISION();
608 if(v > 0) {
609 if(Demod.posCount < 9*2) { // low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
610 Demod.state = DEMOD_UNSYNCD;
611 } else {
612 LED_C_ON(); // Got SOF
613 Demod.state = DEMOD_AWAITING_START_BIT;
614 Demod.posCount = 0;
615 Demod.len = 0;
616 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
617 Demod.metricN = 0;
618 Demod.metric = 0;
619 */
620 }
621 } else {
622 if(Demod.posCount > 12*2) { // low phase of SOF too long (> 12 etu)
623 Demod.state = DEMOD_UNSYNCD;
624 LED_C_OFF();
625 }
626 }
627 break;
628
629 case DEMOD_AWAITING_START_BIT:
630 Demod.posCount++;
631 MAKE_SOFT_DECISION();
632 if(v > 0) {
633 if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
634 Demod.state = DEMOD_UNSYNCD;
635 LED_C_OFF();
636 }
637 } else { // start bit detected
638 Demod.bitCount = 0;
639 Demod.posCount = 1; // this was the first half
640 Demod.thisBit = v;
641 Demod.shiftReg = 0;
642 Demod.state = DEMOD_RECEIVING_DATA;
643 }
644 break;
645
646 case DEMOD_RECEIVING_DATA:
647 MAKE_SOFT_DECISION();
648 if(Demod.posCount == 0) { // first half of bit
649 Demod.thisBit = v;
650 Demod.posCount = 1;
651 } else { // second half of bit
652 Demod.thisBit += v;
653
654 /* this had been used to add RSSI (Received Signal Strength Indication) to traces. Currently not implemented.
655 if(Demod.thisBit > 0) {
656 Demod.metric += Demod.thisBit;
657 } else {
658 Demod.metric -= Demod.thisBit;
659 }
660 (Demod.metricN)++;
661 */
662
663 Demod.shiftReg >>= 1;
664 if(Demod.thisBit > 0) { // logic '1'
665 Demod.shiftReg |= 0x200;
666 }
667
668 Demod.bitCount++;
669 if(Demod.bitCount == 10) {
670 uint16_t s = Demod.shiftReg;
671 if((s & 0x200) && !(s & 0x001)) { // stop bit == '1', start bit == '0'
672 uint8_t b = (s >> 1);
673 Demod.output[Demod.len] = b;
674 Demod.len++;
675 Demod.state = DEMOD_AWAITING_START_BIT;
676 } else {
677 Demod.state = DEMOD_UNSYNCD;
678 LED_C_OFF();
679 if(s == 0x000) {
680 // This is EOF (start, stop and all data bits == '0'
681 return TRUE;
682 }
683 }
684 }
685 Demod.posCount = 0;
686 }
687 break;
688
689 default:
690 Demod.state = DEMOD_UNSYNCD;
691 LED_C_OFF();
692 break;
693 }
694
695 return FALSE;
696 }
697
698
699 static void DemodReset()
700 {
701 // Clear out the state of the "UART" that receives from the tag.
702 Demod.len = 0;
703 Demod.state = DEMOD_UNSYNCD;
704 Demod.posCount = 0;
705 memset(Demod.output, 0x00, MAX_FRAME_SIZE);
706 }
707
708
709 static void DemodInit(uint8_t *data)
710 {
711 Demod.output = data;
712 DemodReset();
713 }
714
715
716 /*
717 * Demodulate the samples we received from the tag, also log to tracebuffer
718 * quiet: set to 'TRUE' to disable debug output
719 */
720 static void GetSamplesFor14443bDemod(int n, bool quiet)
721 {
722 int max = 0;
723 bool gotFrame = FALSE;
724 int lastRxCounter, ci, cq, samples = 0;
725
726 // Allocate memory from BigBuf for some buffers
727 // free all previous allocations first
728 BigBuf_free();
729
730 // The response (tag -> reader) that we're receiving.
731 uint8_t *receivedResponse = BigBuf_malloc(MAX_FRAME_SIZE);
732
733 // The DMA buffer, used to stream samples from the FPGA
734 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
735
736 // Set up the demodulator for tag -> reader responses.
737 DemodInit(receivedResponse);
738
739 // Setup and start DMA.
740 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
741
742 int8_t *upTo = dmaBuf;
743 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
744
745 // Signal field is ON with the appropriate LED:
746 LED_D_ON();
747 // And put the FPGA in the appropriate mode
748 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
749
750 for(;;) {
751 int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
752 if(behindBy > max) max = behindBy;
753
754 while(((lastRxCounter-AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1)) > 2) {
755 ci = upTo[0];
756 cq = upTo[1];
757 upTo += 2;
758 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
759 upTo = dmaBuf;
760 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
761 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
762 }
763 lastRxCounter -= 2;
764 if(lastRxCounter <= 0) {
765 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
766 }
767
768 samples += 2;
769
770 if(Handle14443bSamplesDemod(ci, cq)) {
771 gotFrame = TRUE;
772 break;
773 }
774 }
775
776 if(samples > n || gotFrame) {
777 break;
778 }
779 }
780
781 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
782
783 if (!quiet) Dbprintf("max behindby = %d, samples = %d, gotFrame = %d, Demod.len = %d, Demod.sumI = %d, Demod.sumQ = %d", max, samples, gotFrame, Demod.len, Demod.sumI, Demod.sumQ);
784 //Tracing
785 if (tracing && Demod.len > 0) {
786 uint8_t parity[MAX_PARITY_SIZE];
787 LogTrace(Demod.output, Demod.len, 0, 0, parity, FALSE);
788 }
789 }
790
791
792 //-----------------------------------------------------------------------------
793 // Transmit the command (to the tag) that was placed in ToSend[].
794 //-----------------------------------------------------------------------------
795 static void TransmitFor14443b(void)
796 {
797 int c;
798
799 FpgaSetupSsc();
800
801 while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
802 AT91C_BASE_SSC->SSC_THR = 0xff;
803 }
804
805 // Signal field is ON with the appropriate Red LED
806 LED_D_ON();
807 // Signal we are transmitting with the Green LED
808 LED_B_ON();
809 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
810
811 for(c = 0; c < 10;) {
812 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
813 AT91C_BASE_SSC->SSC_THR = 0xff;
814 c++;
815 }
816 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
817 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
818 (void)r;
819 }
820 WDT_HIT();
821 }
822
823 c = 0;
824 for(;;) {
825 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
826 AT91C_BASE_SSC->SSC_THR = ToSend[c];
827 c++;
828 if(c >= ToSendMax) {
829 break;
830 }
831 }
832 if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
833 volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
834 (void)r;
835 }
836 WDT_HIT();
837 }
838 LED_B_OFF(); // Finished sending
839 }
840
841
842 //-----------------------------------------------------------------------------
843 // Code a layer 2 command (string of octets, including CRC) into ToSend[],
844 // so that it is ready to transmit to the tag using TransmitFor14443b().
845 //-----------------------------------------------------------------------------
846 static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
847 {
848 int i, j;
849 uint8_t b;
850
851 ToSendReset();
852
853 // Establish initial reference level
854 for(i = 0; i < 40; i++) {
855 ToSendStuffBit(1);
856 }
857 // Send SOF
858 for(i = 0; i < 10; i++) {
859 ToSendStuffBit(0);
860 }
861
862 for(i = 0; i < len; i++) {
863 // Stop bits/EGT
864 ToSendStuffBit(1);
865 ToSendStuffBit(1);
866 // Start bit
867 ToSendStuffBit(0);
868 // Data bits
869 b = cmd[i];
870 for(j = 0; j < 8; j++) {
871 if(b & 1) {
872 ToSendStuffBit(1);
873 } else {
874 ToSendStuffBit(0);
875 }
876 b >>= 1;
877 }
878 }
879 // Send EOF
880 ToSendStuffBit(1);
881 for(i = 0; i < 10; i++) {
882 ToSendStuffBit(0);
883 }
884 for(i = 0; i < 8; i++) {
885 ToSendStuffBit(1);
886 }
887
888 // And then a little more, to make sure that the last character makes
889 // it out before we switch to rx mode.
890 for(i = 0; i < 24; i++) {
891 ToSendStuffBit(1);
892 }
893
894 // Convert from last character reference to length
895 ToSendMax++;
896 }
897
898
899 /**
900 Convenience function to encode, transmit and trace iso 14443b comms
901 **/
902 static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len)
903 {
904 CodeIso14443bAsReader(cmd, len);
905 TransmitFor14443b();
906 if (tracing) {
907 uint8_t parity[MAX_PARITY_SIZE];
908 LogTrace(cmd,len, 0, 0, parity, TRUE);
909 }
910 }
911
912
913 //-----------------------------------------------------------------------------
914 // Read a SRI512 ISO 14443B tag.
915 //
916 // SRI512 tags are just simple memory tags, here we're looking at making a dump
917 // of the contents of the memory. No anticollision algorithm is done, we assume
918 // we have a single tag in the field.
919 //
920 // I tried to be systematic and check every answer of the tag, every CRC, etc...
921 //-----------------------------------------------------------------------------
922 void ReadSTMemoryIso14443b(uint32_t dwLast)
923 {
924 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
925
926 clear_trace();
927 set_tracing(TRUE);
928
929 uint8_t i = 0x00;
930
931 // Make sure that we start from off, since the tags are stateful;
932 // confusing things will happen if we don't reset them between reads.
933 LED_D_OFF();
934 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
935 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
936 FpgaSetupSsc();
937
938 // Now give it time to spin up.
939 // Signal field is on with the appropriate LED
940 LED_D_ON();
941 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
942 SpinDelay(200);
943
944 // First command: wake up the tag using the INITIATE command
945 uint8_t cmd1[] = {0x06, 0x00, 0x97, 0x5b};
946 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
947 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
948
949 if (Demod.len == 0) {
950 DbpString("No response from tag");
951 return;
952 } else {
953 Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
954 Demod.output[0], Demod.output[1], Demod.output[2]);
955 }
956
957 // There is a response, SELECT the uid
958 DbpString("Now SELECT tag:");
959 cmd1[0] = 0x0E; // 0x0E is SELECT
960 cmd1[1] = Demod.output[0];
961 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
962 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
963 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
964 if (Demod.len != 3) {
965 Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
966 return;
967 }
968 // Check the CRC of the answer:
969 ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
970 if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
971 DbpString("CRC Error reading select response.");
972 return;
973 }
974 // Check response from the tag: should be the same UID as the command we just sent:
975 if (cmd1[1] != Demod.output[0]) {
976 Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
977 return;
978 }
979
980 // Tag is now selected,
981 // First get the tag's UID:
982 cmd1[0] = 0x0B;
983 ComputeCrc14443(CRC_14443_B, cmd1, 1 , &cmd1[1], &cmd1[2]);
984 CodeAndTransmit14443bAsReader(cmd1, 3); // Only first three bytes for this one
985 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
986 if (Demod.len != 10) {
987 Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
988 return;
989 }
990 // The check the CRC of the answer (use cmd1 as temporary variable):
991 ComputeCrc14443(CRC_14443_B, Demod.output, 8, &cmd1[2], &cmd1[3]);
992 if(cmd1[2] != Demod.output[8] || cmd1[3] != Demod.output[9]) {
993 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
994 (cmd1[2]<<8)+cmd1[3], (Demod.output[8]<<8)+Demod.output[9]);
995 // Do not return;, let's go on... (we should retry, maybe ?)
996 }
997 Dbprintf("Tag UID (64 bits): %08x %08x",
998 (Demod.output[7]<<24) + (Demod.output[6]<<16) + (Demod.output[5]<<8) + Demod.output[4],
999 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0]);
1000
1001 // Now loop to read all 16 blocks, address from 0 to last block
1002 Dbprintf("Tag memory dump, block 0 to %d", dwLast);
1003 cmd1[0] = 0x08;
1004 i = 0x00;
1005 dwLast++;
1006 for (;;) {
1007 if (i == dwLast) {
1008 DbpString("System area block (0xff):");
1009 i = 0xff;
1010 }
1011 cmd1[1] = i;
1012 ComputeCrc14443(CRC_14443_B, cmd1, 2, &cmd1[2], &cmd1[3]);
1013 CodeAndTransmit14443bAsReader(cmd1, sizeof(cmd1));
1014 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1015 if (Demod.len != 6) { // Check if we got an answer from the tag
1016 DbpString("Expected 6 bytes from tag, got less...");
1017 return;
1018 }
1019 // The check the CRC of the answer (use cmd1 as temporary variable):
1020 ComputeCrc14443(CRC_14443_B, Demod.output, 4, &cmd1[2], &cmd1[3]);
1021 if(cmd1[2] != Demod.output[4] || cmd1[3] != Demod.output[5]) {
1022 Dbprintf("CRC Error reading block! Expected: %04x got: %04x",
1023 (cmd1[2]<<8)+cmd1[3], (Demod.output[4]<<8)+Demod.output[5]);
1024 // Do not return;, let's go on... (we should retry, maybe ?)
1025 }
1026 // Now print out the memory location:
1027 Dbprintf("Address=%02x, Contents=%08x, CRC=%04x", i,
1028 (Demod.output[3]<<24) + (Demod.output[2]<<16) + (Demod.output[1]<<8) + Demod.output[0],
1029 (Demod.output[4]<<8)+Demod.output[5]);
1030 if (i == 0xff) {
1031 break;
1032 }
1033 i++;
1034 }
1035 }
1036
1037
1038 //=============================================================================
1039 // Finally, the `sniffer' combines elements from both the reader and
1040 // simulated tag, to show both sides of the conversation.
1041 //=============================================================================
1042
1043 //-----------------------------------------------------------------------------
1044 // Record the sequence of commands sent by the reader to the tag, with
1045 // triggering so that we start recording at the point that the tag is moved
1046 // near the reader.
1047 //-----------------------------------------------------------------------------
1048 /*
1049 * Memory usage for this function, (within BigBuf)
1050 * Last Received command (reader->tag) - MAX_FRAME_SIZE
1051 * Last Received command (tag->reader) - MAX_FRAME_SIZE
1052 * DMA Buffer - ISO14443B_DMA_BUFFER_SIZE
1053 * Demodulated samples received - all the rest
1054 */
1055 void RAMFUNC SnoopIso14443b(void)
1056 {
1057 // We won't start recording the frames that we acquire until we trigger;
1058 // a good trigger condition to get started is probably when we see a
1059 // response from the tag.
1060 int triggered = TRUE; // TODO: set and evaluate trigger condition
1061
1062 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1063 BigBuf_free();
1064
1065 clear_trace();
1066 set_tracing(TRUE);
1067
1068 // The DMA buffer, used to stream samples from the FPGA
1069 int8_t *dmaBuf = (int8_t*) BigBuf_malloc(ISO14443B_DMA_BUFFER_SIZE);
1070 int lastRxCounter;
1071 int8_t *upTo;
1072 int ci, cq;
1073 int maxBehindBy = 0;
1074
1075 // Count of samples received so far, so that we can include timing
1076 // information in the trace buffer.
1077 int samples = 0;
1078
1079 DemodInit(BigBuf_malloc(MAX_FRAME_SIZE));
1080 UartInit(BigBuf_malloc(MAX_FRAME_SIZE));
1081
1082 // Print some debug information about the buffer sizes
1083 Dbprintf("Snooping buffers initialized:");
1084 Dbprintf(" Trace: %i bytes", BigBuf_max_traceLen());
1085 Dbprintf(" Reader -> tag: %i bytes", MAX_FRAME_SIZE);
1086 Dbprintf(" tag -> Reader: %i bytes", MAX_FRAME_SIZE);
1087 Dbprintf(" DMA: %i bytes", ISO14443B_DMA_BUFFER_SIZE);
1088
1089 // Signal field is off, no reader signal, no tag signal
1090 LEDsoff();
1091
1092 // And put the FPGA in the appropriate mode
1093 FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ | FPGA_HF_READER_RX_XCORR_SNOOP);
1094 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1095
1096 // Setup for the DMA.
1097 FpgaSetupSsc();
1098 upTo = dmaBuf;
1099 lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
1100 FpgaSetupSscDma((uint8_t*) dmaBuf, ISO14443B_DMA_BUFFER_SIZE);
1101 uint8_t parity[MAX_PARITY_SIZE];
1102
1103 bool TagIsActive = FALSE;
1104 bool ReaderIsActive = FALSE;
1105
1106 // And now we loop, receiving samples.
1107 for(;;) {
1108 int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) &
1109 (ISO14443B_DMA_BUFFER_SIZE-1);
1110 if(behindBy > maxBehindBy) {
1111 maxBehindBy = behindBy;
1112 }
1113
1114 if(behindBy < 2) continue;
1115
1116 ci = upTo[0];
1117 cq = upTo[1];
1118 upTo += 2;
1119 lastRxCounter -= 2;
1120 if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
1121 upTo = dmaBuf;
1122 lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
1123 AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
1124 AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
1125 WDT_HIT();
1126 if(behindBy > (9*ISO14443B_DMA_BUFFER_SIZE/10)) { // TODO: understand whether we can increase/decrease as we want or not?
1127 Dbprintf("blew circular buffer! behindBy=%d", behindBy);
1128 break;
1129 }
1130 if(!tracing) {
1131 DbpString("Reached trace limit");
1132 break;
1133 }
1134 if(BUTTON_PRESS()) {
1135 DbpString("cancelled");
1136 break;
1137 }
1138 }
1139
1140 samples += 2;
1141
1142 if (!TagIsActive) { // no need to try decoding reader data if the tag is sending
1143 if(Handle14443bUartBit(ci & 0x01)) {
1144 if(triggered && tracing) {
1145 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1146 }
1147 /* And ready to receive another command. */
1148 UartReset();
1149 /* And also reset the demod code, which might have been */
1150 /* false-triggered by the commands from the reader. */
1151 DemodReset();
1152 }
1153 if(Handle14443bUartBit(cq & 0x01)) {
1154 if(triggered && tracing) {
1155 LogTrace(Uart.output, Uart.byteCnt, samples, samples, parity, TRUE);
1156 }
1157 /* And ready to receive another command. */
1158 UartReset();
1159 /* And also reset the demod code, which might have been */
1160 /* false-triggered by the commands from the reader. */
1161 DemodReset();
1162 }
1163 ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
1164 }
1165
1166 if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
1167 if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
1168
1169 //Use samples as a time measurement
1170 if(tracing)
1171 {
1172 uint8_t parity[MAX_PARITY_SIZE];
1173 LogTrace(Demod.output, Demod.len, samples, samples, parity, FALSE);
1174 }
1175 triggered = TRUE;
1176
1177 // And ready to receive another response.
1178 DemodReset();
1179 }
1180 TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
1181 }
1182
1183 }
1184
1185 FpgaDisableSscDma();
1186 LEDsoff();
1187 AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
1188 DbpString("Snoop statistics:");
1189 Dbprintf(" Max behind by: %i", maxBehindBy);
1190 Dbprintf(" Uart State: %x", Uart.state);
1191 Dbprintf(" Uart ByteCnt: %i", Uart.byteCnt);
1192 Dbprintf(" Uart ByteCntMax: %i", Uart.byteCntMax);
1193 Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
1194 }
1195
1196
1197 /*
1198 * Send raw command to tag ISO14443B
1199 * @Input
1200 * datalen len of buffer data
1201 * recv bool when true wait for data from tag and send to client
1202 * powerfield bool leave the field on when true
1203 * data buffer with byte to send
1204 *
1205 * @Output
1206 * none
1207 *
1208 */
1209 void SendRawCommand14443B(uint32_t datalen, uint32_t recv, uint8_t powerfield, uint8_t data[])
1210 {
1211 FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
1212 BigBuf_free();
1213 SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
1214 FpgaSetupSsc();
1215
1216 set_tracing(TRUE);
1217
1218 CodeAndTransmit14443bAsReader(data, datalen);
1219
1220 if(recv) {
1221 GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
1222 uint16_t iLen = MIN(Demod.len, USB_CMD_DATA_SIZE);
1223 cmd_send(CMD_ACK, iLen, 0, 0, Demod.output, iLen);
1224 }
1225
1226 if(!powerfield) {
1227 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1228 LED_D_OFF();
1229 }
1230 }
1231
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