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[proxmark3-svn] / armsrc / lfops.c
1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18
19 typedef struct {
20 uint8_t * buffer;
21 uint32_t numbits;
22 uint8_t position;
23 } BitstreamOut;
24 /**
25 * @brief Pushes bit onto the stream
26 * @param stream
27 * @param bit
28 */
29 void pushBit( BitstreamOut* stream, bool bit)
30 {
31 int bytepos = stream->position >> 3; // divide by 8
32 int bitpos = stream->position & 7;
33 *(stream->buffer+bytepos) |= (bit & 1) << (7 - bitpos);
34 stream->position++;
35 stream->numbits++;
36 }
37 void DoAcquisition(int decimation, int quantization, int trigger_threshold, bool averaging)
38 {
39 //A decimation of 2 means we keep every 2nd sample
40 //A decimation of 3 means we keep 1 in 3 samples.
41 //A quantization of 1 means one bit is discarded from the sample (division by 2).
42 uint8_t *dest = (uint8_t *)BigBuf;
43 int bufsize = BIGBUF_SIZE;
44 memset(dest, 0, bufsize);
45 // You can't decimate 8 bits more than 7 times
46 if(quantization > 7) quantization = 7;
47 // Use a bit stream to handle the output
48 BitstreamOut data = { dest , 0, 0};
49 int sample_counter = 0;
50 uint8_t sample = 0;
51 //If we want to do averaging
52 uint32_t sample_sum =0 ;
53 uint32_t sample_total_numbers =0 ;
54 uint32_t sample_total_saved =0 ;
55
56 for(;;) {
57 WDT_HIT();
58 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
59 AT91C_BASE_SSC->SSC_THR = 0x43;
60 LED_D_ON();
61 }
62 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
63 sample = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
64 if (trigger_threshold != -1 && sample < trigger_threshold)
65 continue;
66 sample_total_numbers++;
67
68 LED_D_OFF();
69 trigger_threshold = -1;
70 sample_counter++;
71 sample_sum += sample;
72 //Check decimation
73 if(sample_counter < decimation) continue;
74 //Averaging
75 if(averaging) sample = sample_sum / decimation;
76
77 sample_counter = 0;
78 sample_sum =0;
79 sample_total_saved ++;
80 pushBit(&data, sample & 0x80);
81 if(quantization < 7) pushBit(&data, sample & 0x40);
82 if(quantization < 6) pushBit(&data, sample & 0x20);
83 if(quantization < 5) pushBit(&data, sample & 0x10);
84 if(quantization < 4) pushBit(&data, sample & 0x08);
85 if(quantization < 3) pushBit(&data, sample & 0x04);
86 if(quantization < 2) pushBit(&data, sample & 0x02);
87 if(quantization < 1) pushBit(&data, sample & 0x01);
88
89 if((data.numbits / 8) +1 >= bufsize) break;
90 }
91 }
92 Dbprintf("Done, saved %l out of %l seen samples.",sample_total_saved, sample_total_numbers);
93
94 }
95
96
97 /**
98 * Does the sample acquisition. If threshold is specified, the actual sampling
99 * is not commenced until the threshold has been reached.
100 * @param trigger_threshold - the threshold
101 * @param silent - is true, now outputs are made. If false, dbprints the status
102 */
103 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
104 {
105 uint8_t *dest = (uint8_t *)BigBuf;
106 int n = sizeof(BigBuf);
107 int i;
108
109 memset(dest, 0, n);
110 i = 0;
111 for(;;) {
112 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
113 AT91C_BASE_SSC->SSC_THR = 0x43;
114 LED_D_ON();
115 }
116 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
117 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
118 LED_D_OFF();
119 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
120 continue;
121 else
122 trigger_threshold = -1;
123 if (++i >= n) break;
124 }
125 }
126 if(!silent)
127 {
128 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
129 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
130
131 }
132 }
133 /**
134 * Perform sample aquisition.
135 */
136 void DoAcquisition125k(int trigger_threshold)
137 {
138 DoAcquisition125k_internal(trigger_threshold, false);
139 }
140
141 /**
142 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
143 * if not already loaded, sets divisor and starts up the antenna.
144 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
145 * 0 or 95 ==> 125 KHz
146 *
147 **/
148 void LFSetupFPGAForADC(int divisor, bool lf_field)
149 {
150 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
151 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
152 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
153 else if (divisor == 0)
154 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
155 else
156 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
157
158 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
159
160 // Connect the A/D to the peak-detected low-frequency path.
161 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
162 // Give it a bit of time for the resonant antenna to settle.
163 SpinDelay(50);
164 // Now set up the SSC to get the ADC samples that are now streaming at us.
165 FpgaSetupSsc();
166 }
167 /**
168 * Initializes the FPGA, and acquires the samples.
169 **/
170 void AcquireRawAdcSamples125k(int divisor)
171 {
172 LFSetupFPGAForADC(divisor, true);
173 // Now call the acquisition routine
174 DoAcquisition125k_internal(-1,false);
175 }
176 /**
177 * Initializes the FPGA for snoop-mode, and acquires the samples.
178 **/
179
180 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
181 {
182 LFSetupFPGAForADC(divisor, false);
183 DoAcquisition125k(trigger_threshold);
184 }
185
186 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
187 {
188
189 /* Make sure the tag is reset */
190 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
191 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
192 SpinDelay(2500);
193
194
195 int divisor_used = 95; // 125 KHz
196 // see if 'h' was specified
197
198 if (command[strlen((char *) command) - 1] == 'h')
199 divisor_used = 88; // 134.8 KHz
200
201
202 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
203 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
204 // Give it a bit of time for the resonant antenna to settle.
205 SpinDelay(50);
206
207 // And a little more time for the tag to fully power up
208 SpinDelay(2000);
209
210 // Now set up the SSC to get the ADC samples that are now streaming at us.
211 FpgaSetupSsc();
212
213 // now modulate the reader field
214 while(*command != '\0' && *command != ' ') {
215 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
216 LED_D_OFF();
217 SpinDelayUs(delay_off);
218 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
219
220 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
221 LED_D_ON();
222 if(*(command++) == '0')
223 SpinDelayUs(period_0);
224 else
225 SpinDelayUs(period_1);
226 }
227 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
228 LED_D_OFF();
229 SpinDelayUs(delay_off);
230 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
231
232 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
233
234 // now do the read
235 DoAcquisition125k(-1);
236 }
237
238 /* blank r/w tag data stream
239 ...0000000000000000 01111111
240 1010101010101010101010101010101010101010101010101010101010101010
241 0011010010100001
242 01111111
243 101010101010101[0]000...
244
245 [5555fe852c5555555555555555fe0000]
246 */
247 void ReadTItag(void)
248 {
249 // some hardcoded initial params
250 // when we read a TI tag we sample the zerocross line at 2Mhz
251 // TI tags modulate a 1 as 16 cycles of 123.2Khz
252 // TI tags modulate a 0 as 16 cycles of 134.2Khz
253 #define FSAMPLE 2000000
254 #define FREQLO 123200
255 #define FREQHI 134200
256
257 signed char *dest = (signed char *)BigBuf;
258 int n = sizeof(BigBuf);
259 // 128 bit shift register [shift3:shift2:shift1:shift0]
260 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
261
262 int i, cycles=0, samples=0;
263 // how many sample points fit in 16 cycles of each frequency
264 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
265 // when to tell if we're close enough to one freq or another
266 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
267
268 // TI tags charge at 134.2Khz
269 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
270 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
271
272 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
273 // connects to SSP_DIN and the SSP_DOUT logic level controls
274 // whether we're modulating the antenna (high)
275 // or listening to the antenna (low)
276 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
277
278 // get TI tag data into the buffer
279 AcquireTiType();
280
281 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
282
283 for (i=0; i<n-1; i++) {
284 // count cycles by looking for lo to hi zero crossings
285 if ( (dest[i]<0) && (dest[i+1]>0) ) {
286 cycles++;
287 // after 16 cycles, measure the frequency
288 if (cycles>15) {
289 cycles=0;
290 samples=i-samples; // number of samples in these 16 cycles
291
292 // TI bits are coming to us lsb first so shift them
293 // right through our 128 bit right shift register
294 shift0 = (shift0>>1) | (shift1 << 31);
295 shift1 = (shift1>>1) | (shift2 << 31);
296 shift2 = (shift2>>1) | (shift3 << 31);
297 shift3 >>= 1;
298
299 // check if the cycles fall close to the number
300 // expected for either the low or high frequency
301 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
302 // low frequency represents a 1
303 shift3 |= (1<<31);
304 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
305 // high frequency represents a 0
306 } else {
307 // probably detected a gay waveform or noise
308 // use this as gaydar or discard shift register and start again
309 shift3 = shift2 = shift1 = shift0 = 0;
310 }
311 samples = i;
312
313 // for each bit we receive, test if we've detected a valid tag
314
315 // if we see 17 zeroes followed by 6 ones, we might have a tag
316 // remember the bits are backwards
317 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
318 // if start and end bytes match, we have a tag so break out of the loop
319 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
320 cycles = 0xF0B; //use this as a flag (ugly but whatever)
321 break;
322 }
323 }
324 }
325 }
326 }
327
328 // if flag is set we have a tag
329 if (cycles!=0xF0B) {
330 DbpString("Info: No valid tag detected.");
331 } else {
332 // put 64 bit data into shift1 and shift0
333 shift0 = (shift0>>24) | (shift1 << 8);
334 shift1 = (shift1>>24) | (shift2 << 8);
335
336 // align 16 bit crc into lower half of shift2
337 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
338
339 // if r/w tag, check ident match
340 if (shift3 & (1<<15) ) {
341 DbpString("Info: TI tag is rewriteable");
342 // only 15 bits compare, last bit of ident is not valid
343 if (((shift3 >> 16) ^ shift0) & 0x7fff ) {
344 DbpString("Error: Ident mismatch!");
345 } else {
346 DbpString("Info: TI tag ident is valid");
347 }
348 } else {
349 DbpString("Info: TI tag is readonly");
350 }
351
352 // WARNING the order of the bytes in which we calc crc below needs checking
353 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
354 // bytes in reverse or something
355 // calculate CRC
356 uint32_t crc=0;
357
358 crc = update_crc16(crc, (shift0)&0xff);
359 crc = update_crc16(crc, (shift0>>8)&0xff);
360 crc = update_crc16(crc, (shift0>>16)&0xff);
361 crc = update_crc16(crc, (shift0>>24)&0xff);
362 crc = update_crc16(crc, (shift1)&0xff);
363 crc = update_crc16(crc, (shift1>>8)&0xff);
364 crc = update_crc16(crc, (shift1>>16)&0xff);
365 crc = update_crc16(crc, (shift1>>24)&0xff);
366
367 Dbprintf("Info: Tag data: %x%08x, crc=%x",
368 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
369 if (crc != (shift2&0xffff)) {
370 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
371 } else {
372 DbpString("Info: CRC is good");
373 }
374 }
375 }
376
377 void WriteTIbyte(uint8_t b)
378 {
379 int i = 0;
380
381 // modulate 8 bits out to the antenna
382 for (i=0; i<8; i++)
383 {
384 if (b&(1<<i)) {
385 // stop modulating antenna
386 LOW(GPIO_SSC_DOUT);
387 SpinDelayUs(1000);
388 // modulate antenna
389 HIGH(GPIO_SSC_DOUT);
390 SpinDelayUs(1000);
391 } else {
392 // stop modulating antenna
393 LOW(GPIO_SSC_DOUT);
394 SpinDelayUs(300);
395 // modulate antenna
396 HIGH(GPIO_SSC_DOUT);
397 SpinDelayUs(1700);
398 }
399 }
400 }
401
402 void AcquireTiType(void)
403 {
404 int i, j, n;
405 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
406 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
407 #define TIBUFLEN 1250
408
409 // clear buffer
410 memset(BigBuf,0,sizeof(BigBuf));
411
412 // Set up the synchronous serial port
413 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
414 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
415
416 // steal this pin from the SSP and use it to control the modulation
417 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
418 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
419
420 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
421 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
422
423 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
424 // 48/2 = 24 MHz clock must be divided by 12
425 AT91C_BASE_SSC->SSC_CMR = 12;
426
427 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
428 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
429 AT91C_BASE_SSC->SSC_TCMR = 0;
430 AT91C_BASE_SSC->SSC_TFMR = 0;
431
432 LED_D_ON();
433
434 // modulate antenna
435 HIGH(GPIO_SSC_DOUT);
436
437 // Charge TI tag for 50ms.
438 SpinDelay(50);
439
440 // stop modulating antenna and listen
441 LOW(GPIO_SSC_DOUT);
442
443 LED_D_OFF();
444
445 i = 0;
446 for(;;) {
447 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
448 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
449 i++; if(i >= TIBUFLEN) break;
450 }
451 WDT_HIT();
452 }
453
454 // return stolen pin to SSP
455 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
456 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
457
458 char *dest = (char *)BigBuf;
459 n = TIBUFLEN*32;
460 // unpack buffer
461 for (i=TIBUFLEN-1; i>=0; i--) {
462 for (j=0; j<32; j++) {
463 if(BigBuf[i] & (1 << j)) {
464 dest[--n] = 1;
465 } else {
466 dest[--n] = -1;
467 }
468 }
469 }
470 }
471
472 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
473 // if crc provided, it will be written with the data verbatim (even if bogus)
474 // if not provided a valid crc will be computed from the data and written.
475 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
476 {
477 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
478 if(crc == 0) {
479 crc = update_crc16(crc, (idlo)&0xff);
480 crc = update_crc16(crc, (idlo>>8)&0xff);
481 crc = update_crc16(crc, (idlo>>16)&0xff);
482 crc = update_crc16(crc, (idlo>>24)&0xff);
483 crc = update_crc16(crc, (idhi)&0xff);
484 crc = update_crc16(crc, (idhi>>8)&0xff);
485 crc = update_crc16(crc, (idhi>>16)&0xff);
486 crc = update_crc16(crc, (idhi>>24)&0xff);
487 }
488 Dbprintf("Writing to tag: %x%08x, crc=%x",
489 (unsigned int) idhi, (unsigned int) idlo, crc);
490
491 // TI tags charge at 134.2Khz
492 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
493 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
494 // connects to SSP_DIN and the SSP_DOUT logic level controls
495 // whether we're modulating the antenna (high)
496 // or listening to the antenna (low)
497 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
498 LED_A_ON();
499
500 // steal this pin from the SSP and use it to control the modulation
501 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
502 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
503
504 // writing algorithm:
505 // a high bit consists of a field off for 1ms and field on for 1ms
506 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
507 // initiate a charge time of 50ms (field on) then immediately start writing bits
508 // start by writing 0xBB (keyword) and 0xEB (password)
509 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
510 // finally end with 0x0300 (write frame)
511 // all data is sent lsb firts
512 // finish with 15ms programming time
513
514 // modulate antenna
515 HIGH(GPIO_SSC_DOUT);
516 SpinDelay(50); // charge time
517
518 WriteTIbyte(0xbb); // keyword
519 WriteTIbyte(0xeb); // password
520 WriteTIbyte( (idlo )&0xff );
521 WriteTIbyte( (idlo>>8 )&0xff );
522 WriteTIbyte( (idlo>>16)&0xff );
523 WriteTIbyte( (idlo>>24)&0xff );
524 WriteTIbyte( (idhi )&0xff );
525 WriteTIbyte( (idhi>>8 )&0xff );
526 WriteTIbyte( (idhi>>16)&0xff );
527 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
528 WriteTIbyte( (crc )&0xff ); // crc lo
529 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
530 WriteTIbyte(0x00); // write frame lo
531 WriteTIbyte(0x03); // write frame hi
532 HIGH(GPIO_SSC_DOUT);
533 SpinDelay(50); // programming time
534
535 LED_A_OFF();
536
537 // get TI tag data into the buffer
538 AcquireTiType();
539
540 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
541 DbpString("Now use tiread to check");
542 }
543
544 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
545 {
546 int i;
547 uint8_t *tab = (uint8_t *)BigBuf;
548
549 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
550 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
551
552 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
553
554 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
555 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
556
557 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
558 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
559
560 i = 0;
561 for(;;) {
562 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
563 if(BUTTON_PRESS()) {
564 DbpString("Stopped");
565 return;
566 }
567 WDT_HIT();
568 }
569
570 if (ledcontrol)
571 LED_D_ON();
572
573 if(tab[i])
574 OPEN_COIL();
575 else
576 SHORT_COIL();
577
578 if (ledcontrol)
579 LED_D_OFF();
580
581 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
582 if(BUTTON_PRESS()) {
583 DbpString("Stopped");
584 return;
585 }
586 WDT_HIT();
587 }
588
589 i++;
590 if(i == period) {
591 i = 0;
592 if (gap) {
593 SHORT_COIL();
594 SpinDelayUs(gap);
595 }
596 }
597 }
598 }
599
600 #define DEBUG_FRAME_CONTENTS 1
601 void SimulateTagLowFrequencyBidir(int divisor, int t0)
602 {
603 }
604
605 // compose fc/8 fc/10 waveform
606 static void fc(int c, int *n) {
607 uint8_t *dest = (uint8_t *)BigBuf;
608 int idx;
609
610 // for when we want an fc8 pattern every 4 logical bits
611 if(c==0) {
612 dest[((*n)++)]=1;
613 dest[((*n)++)]=1;
614 dest[((*n)++)]=0;
615 dest[((*n)++)]=0;
616 dest[((*n)++)]=0;
617 dest[((*n)++)]=0;
618 dest[((*n)++)]=0;
619 dest[((*n)++)]=0;
620 }
621 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
622 if(c==8) {
623 for (idx=0; idx<6; idx++) {
624 dest[((*n)++)]=1;
625 dest[((*n)++)]=1;
626 dest[((*n)++)]=0;
627 dest[((*n)++)]=0;
628 dest[((*n)++)]=0;
629 dest[((*n)++)]=0;
630 dest[((*n)++)]=0;
631 dest[((*n)++)]=0;
632 }
633 }
634
635 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
636 if(c==10) {
637 for (idx=0; idx<5; idx++) {
638 dest[((*n)++)]=1;
639 dest[((*n)++)]=1;
640 dest[((*n)++)]=1;
641 dest[((*n)++)]=0;
642 dest[((*n)++)]=0;
643 dest[((*n)++)]=0;
644 dest[((*n)++)]=0;
645 dest[((*n)++)]=0;
646 dest[((*n)++)]=0;
647 dest[((*n)++)]=0;
648 }
649 }
650 }
651
652 // prepare a waveform pattern in the buffer based on the ID given then
653 // simulate a HID tag until the button is pressed
654 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
655 {
656 int n=0, i=0;
657 /*
658 HID tag bitstream format
659 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
660 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
661 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
662 A fc8 is inserted before every 4 bits
663 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
664 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
665 */
666
667 if (hi>0xFFF) {
668 DbpString("Tags can only have 44 bits.");
669 return;
670 }
671 fc(0,&n);
672 // special start of frame marker containing invalid bit sequences
673 fc(8, &n); fc(8, &n); // invalid
674 fc(8, &n); fc(10, &n); // logical 0
675 fc(10, &n); fc(10, &n); // invalid
676 fc(8, &n); fc(10, &n); // logical 0
677
678 WDT_HIT();
679 // manchester encode bits 43 to 32
680 for (i=11; i>=0; i--) {
681 if ((i%4)==3) fc(0,&n);
682 if ((hi>>i)&1) {
683 fc(10, &n); fc(8, &n); // low-high transition
684 } else {
685 fc(8, &n); fc(10, &n); // high-low transition
686 }
687 }
688
689 WDT_HIT();
690 // manchester encode bits 31 to 0
691 for (i=31; i>=0; i--) {
692 if ((i%4)==3) fc(0,&n);
693 if ((lo>>i)&1) {
694 fc(10, &n); fc(8, &n); // low-high transition
695 } else {
696 fc(8, &n); fc(10, &n); // high-low transition
697 }
698 }
699
700 if (ledcontrol)
701 LED_A_ON();
702 SimulateTagLowFrequency(n, 0, ledcontrol);
703
704 if (ledcontrol)
705 LED_A_OFF();
706 }
707
708 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
709 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
710 {
711 uint8_t *dest = (uint8_t *)BigBuf;
712
713 size_t size=0; //, found=0;
714 uint32_t hi2=0, hi=0, lo=0;
715
716 // Configure to go in 125Khz listen mode
717 LFSetupFPGAForADC(95, true);
718
719 while(!BUTTON_PRESS()) {
720
721 WDT_HIT();
722 if (ledcontrol) LED_A_ON();
723
724 DoAcquisition125k_internal(-1,true);
725 // FSK demodulator
726 size = HIDdemodFSK(dest, sizeof(BigBuf), &hi2, &hi, &lo);
727
728 WDT_HIT();
729
730 if (size>0 && lo>0){
731 // final loop, go over previously decoded manchester data and decode into usable tag ID
732 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
733 if (hi2 != 0){ //extra large HID tags
734 Dbprintf("TAG ID: %x%08x%08x (%d)",
735 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
736 }else { //standard HID tags <38 bits
737 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
738 uint8_t bitlen = 0;
739 uint32_t fc = 0;
740 uint32_t cardnum = 0;
741 if (((hi>>5)&1) == 1){//if bit 38 is set then < 37 bit format is used
742 uint32_t lo2=0;
743 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
744 uint8_t idx3 = 1;
745 while(lo2 > 1){ //find last bit set to 1 (format len bit)
746 lo2=lo2 >> 1;
747 idx3++;
748 }
749 bitlen = idx3+19;
750 fc =0;
751 cardnum=0;
752 if(bitlen == 26){
753 cardnum = (lo>>1)&0xFFFF;
754 fc = (lo>>17)&0xFF;
755 }
756 if(bitlen == 37){
757 cardnum = (lo>>1)&0x7FFFF;
758 fc = ((hi&0xF)<<12)|(lo>>20);
759 }
760 if(bitlen == 34){
761 cardnum = (lo>>1)&0xFFFF;
762 fc= ((hi&1)<<15)|(lo>>17);
763 }
764 if(bitlen == 35){
765 cardnum = (lo>>1)&0xFFFFF;
766 fc = ((hi&1)<<11)|(lo>>21);
767 }
768 }
769 else { //if bit 38 is not set then 37 bit format is used
770 bitlen= 37;
771 fc =0;
772 cardnum=0;
773 if(bitlen==37){
774 cardnum = (lo>>1)&0x7FFFF;
775 fc = ((hi&0xF)<<12)|(lo>>20);
776 }
777 }
778 //Dbprintf("TAG ID: %x%08x (%d)",
779 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
780 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
781 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
782 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
783 }
784 if (findone){
785 if (ledcontrol) LED_A_OFF();
786 return;
787 }
788 // reset
789 hi2 = hi = lo = 0;
790 }
791 WDT_HIT();
792 }
793 DbpString("Stopped");
794 if (ledcontrol) LED_A_OFF();
795 }
796
797 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
798 {
799 uint8_t *dest = (uint8_t *)BigBuf;
800
801 size_t size=0;
802 int clk=0, invert=0, errCnt=0;
803 uint64_t lo=0;
804 // Configure to go in 125Khz listen mode
805 LFSetupFPGAForADC(95, true);
806
807 while(!BUTTON_PRESS()) {
808
809 WDT_HIT();
810 if (ledcontrol) LED_A_ON();
811
812 DoAcquisition125k_internal(-1,true);
813 size = sizeof(BigBuf);
814 //Dbprintf("DEBUG: Buffer got");
815 //askdemod and manchester decode
816 errCnt = askmandemod(dest, &size, &clk, &invert);
817 //Dbprintf("DEBUG: ASK Got");
818 WDT_HIT();
819
820 if (errCnt>=0){
821 lo = Em410xDecode(dest,size);
822 //Dbprintf("DEBUG: EM GOT");
823 if (lo>0){
824 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
825 (uint32_t)(lo>>32),
826 (uint32_t)lo,
827 (uint32_t)(lo&0xFFFF),
828 (uint32_t)((lo>>16LL) & 0xFF),
829 (uint32_t)(lo & 0xFFFFFF));
830 }
831 if (findone){
832 if (ledcontrol) LED_A_OFF();
833 return;
834 }
835 } else{
836 //Dbprintf("DEBUG: No Tag");
837 }
838 WDT_HIT();
839 lo = 0;
840 clk=0;
841 invert=0;
842 errCnt=0;
843 size=0;
844 }
845 DbpString("Stopped");
846 if (ledcontrol) LED_A_OFF();
847 }
848
849 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
850 {
851 uint8_t *dest = (uint8_t *)BigBuf;
852 int idx=0;
853 uint32_t code=0, code2=0;
854 uint8_t version=0;
855 uint8_t facilitycode=0;
856 uint16_t number=0;
857 // Configure to go in 125Khz listen mode
858 LFSetupFPGAForADC(95, true);
859
860 while(!BUTTON_PRESS()) {
861 WDT_HIT();
862 if (ledcontrol) LED_A_ON();
863 DoAcquisition125k_internal(-1,true);
864 //fskdemod and get start index
865 WDT_HIT();
866 idx = IOdemodFSK(dest,sizeof(BigBuf));
867 if (idx>0){
868 //valid tag found
869
870 //Index map
871 //0 10 20 30 40 50 60
872 //| | | | | | |
873 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
874 //-----------------------------------------------------------------------------
875 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
876 //
877 //XSF(version)facility:codeone+codetwo
878 //Handle the data
879 if(findone){ //only print binary if we are doing one
880 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
881 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
882 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
883 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
884 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
885 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
886 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
887 }
888 code = bytebits_to_byte(dest+idx,32);
889 code2 = bytebits_to_byte(dest+idx+32,32);
890 version = bytebits_to_byte(dest+idx+27,8); //14,4
891 facilitycode = bytebits_to_byte(dest+idx+18,8) ;
892 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
893
894 Dbprintf("XSF(%02d)%02x:%05d (%08x%08x)",version,facilitycode,number,code,code2);
895 // if we're only looking for one tag
896 if (findone){
897 if (ledcontrol) LED_A_OFF();
898 //LED_A_OFF();
899 return;
900 }
901 code=code2=0;
902 version=facilitycode=0;
903 number=0;
904 idx=0;
905 }
906 WDT_HIT();
907 }
908 DbpString("Stopped");
909 if (ledcontrol) LED_A_OFF();
910 }
911
912 /*------------------------------
913 * T5555/T5557/T5567 routines
914 *------------------------------
915 */
916
917 /* T55x7 configuration register definitions */
918 #define T55x7_POR_DELAY 0x00000001
919 #define T55x7_ST_TERMINATOR 0x00000008
920 #define T55x7_PWD 0x00000010
921 #define T55x7_MAXBLOCK_SHIFT 5
922 #define T55x7_AOR 0x00000200
923 #define T55x7_PSKCF_RF_2 0
924 #define T55x7_PSKCF_RF_4 0x00000400
925 #define T55x7_PSKCF_RF_8 0x00000800
926 #define T55x7_MODULATION_DIRECT 0
927 #define T55x7_MODULATION_PSK1 0x00001000
928 #define T55x7_MODULATION_PSK2 0x00002000
929 #define T55x7_MODULATION_PSK3 0x00003000
930 #define T55x7_MODULATION_FSK1 0x00004000
931 #define T55x7_MODULATION_FSK2 0x00005000
932 #define T55x7_MODULATION_FSK1a 0x00006000
933 #define T55x7_MODULATION_FSK2a 0x00007000
934 #define T55x7_MODULATION_MANCHESTER 0x00008000
935 #define T55x7_MODULATION_BIPHASE 0x00010000
936 #define T55x7_BITRATE_RF_8 0
937 #define T55x7_BITRATE_RF_16 0x00040000
938 #define T55x7_BITRATE_RF_32 0x00080000
939 #define T55x7_BITRATE_RF_40 0x000C0000
940 #define T55x7_BITRATE_RF_50 0x00100000
941 #define T55x7_BITRATE_RF_64 0x00140000
942 #define T55x7_BITRATE_RF_100 0x00180000
943 #define T55x7_BITRATE_RF_128 0x001C0000
944
945 /* T5555 (Q5) configuration register definitions */
946 #define T5555_ST_TERMINATOR 0x00000001
947 #define T5555_MAXBLOCK_SHIFT 0x00000001
948 #define T5555_MODULATION_MANCHESTER 0
949 #define T5555_MODULATION_PSK1 0x00000010
950 #define T5555_MODULATION_PSK2 0x00000020
951 #define T5555_MODULATION_PSK3 0x00000030
952 #define T5555_MODULATION_FSK1 0x00000040
953 #define T5555_MODULATION_FSK2 0x00000050
954 #define T5555_MODULATION_BIPHASE 0x00000060
955 #define T5555_MODULATION_DIRECT 0x00000070
956 #define T5555_INVERT_OUTPUT 0x00000080
957 #define T5555_PSK_RF_2 0
958 #define T5555_PSK_RF_4 0x00000100
959 #define T5555_PSK_RF_8 0x00000200
960 #define T5555_USE_PWD 0x00000400
961 #define T5555_USE_AOR 0x00000800
962 #define T5555_BITRATE_SHIFT 12
963 #define T5555_FAST_WRITE 0x00004000
964 #define T5555_PAGE_SELECT 0x00008000
965
966 /*
967 * Relevant times in microsecond
968 * To compensate antenna falling times shorten the write times
969 * and enlarge the gap ones.
970 */
971 #define START_GAP 250
972 #define WRITE_GAP 160
973 #define WRITE_0 144 // 192
974 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
975
976 // Write one bit to card
977 void T55xxWriteBit(int bit)
978 {
979 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
980 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
981 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
982 if (bit == 0)
983 SpinDelayUs(WRITE_0);
984 else
985 SpinDelayUs(WRITE_1);
986 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
987 SpinDelayUs(WRITE_GAP);
988 }
989
990 // Write one card block in page 0, no lock
991 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
992 {
993 //unsigned int i; //enio adjustment 12/10/14
994 uint32_t i;
995
996 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
997 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
998 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
999
1000 // Give it a bit of time for the resonant antenna to settle.
1001 // And for the tag to fully power up
1002 SpinDelay(150);
1003
1004 // Now start writting
1005 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1006 SpinDelayUs(START_GAP);
1007
1008 // Opcode
1009 T55xxWriteBit(1);
1010 T55xxWriteBit(0); //Page 0
1011 if (PwdMode == 1){
1012 // Pwd
1013 for (i = 0x80000000; i != 0; i >>= 1)
1014 T55xxWriteBit(Pwd & i);
1015 }
1016 // Lock bit
1017 T55xxWriteBit(0);
1018
1019 // Data
1020 for (i = 0x80000000; i != 0; i >>= 1)
1021 T55xxWriteBit(Data & i);
1022
1023 // Block
1024 for (i = 0x04; i != 0; i >>= 1)
1025 T55xxWriteBit(Block & i);
1026
1027 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
1028 // so wait a little more)
1029 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1030 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1031 SpinDelay(20);
1032 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1033 }
1034
1035 // Read one card block in page 0
1036 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
1037 {
1038 uint8_t *dest = (uint8_t *)BigBuf;
1039 //int m=0, i=0; //enio adjustment 12/10/14
1040 uint32_t m=0, i=0;
1041 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1042 m = sizeof(BigBuf);
1043 // Clear destination buffer before sending the command
1044 memset(dest, 128, m);
1045 // Connect the A/D to the peak-detected low-frequency path.
1046 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1047 // Now set up the SSC to get the ADC samples that are now streaming at us.
1048 FpgaSetupSsc();
1049
1050 LED_D_ON();
1051 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1052 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1053
1054 // Give it a bit of time for the resonant antenna to settle.
1055 // And for the tag to fully power up
1056 SpinDelay(150);
1057
1058 // Now start writting
1059 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1060 SpinDelayUs(START_GAP);
1061
1062 // Opcode
1063 T55xxWriteBit(1);
1064 T55xxWriteBit(0); //Page 0
1065 if (PwdMode == 1){
1066 // Pwd
1067 for (i = 0x80000000; i != 0; i >>= 1)
1068 T55xxWriteBit(Pwd & i);
1069 }
1070 // Lock bit
1071 T55xxWriteBit(0);
1072 // Block
1073 for (i = 0x04; i != 0; i >>= 1)
1074 T55xxWriteBit(Block & i);
1075
1076 // Turn field on to read the response
1077 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1078 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1079
1080 // Now do the acquisition
1081 i = 0;
1082 for(;;) {
1083 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1084 AT91C_BASE_SSC->SSC_THR = 0x43;
1085 }
1086 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1087 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1088 // we don't care about actual value, only if it's more or less than a
1089 // threshold essentially we capture zero crossings for later analysis
1090 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1091 i++;
1092 if (i >= m) break;
1093 }
1094 }
1095
1096 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1097 LED_D_OFF();
1098 DbpString("DONE!");
1099 }
1100
1101 // Read card traceability data (page 1)
1102 void T55xxReadTrace(void){
1103 uint8_t *dest = (uint8_t *)BigBuf;
1104 int m=0, i=0;
1105
1106 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1107 m = sizeof(BigBuf);
1108 // Clear destination buffer before sending the command
1109 memset(dest, 128, m);
1110 // Connect the A/D to the peak-detected low-frequency path.
1111 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1112 // Now set up the SSC to get the ADC samples that are now streaming at us.
1113 FpgaSetupSsc();
1114
1115 LED_D_ON();
1116 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1117 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1118
1119 // Give it a bit of time for the resonant antenna to settle.
1120 // And for the tag to fully power up
1121 SpinDelay(150);
1122
1123 // Now start writting
1124 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1125 SpinDelayUs(START_GAP);
1126
1127 // Opcode
1128 T55xxWriteBit(1);
1129 T55xxWriteBit(1); //Page 1
1130
1131 // Turn field on to read the response
1132 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1133 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1134
1135 // Now do the acquisition
1136 i = 0;
1137 for(;;) {
1138 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1139 AT91C_BASE_SSC->SSC_THR = 0x43;
1140 }
1141 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1142 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1143 i++;
1144 if (i >= m) break;
1145 }
1146 }
1147
1148 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1149 LED_D_OFF();
1150 DbpString("DONE!");
1151 }
1152
1153 /*-------------- Cloning routines -----------*/
1154 // Copy HID id to card and setup block 0 config
1155 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1156 {
1157 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1158 int last_block = 0;
1159
1160 if (longFMT){
1161 // Ensure no more than 84 bits supplied
1162 if (hi2>0xFFFFF) {
1163 DbpString("Tags can only have 84 bits.");
1164 return;
1165 }
1166 // Build the 6 data blocks for supplied 84bit ID
1167 last_block = 6;
1168 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1169 for (int i=0;i<4;i++) {
1170 if (hi2 & (1<<(19-i)))
1171 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1172 else
1173 data1 |= (1<<((3-i)*2)); // 0 -> 01
1174 }
1175
1176 data2 = 0;
1177 for (int i=0;i<16;i++) {
1178 if (hi2 & (1<<(15-i)))
1179 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1180 else
1181 data2 |= (1<<((15-i)*2)); // 0 -> 01
1182 }
1183
1184 data3 = 0;
1185 for (int i=0;i<16;i++) {
1186 if (hi & (1<<(31-i)))
1187 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1188 else
1189 data3 |= (1<<((15-i)*2)); // 0 -> 01
1190 }
1191
1192 data4 = 0;
1193 for (int i=0;i<16;i++) {
1194 if (hi & (1<<(15-i)))
1195 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1196 else
1197 data4 |= (1<<((15-i)*2)); // 0 -> 01
1198 }
1199
1200 data5 = 0;
1201 for (int i=0;i<16;i++) {
1202 if (lo & (1<<(31-i)))
1203 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1204 else
1205 data5 |= (1<<((15-i)*2)); // 0 -> 01
1206 }
1207
1208 data6 = 0;
1209 for (int i=0;i<16;i++) {
1210 if (lo & (1<<(15-i)))
1211 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1212 else
1213 data6 |= (1<<((15-i)*2)); // 0 -> 01
1214 }
1215 }
1216 else {
1217 // Ensure no more than 44 bits supplied
1218 if (hi>0xFFF) {
1219 DbpString("Tags can only have 44 bits.");
1220 return;
1221 }
1222
1223 // Build the 3 data blocks for supplied 44bit ID
1224 last_block = 3;
1225
1226 data1 = 0x1D000000; // load preamble
1227
1228 for (int i=0;i<12;i++) {
1229 if (hi & (1<<(11-i)))
1230 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1231 else
1232 data1 |= (1<<((11-i)*2)); // 0 -> 01
1233 }
1234
1235 data2 = 0;
1236 for (int i=0;i<16;i++) {
1237 if (lo & (1<<(31-i)))
1238 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1239 else
1240 data2 |= (1<<((15-i)*2)); // 0 -> 01
1241 }
1242
1243 data3 = 0;
1244 for (int i=0;i<16;i++) {
1245 if (lo & (1<<(15-i)))
1246 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1247 else
1248 data3 |= (1<<((15-i)*2)); // 0 -> 01
1249 }
1250 }
1251
1252 LED_D_ON();
1253 // Program the data blocks for supplied ID
1254 // and the block 0 for HID format
1255 T55xxWriteBlock(data1,1,0,0);
1256 T55xxWriteBlock(data2,2,0,0);
1257 T55xxWriteBlock(data3,3,0,0);
1258
1259 if (longFMT) { // if long format there are 6 blocks
1260 T55xxWriteBlock(data4,4,0,0);
1261 T55xxWriteBlock(data5,5,0,0);
1262 T55xxWriteBlock(data6,6,0,0);
1263 }
1264
1265 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1266 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1267 T55x7_MODULATION_FSK2a |
1268 last_block << T55x7_MAXBLOCK_SHIFT,
1269 0,0,0);
1270
1271 LED_D_OFF();
1272
1273 DbpString("DONE!");
1274 }
1275
1276 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1277 {
1278 int data1=0, data2=0; //up to six blocks for long format
1279
1280 data1 = hi; // load preamble
1281 data2 = lo;
1282
1283 LED_D_ON();
1284 // Program the data blocks for supplied ID
1285 // and the block 0 for HID format
1286 T55xxWriteBlock(data1,1,0,0);
1287 T55xxWriteBlock(data2,2,0,0);
1288
1289 //Config Block
1290 T55xxWriteBlock(0x00147040,0,0,0);
1291 LED_D_OFF();
1292
1293 DbpString("DONE!");
1294 }
1295
1296 // Define 9bit header for EM410x tags
1297 #define EM410X_HEADER 0x1FF
1298 #define EM410X_ID_LENGTH 40
1299
1300 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1301 {
1302 int i, id_bit;
1303 uint64_t id = EM410X_HEADER;
1304 uint64_t rev_id = 0; // reversed ID
1305 int c_parity[4]; // column parity
1306 int r_parity = 0; // row parity
1307 uint32_t clock = 0;
1308
1309 // Reverse ID bits given as parameter (for simpler operations)
1310 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1311 if (i < 32) {
1312 rev_id = (rev_id << 1) | (id_lo & 1);
1313 id_lo >>= 1;
1314 } else {
1315 rev_id = (rev_id << 1) | (id_hi & 1);
1316 id_hi >>= 1;
1317 }
1318 }
1319
1320 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1321 id_bit = rev_id & 1;
1322
1323 if (i % 4 == 0) {
1324 // Don't write row parity bit at start of parsing
1325 if (i)
1326 id = (id << 1) | r_parity;
1327 // Start counting parity for new row
1328 r_parity = id_bit;
1329 } else {
1330 // Count row parity
1331 r_parity ^= id_bit;
1332 }
1333
1334 // First elements in column?
1335 if (i < 4)
1336 // Fill out first elements
1337 c_parity[i] = id_bit;
1338 else
1339 // Count column parity
1340 c_parity[i % 4] ^= id_bit;
1341
1342 // Insert ID bit
1343 id = (id << 1) | id_bit;
1344 rev_id >>= 1;
1345 }
1346
1347 // Insert parity bit of last row
1348 id = (id << 1) | r_parity;
1349
1350 // Fill out column parity at the end of tag
1351 for (i = 0; i < 4; ++i)
1352 id = (id << 1) | c_parity[i];
1353
1354 // Add stop bit
1355 id <<= 1;
1356
1357 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1358 LED_D_ON();
1359
1360 // Write EM410x ID
1361 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1362 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1363
1364 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1365 if (card) {
1366 // Clock rate is stored in bits 8-15 of the card value
1367 clock = (card & 0xFF00) >> 8;
1368 Dbprintf("Clock rate: %d", clock);
1369 switch (clock)
1370 {
1371 case 32:
1372 clock = T55x7_BITRATE_RF_32;
1373 break;
1374 case 16:
1375 clock = T55x7_BITRATE_RF_16;
1376 break;
1377 case 0:
1378 // A value of 0 is assumed to be 64 for backwards-compatibility
1379 // Fall through...
1380 case 64:
1381 clock = T55x7_BITRATE_RF_64;
1382 break;
1383 default:
1384 Dbprintf("Invalid clock rate: %d", clock);
1385 return;
1386 }
1387
1388 // Writing configuration for T55x7 tag
1389 T55xxWriteBlock(clock |
1390 T55x7_MODULATION_MANCHESTER |
1391 2 << T55x7_MAXBLOCK_SHIFT,
1392 0, 0, 0);
1393 }
1394 else
1395 // Writing configuration for T5555(Q5) tag
1396 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1397 T5555_MODULATION_MANCHESTER |
1398 2 << T5555_MAXBLOCK_SHIFT,
1399 0, 0, 0);
1400
1401 LED_D_OFF();
1402 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1403 (uint32_t)(id >> 32), (uint32_t)id);
1404 }
1405
1406 // Clone Indala 64-bit tag by UID to T55x7
1407 void CopyIndala64toT55x7(int hi, int lo)
1408 {
1409
1410 //Program the 2 data blocks for supplied 64bit UID
1411 // and the block 0 for Indala64 format
1412 T55xxWriteBlock(hi,1,0,0);
1413 T55xxWriteBlock(lo,2,0,0);
1414 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1415 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1416 T55x7_MODULATION_PSK1 |
1417 2 << T55x7_MAXBLOCK_SHIFT,
1418 0, 0, 0);
1419 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1420 // T5567WriteBlock(0x603E1042,0);
1421
1422 DbpString("DONE!");
1423
1424 }
1425
1426 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1427 {
1428
1429 //Program the 7 data blocks for supplied 224bit UID
1430 // and the block 0 for Indala224 format
1431 T55xxWriteBlock(uid1,1,0,0);
1432 T55xxWriteBlock(uid2,2,0,0);
1433 T55xxWriteBlock(uid3,3,0,0);
1434 T55xxWriteBlock(uid4,4,0,0);
1435 T55xxWriteBlock(uid5,5,0,0);
1436 T55xxWriteBlock(uid6,6,0,0);
1437 T55xxWriteBlock(uid7,7,0,0);
1438 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1439 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1440 T55x7_MODULATION_PSK1 |
1441 7 << T55x7_MAXBLOCK_SHIFT,
1442 0,0,0);
1443 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1444 // T5567WriteBlock(0x603E10E2,0);
1445
1446 DbpString("DONE!");
1447
1448 }
1449
1450
1451 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1452 #define max(x,y) ( x<y ? y:x)
1453
1454 int DemodPCF7931(uint8_t **outBlocks) {
1455 uint8_t BitStream[256];
1456 uint8_t Blocks[8][16];
1457 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1458 int GraphTraceLen = sizeof(BigBuf);
1459 int i, j, lastval, bitidx, half_switch;
1460 int clock = 64;
1461 int tolerance = clock / 8;
1462 int pmc, block_done;
1463 int lc, warnings = 0;
1464 int num_blocks = 0;
1465 int lmin=128, lmax=128;
1466 uint8_t dir;
1467
1468 AcquireRawAdcSamples125k(0);
1469
1470 lmin = 64;
1471 lmax = 192;
1472
1473 i = 2;
1474
1475 /* Find first local max/min */
1476 if(GraphBuffer[1] > GraphBuffer[0]) {
1477 while(i < GraphTraceLen) {
1478 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1479 break;
1480 i++;
1481 }
1482 dir = 0;
1483 }
1484 else {
1485 while(i < GraphTraceLen) {
1486 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1487 break;
1488 i++;
1489 }
1490 dir = 1;
1491 }
1492
1493 lastval = i++;
1494 half_switch = 0;
1495 pmc = 0;
1496 block_done = 0;
1497
1498 for (bitidx = 0; i < GraphTraceLen; i++)
1499 {
1500 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1501 {
1502 lc = i - lastval;
1503 lastval = i;
1504
1505 // Switch depending on lc length:
1506 // Tolerance is 1/8 of clock rate (arbitrary)
1507 if (abs(lc-clock/4) < tolerance) {
1508 // 16T0
1509 if((i - pmc) == lc) { /* 16T0 was previous one */
1510 /* It's a PMC ! */
1511 i += (128+127+16+32+33+16)-1;
1512 lastval = i;
1513 pmc = 0;
1514 block_done = 1;
1515 }
1516 else {
1517 pmc = i;
1518 }
1519 } else if (abs(lc-clock/2) < tolerance) {
1520 // 32TO
1521 if((i - pmc) == lc) { /* 16T0 was previous one */
1522 /* It's a PMC ! */
1523 i += (128+127+16+32+33)-1;
1524 lastval = i;
1525 pmc = 0;
1526 block_done = 1;
1527 }
1528 else if(half_switch == 1) {
1529 BitStream[bitidx++] = 0;
1530 half_switch = 0;
1531 }
1532 else
1533 half_switch++;
1534 } else if (abs(lc-clock) < tolerance) {
1535 // 64TO
1536 BitStream[bitidx++] = 1;
1537 } else {
1538 // Error
1539 warnings++;
1540 if (warnings > 10)
1541 {
1542 Dbprintf("Error: too many detection errors, aborting.");
1543 return 0;
1544 }
1545 }
1546
1547 if(block_done == 1) {
1548 if(bitidx == 128) {
1549 for(j=0; j<16; j++) {
1550 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1551 64*BitStream[j*8+6]+
1552 32*BitStream[j*8+5]+
1553 16*BitStream[j*8+4]+
1554 8*BitStream[j*8+3]+
1555 4*BitStream[j*8+2]+
1556 2*BitStream[j*8+1]+
1557 BitStream[j*8];
1558 }
1559 num_blocks++;
1560 }
1561 bitidx = 0;
1562 block_done = 0;
1563 half_switch = 0;
1564 }
1565 if(i < GraphTraceLen)
1566 {
1567 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1568 else dir = 1;
1569 }
1570 }
1571 if(bitidx==255)
1572 bitidx=0;
1573 warnings = 0;
1574 if(num_blocks == 4) break;
1575 }
1576 memcpy(outBlocks, Blocks, 16*num_blocks);
1577 return num_blocks;
1578 }
1579
1580 int IsBlock0PCF7931(uint8_t *Block) {
1581 // Assume RFU means 0 :)
1582 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1583 return 1;
1584 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1585 return 1;
1586 return 0;
1587 }
1588
1589 int IsBlock1PCF7931(uint8_t *Block) {
1590 // Assume RFU means 0 :)
1591 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1592 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1593 return 1;
1594
1595 return 0;
1596 }
1597
1598 #define ALLOC 16
1599
1600 void ReadPCF7931() {
1601 uint8_t Blocks[8][17];
1602 uint8_t tmpBlocks[4][16];
1603 int i, j, ind, ind2, n;
1604 int num_blocks = 0;
1605 int max_blocks = 8;
1606 int ident = 0;
1607 int error = 0;
1608 int tries = 0;
1609
1610 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1611
1612 do {
1613 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1614 n = DemodPCF7931((uint8_t**)tmpBlocks);
1615 if(!n)
1616 error++;
1617 if(error==10 && num_blocks == 0) {
1618 Dbprintf("Error, no tag or bad tag");
1619 return;
1620 }
1621 else if (tries==20 || error==10) {
1622 Dbprintf("Error reading the tag");
1623 Dbprintf("Here is the partial content");
1624 goto end;
1625 }
1626
1627 for(i=0; i<n; i++)
1628 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1629 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1630 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1631 if(!ident) {
1632 for(i=0; i<n; i++) {
1633 if(IsBlock0PCF7931(tmpBlocks[i])) {
1634 // Found block 0 ?
1635 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1636 // Found block 1!
1637 // \o/
1638 ident = 1;
1639 memcpy(Blocks[0], tmpBlocks[i], 16);
1640 Blocks[0][ALLOC] = 1;
1641 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1642 Blocks[1][ALLOC] = 1;
1643 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1644 // Debug print
1645 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1646 num_blocks = 2;
1647 // Handle following blocks
1648 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1649 if(j==n) j=0;
1650 if(j==i) break;
1651 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1652 Blocks[ind2][ALLOC] = 1;
1653 }
1654 break;
1655 }
1656 }
1657 }
1658 }
1659 else {
1660 for(i=0; i<n; i++) { // Look for identical block in known blocks
1661 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1662 for(j=0; j<max_blocks; j++) {
1663 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1664 // Found an identical block
1665 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1666 if(ind2 < 0)
1667 ind2 = max_blocks;
1668 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1669 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1670 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1671 Blocks[ind2][ALLOC] = 1;
1672 num_blocks++;
1673 if(num_blocks == max_blocks) goto end;
1674 }
1675 }
1676 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1677 if(ind2 > max_blocks)
1678 ind2 = 0;
1679 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1680 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1681 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1682 Blocks[ind2][ALLOC] = 1;
1683 num_blocks++;
1684 if(num_blocks == max_blocks) goto end;
1685 }
1686 }
1687 }
1688 }
1689 }
1690 }
1691 }
1692 tries++;
1693 if (BUTTON_PRESS()) return;
1694 } while (num_blocks != max_blocks);
1695 end:
1696 Dbprintf("-----------------------------------------");
1697 Dbprintf("Memory content:");
1698 Dbprintf("-----------------------------------------");
1699 for(i=0; i<max_blocks; i++) {
1700 if(Blocks[i][ALLOC]==1)
1701 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1702 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1703 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1704 else
1705 Dbprintf("<missing block %d>", i);
1706 }
1707 Dbprintf("-----------------------------------------");
1708
1709 return ;
1710 }
1711
1712
1713 //-----------------------------------
1714 // EM4469 / EM4305 routines
1715 //-----------------------------------
1716 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1717 #define FWD_CMD_WRITE 0xA
1718 #define FWD_CMD_READ 0x9
1719 #define FWD_CMD_DISABLE 0x5
1720
1721
1722 uint8_t forwardLink_data[64]; //array of forwarded bits
1723 uint8_t * forward_ptr; //ptr for forward message preparation
1724 uint8_t fwd_bit_sz; //forwardlink bit counter
1725 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1726
1727 //====================================================================
1728 // prepares command bits
1729 // see EM4469 spec
1730 //====================================================================
1731 //--------------------------------------------------------------------
1732 uint8_t Prepare_Cmd( uint8_t cmd ) {
1733 //--------------------------------------------------------------------
1734
1735 *forward_ptr++ = 0; //start bit
1736 *forward_ptr++ = 0; //second pause for 4050 code
1737
1738 *forward_ptr++ = cmd;
1739 cmd >>= 1;
1740 *forward_ptr++ = cmd;
1741 cmd >>= 1;
1742 *forward_ptr++ = cmd;
1743 cmd >>= 1;
1744 *forward_ptr++ = cmd;
1745
1746 return 6; //return number of emited bits
1747 }
1748
1749 //====================================================================
1750 // prepares address bits
1751 // see EM4469 spec
1752 //====================================================================
1753
1754 //--------------------------------------------------------------------
1755 uint8_t Prepare_Addr( uint8_t addr ) {
1756 //--------------------------------------------------------------------
1757
1758 register uint8_t line_parity;
1759
1760 uint8_t i;
1761 line_parity = 0;
1762 for(i=0;i<6;i++) {
1763 *forward_ptr++ = addr;
1764 line_parity ^= addr;
1765 addr >>= 1;
1766 }
1767
1768 *forward_ptr++ = (line_parity & 1);
1769
1770 return 7; //return number of emited bits
1771 }
1772
1773 //====================================================================
1774 // prepares data bits intreleaved with parity bits
1775 // see EM4469 spec
1776 //====================================================================
1777
1778 //--------------------------------------------------------------------
1779 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1780 //--------------------------------------------------------------------
1781
1782 register uint8_t line_parity;
1783 register uint8_t column_parity;
1784 register uint8_t i, j;
1785 register uint16_t data;
1786
1787 data = data_low;
1788 column_parity = 0;
1789
1790 for(i=0; i<4; i++) {
1791 line_parity = 0;
1792 for(j=0; j<8; j++) {
1793 line_parity ^= data;
1794 column_parity ^= (data & 1) << j;
1795 *forward_ptr++ = data;
1796 data >>= 1;
1797 }
1798 *forward_ptr++ = line_parity;
1799 if(i == 1)
1800 data = data_hi;
1801 }
1802
1803 for(j=0; j<8; j++) {
1804 *forward_ptr++ = column_parity;
1805 column_parity >>= 1;
1806 }
1807 *forward_ptr = 0;
1808
1809 return 45; //return number of emited bits
1810 }
1811
1812 //====================================================================
1813 // Forward Link send function
1814 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1815 // fwd_bit_count set with number of bits to be sent
1816 //====================================================================
1817 void SendForward(uint8_t fwd_bit_count) {
1818
1819 fwd_write_ptr = forwardLink_data;
1820 fwd_bit_sz = fwd_bit_count;
1821
1822 LED_D_ON();
1823
1824 //Field on
1825 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1826 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1827 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1828
1829 // Give it a bit of time for the resonant antenna to settle.
1830 // And for the tag to fully power up
1831 SpinDelay(150);
1832
1833 // force 1st mod pulse (start gap must be longer for 4305)
1834 fwd_bit_sz--; //prepare next bit modulation
1835 fwd_write_ptr++;
1836 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1837 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1838 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1839 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1840 SpinDelayUs(16*8); //16 cycles on (8us each)
1841
1842 // now start writting
1843 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1844 if(((*fwd_write_ptr++) & 1) == 1)
1845 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1846 else {
1847 //These timings work for 4469/4269/4305 (with the 55*8 above)
1848 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1849 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1850 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1851 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1852 SpinDelayUs(9*8); //16 cycles on (8us each)
1853 }
1854 }
1855 }
1856
1857 void EM4xLogin(uint32_t Password) {
1858
1859 uint8_t fwd_bit_count;
1860
1861 forward_ptr = forwardLink_data;
1862 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1863 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1864
1865 SendForward(fwd_bit_count);
1866
1867 //Wait for command to complete
1868 SpinDelay(20);
1869
1870 }
1871
1872 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1873
1874 uint8_t fwd_bit_count;
1875 uint8_t *dest = (uint8_t *)BigBuf;
1876 int m=0, i=0;
1877
1878 //If password mode do login
1879 if (PwdMode == 1) EM4xLogin(Pwd);
1880
1881 forward_ptr = forwardLink_data;
1882 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1883 fwd_bit_count += Prepare_Addr( Address );
1884
1885 m = sizeof(BigBuf);
1886 // Clear destination buffer before sending the command
1887 memset(dest, 128, m);
1888 // Connect the A/D to the peak-detected low-frequency path.
1889 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1890 // Now set up the SSC to get the ADC samples that are now streaming at us.
1891 FpgaSetupSsc();
1892
1893 SendForward(fwd_bit_count);
1894
1895 // Now do the acquisition
1896 i = 0;
1897 for(;;) {
1898 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1899 AT91C_BASE_SSC->SSC_THR = 0x43;
1900 }
1901 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1902 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1903 i++;
1904 if (i >= m) break;
1905 }
1906 }
1907 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1908 LED_D_OFF();
1909 }
1910
1911 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1912
1913 uint8_t fwd_bit_count;
1914
1915 //If password mode do login
1916 if (PwdMode == 1) EM4xLogin(Pwd);
1917
1918 forward_ptr = forwardLink_data;
1919 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1920 fwd_bit_count += Prepare_Addr( Address );
1921 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1922
1923 SendForward(fwd_bit_count);
1924
1925 //Wait for write to complete
1926 SpinDelay(20);
1927 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1928 LED_D_OFF();
1929 }
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