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1 //-----------------------------------------------------------------------------
2 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
3 // at your option, any later version. See the LICENSE.txt file for the text of
4 // the license.
5 //-----------------------------------------------------------------------------
6 // Miscellaneous routines for low frequency tag operations.
7 // Tags supported here so far are Texas Instruments (TI), HID
8 // Also routines for raw mode reading/simulating of LF waveform
9 //-----------------------------------------------------------------------------
10
11 #include "proxmark3.h"
12 #include "apps.h"
13 #include "util.h"
14 #include "hitag2.h"
15 #include "crc16.h"
16 #include "string.h"
17 #include "lfdemod.h"
18
19
20 /**
21 * Does the sample acquisition. If threshold is specified, the actual sampling
22 * is not commenced until the threshold has been reached.
23 * @param trigger_threshold - the threshold
24 * @param silent - is true, now outputs are made. If false, dbprints the status
25 */
26 void DoAcquisition125k_internal(int trigger_threshold,bool silent)
27 {
28 uint8_t *dest = (uint8_t *)BigBuf;
29 int n = sizeof(BigBuf);
30 int i;
31
32 memset(dest, 0, n);
33 i = 0;
34 for(;;) {
35 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
36 AT91C_BASE_SSC->SSC_THR = 0x43;
37 LED_D_ON();
38 }
39 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
40 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
41 LED_D_OFF();
42 if (trigger_threshold != -1 && dest[i] < trigger_threshold)
43 continue;
44 else
45 trigger_threshold = -1;
46 if (++i >= n) break;
47 }
48 }
49 if(!silent)
50 {
51 Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
52 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
53
54 }
55 }
56 /**
57 * Perform sample aquisition.
58 */
59 void DoAcquisition125k(int trigger_threshold)
60 {
61 DoAcquisition125k_internal(trigger_threshold, false);
62 }
63
64 /**
65 * Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
66 * if not already loaded, sets divisor and starts up the antenna.
67 * @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
68 * 0 or 95 ==> 125 KHz
69 *
70 **/
71 void LFSetupFPGAForADC(int divisor, bool lf_field)
72 {
73 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
74 if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
75 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
76 else if (divisor == 0)
77 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
78 else
79 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
80
81 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
82
83 // Connect the A/D to the peak-detected low-frequency path.
84 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
85 // Give it a bit of time for the resonant antenna to settle.
86 SpinDelay(50);
87 // Now set up the SSC to get the ADC samples that are now streaming at us.
88 FpgaSetupSsc();
89 }
90 /**
91 * Initializes the FPGA, and acquires the samples.
92 **/
93 void AcquireRawAdcSamples125k(int divisor)
94 {
95 LFSetupFPGAForADC(divisor, true);
96 // Now call the acquisition routine
97 DoAcquisition125k_internal(-1,false);
98 }
99 /**
100 * Initializes the FPGA for snoop-mode, and acquires the samples.
101 **/
102
103 void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
104 {
105 LFSetupFPGAForADC(divisor, false);
106 DoAcquisition125k(trigger_threshold);
107 }
108
109 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
110 {
111
112 /* Make sure the tag is reset */
113 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
114 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
115 SpinDelay(2500);
116
117
118 int divisor_used = 95; // 125 KHz
119 // see if 'h' was specified
120
121 if (command[strlen((char *) command) - 1] == 'h')
122 divisor_used = 88; // 134.8 KHz
123
124
125 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
126 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
127 // Give it a bit of time for the resonant antenna to settle.
128 SpinDelay(50);
129
130 // And a little more time for the tag to fully power up
131 SpinDelay(2000);
132
133 // Now set up the SSC to get the ADC samples that are now streaming at us.
134 FpgaSetupSsc();
135
136 // now modulate the reader field
137 while(*command != '\0' && *command != ' ') {
138 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
139 LED_D_OFF();
140 SpinDelayUs(delay_off);
141 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
142
143 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
144 LED_D_ON();
145 if(*(command++) == '0')
146 SpinDelayUs(period_0);
147 else
148 SpinDelayUs(period_1);
149 }
150 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
151 LED_D_OFF();
152 SpinDelayUs(delay_off);
153 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
154
155 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
156
157 // now do the read
158 DoAcquisition125k(-1);
159 }
160
161 /* blank r/w tag data stream
162 ...0000000000000000 01111111
163 1010101010101010101010101010101010101010101010101010101010101010
164 0011010010100001
165 01111111
166 101010101010101[0]000...
167
168 [5555fe852c5555555555555555fe0000]
169 */
170 void ReadTItag(void)
171 {
172 // some hardcoded initial params
173 // when we read a TI tag we sample the zerocross line at 2Mhz
174 // TI tags modulate a 1 as 16 cycles of 123.2Khz
175 // TI tags modulate a 0 as 16 cycles of 134.2Khz
176 #define FSAMPLE 2000000
177 #define FREQLO 123200
178 #define FREQHI 134200
179
180 signed char *dest = (signed char *)BigBuf;
181 int n = sizeof(BigBuf);
182 // int *dest = GraphBuffer;
183 // int n = GraphTraceLen;
184
185 // 128 bit shift register [shift3:shift2:shift1:shift0]
186 uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
187
188 int i, cycles=0, samples=0;
189 // how many sample points fit in 16 cycles of each frequency
190 uint32_t sampleslo = (FSAMPLE<<4)/FREQLO, sampleshi = (FSAMPLE<<4)/FREQHI;
191 // when to tell if we're close enough to one freq or another
192 uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
193
194 // TI tags charge at 134.2Khz
195 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
196 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
197
198 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
199 // connects to SSP_DIN and the SSP_DOUT logic level controls
200 // whether we're modulating the antenna (high)
201 // or listening to the antenna (low)
202 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
203
204 // get TI tag data into the buffer
205 AcquireTiType();
206
207 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
208
209 for (i=0; i<n-1; i++) {
210 // count cycles by looking for lo to hi zero crossings
211 if ( (dest[i]<0) && (dest[i+1]>0) ) {
212 cycles++;
213 // after 16 cycles, measure the frequency
214 if (cycles>15) {
215 cycles=0;
216 samples=i-samples; // number of samples in these 16 cycles
217
218 // TI bits are coming to us lsb first so shift them
219 // right through our 128 bit right shift register
220 shift0 = (shift0>>1) | (shift1 << 31);
221 shift1 = (shift1>>1) | (shift2 << 31);
222 shift2 = (shift2>>1) | (shift3 << 31);
223 shift3 >>= 1;
224
225 // check if the cycles fall close to the number
226 // expected for either the low or high frequency
227 if ( (samples>(sampleslo-threshold)) && (samples<(sampleslo+threshold)) ) {
228 // low frequency represents a 1
229 shift3 |= (1<<31);
230 } else if ( (samples>(sampleshi-threshold)) && (samples<(sampleshi+threshold)) ) {
231 // high frequency represents a 0
232 } else {
233 // probably detected a gay waveform or noise
234 // use this as gaydar or discard shift register and start again
235 shift3 = shift2 = shift1 = shift0 = 0;
236 }
237 samples = i;
238
239 // for each bit we receive, test if we've detected a valid tag
240
241 // if we see 17 zeroes followed by 6 ones, we might have a tag
242 // remember the bits are backwards
243 if ( ((shift0 & 0x7fffff) == 0x7e0000) ) {
244 // if start and end bytes match, we have a tag so break out of the loop
245 if ( ((shift0>>16)&0xff) == ((shift3>>8)&0xff) ) {
246 cycles = 0xF0B; //use this as a flag (ugly but whatever)
247 break;
248 }
249 }
250 }
251 }
252 }
253
254 // if flag is set we have a tag
255 if (cycles!=0xF0B) {
256 DbpString("Info: No valid tag detected.");
257 } else {
258 // put 64 bit data into shift1 and shift0
259 shift0 = (shift0>>24) | (shift1 << 8);
260 shift1 = (shift1>>24) | (shift2 << 8);
261
262 // align 16 bit crc into lower half of shift2
263 shift2 = ((shift2>>24) | (shift3 << 8)) & 0x0ffff;
264
265 // if r/w tag, check ident match
266 if ( shift3&(1<<15) ) {
267 DbpString("Info: TI tag is rewriteable");
268 // only 15 bits compare, last bit of ident is not valid
269 if ( ((shift3>>16)^shift0)&0x7fff ) {
270 DbpString("Error: Ident mismatch!");
271 } else {
272 DbpString("Info: TI tag ident is valid");
273 }
274 } else {
275 DbpString("Info: TI tag is readonly");
276 }
277
278 // WARNING the order of the bytes in which we calc crc below needs checking
279 // i'm 99% sure the crc algorithm is correct, but it may need to eat the
280 // bytes in reverse or something
281 // calculate CRC
282 uint32_t crc=0;
283
284 crc = update_crc16(crc, (shift0)&0xff);
285 crc = update_crc16(crc, (shift0>>8)&0xff);
286 crc = update_crc16(crc, (shift0>>16)&0xff);
287 crc = update_crc16(crc, (shift0>>24)&0xff);
288 crc = update_crc16(crc, (shift1)&0xff);
289 crc = update_crc16(crc, (shift1>>8)&0xff);
290 crc = update_crc16(crc, (shift1>>16)&0xff);
291 crc = update_crc16(crc, (shift1>>24)&0xff);
292
293 Dbprintf("Info: Tag data: %x%08x, crc=%x",
294 (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);
295 if (crc != (shift2&0xffff)) {
296 Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);
297 } else {
298 DbpString("Info: CRC is good");
299 }
300 }
301 }
302
303 void WriteTIbyte(uint8_t b)
304 {
305 int i = 0;
306
307 // modulate 8 bits out to the antenna
308 for (i=0; i<8; i++)
309 {
310 if (b&(1<<i)) {
311 // stop modulating antenna
312 LOW(GPIO_SSC_DOUT);
313 SpinDelayUs(1000);
314 // modulate antenna
315 HIGH(GPIO_SSC_DOUT);
316 SpinDelayUs(1000);
317 } else {
318 // stop modulating antenna
319 LOW(GPIO_SSC_DOUT);
320 SpinDelayUs(300);
321 // modulate antenna
322 HIGH(GPIO_SSC_DOUT);
323 SpinDelayUs(1700);
324 }
325 }
326 }
327
328 void AcquireTiType(void)
329 {
330 int i, j, n;
331 // tag transmission is <20ms, sampling at 2M gives us 40K samples max
332 // each sample is 1 bit stuffed into a uint32_t so we need 1250 uint32_t
333 #define TIBUFLEN 1250
334
335 // clear buffer
336 memset(BigBuf,0,sizeof(BigBuf));
337
338 // Set up the synchronous serial port
339 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
340 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;
341
342 // steal this pin from the SSP and use it to control the modulation
343 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
344 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
345
346 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;
347 AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;
348
349 // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long
350 // 48/2 = 24 MHz clock must be divided by 12
351 AT91C_BASE_SSC->SSC_CMR = 12;
352
353 AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);
354 AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;
355 AT91C_BASE_SSC->SSC_TCMR = 0;
356 AT91C_BASE_SSC->SSC_TFMR = 0;
357
358 LED_D_ON();
359
360 // modulate antenna
361 HIGH(GPIO_SSC_DOUT);
362
363 // Charge TI tag for 50ms.
364 SpinDelay(50);
365
366 // stop modulating antenna and listen
367 LOW(GPIO_SSC_DOUT);
368
369 LED_D_OFF();
370
371 i = 0;
372 for(;;) {
373 if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
374 BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer
375 i++; if(i >= TIBUFLEN) break;
376 }
377 WDT_HIT();
378 }
379
380 // return stolen pin to SSP
381 AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
382 AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
383
384 char *dest = (char *)BigBuf;
385 n = TIBUFLEN*32;
386 // unpack buffer
387 for (i=TIBUFLEN-1; i>=0; i--) {
388 for (j=0; j<32; j++) {
389 if(BigBuf[i] & (1 << j)) {
390 dest[--n] = 1;
391 } else {
392 dest[--n] = -1;
393 }
394 }
395 }
396 }
397
398 // arguments: 64bit data split into 32bit idhi:idlo and optional 16bit crc
399 // if crc provided, it will be written with the data verbatim (even if bogus)
400 // if not provided a valid crc will be computed from the data and written.
401 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
402 {
403 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
404 if(crc == 0) {
405 crc = update_crc16(crc, (idlo)&0xff);
406 crc = update_crc16(crc, (idlo>>8)&0xff);
407 crc = update_crc16(crc, (idlo>>16)&0xff);
408 crc = update_crc16(crc, (idlo>>24)&0xff);
409 crc = update_crc16(crc, (idhi)&0xff);
410 crc = update_crc16(crc, (idhi>>8)&0xff);
411 crc = update_crc16(crc, (idhi>>16)&0xff);
412 crc = update_crc16(crc, (idhi>>24)&0xff);
413 }
414 Dbprintf("Writing to tag: %x%08x, crc=%x",
415 (unsigned int) idhi, (unsigned int) idlo, crc);
416
417 // TI tags charge at 134.2Khz
418 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
419 // Place FPGA in passthrough mode, in this mode the CROSS_LO line
420 // connects to SSP_DIN and the SSP_DOUT logic level controls
421 // whether we're modulating the antenna (high)
422 // or listening to the antenna (low)
423 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
424 LED_A_ON();
425
426 // steal this pin from the SSP and use it to control the modulation
427 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
428 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
429
430 // writing algorithm:
431 // a high bit consists of a field off for 1ms and field on for 1ms
432 // a low bit consists of a field off for 0.3ms and field on for 1.7ms
433 // initiate a charge time of 50ms (field on) then immediately start writing bits
434 // start by writing 0xBB (keyword) and 0xEB (password)
435 // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
436 // finally end with 0x0300 (write frame)
437 // all data is sent lsb firts
438 // finish with 15ms programming time
439
440 // modulate antenna
441 HIGH(GPIO_SSC_DOUT);
442 SpinDelay(50); // charge time
443
444 WriteTIbyte(0xbb); // keyword
445 WriteTIbyte(0xeb); // password
446 WriteTIbyte( (idlo )&0xff );
447 WriteTIbyte( (idlo>>8 )&0xff );
448 WriteTIbyte( (idlo>>16)&0xff );
449 WriteTIbyte( (idlo>>24)&0xff );
450 WriteTIbyte( (idhi )&0xff );
451 WriteTIbyte( (idhi>>8 )&0xff );
452 WriteTIbyte( (idhi>>16)&0xff );
453 WriteTIbyte( (idhi>>24)&0xff ); // data hi to lo
454 WriteTIbyte( (crc )&0xff ); // crc lo
455 WriteTIbyte( (crc>>8 )&0xff ); // crc hi
456 WriteTIbyte(0x00); // write frame lo
457 WriteTIbyte(0x03); // write frame hi
458 HIGH(GPIO_SSC_DOUT);
459 SpinDelay(50); // programming time
460
461 LED_A_OFF();
462
463 // get TI tag data into the buffer
464 AcquireTiType();
465
466 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
467 DbpString("Now use tiread to check");
468 }
469
470 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
471 {
472 int i;
473 uint8_t *tab = (uint8_t *)BigBuf;
474
475 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
476 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
477
478 AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
479
480 AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
481 AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
482
483 #define SHORT_COIL() LOW(GPIO_SSC_DOUT)
484 #define OPEN_COIL() HIGH(GPIO_SSC_DOUT)
485
486 i = 0;
487 for(;;) {
488 while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
489 if(BUTTON_PRESS()) {
490 DbpString("Stopped");
491 return;
492 }
493 WDT_HIT();
494 }
495
496 if (ledcontrol)
497 LED_D_ON();
498
499 if(tab[i])
500 OPEN_COIL();
501 else
502 SHORT_COIL();
503
504 if (ledcontrol)
505 LED_D_OFF();
506
507 while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
508 if(BUTTON_PRESS()) {
509 DbpString("Stopped");
510 return;
511 }
512 WDT_HIT();
513 }
514
515 i++;
516 if(i == period) {
517 i = 0;
518 if (gap) {
519 SHORT_COIL();
520 SpinDelayUs(gap);
521 }
522 }
523 }
524 }
525
526 #define DEBUG_FRAME_CONTENTS 1
527 void SimulateTagLowFrequencyBidir(int divisor, int t0)
528 {
529 }
530
531 // compose fc/8 fc/10 waveform
532 static void fc(int c, int *n) {
533 uint8_t *dest = (uint8_t *)BigBuf;
534 int idx;
535
536 // for when we want an fc8 pattern every 4 logical bits
537 if(c==0) {
538 dest[((*n)++)]=1;
539 dest[((*n)++)]=1;
540 dest[((*n)++)]=0;
541 dest[((*n)++)]=0;
542 dest[((*n)++)]=0;
543 dest[((*n)++)]=0;
544 dest[((*n)++)]=0;
545 dest[((*n)++)]=0;
546 }
547 // an fc/8 encoded bit is a bit pattern of 11000000 x6 = 48 samples
548 if(c==8) {
549 for (idx=0; idx<6; idx++) {
550 dest[((*n)++)]=1;
551 dest[((*n)++)]=1;
552 dest[((*n)++)]=0;
553 dest[((*n)++)]=0;
554 dest[((*n)++)]=0;
555 dest[((*n)++)]=0;
556 dest[((*n)++)]=0;
557 dest[((*n)++)]=0;
558 }
559 }
560
561 // an fc/10 encoded bit is a bit pattern of 1110000000 x5 = 50 samples
562 if(c==10) {
563 for (idx=0; idx<5; idx++) {
564 dest[((*n)++)]=1;
565 dest[((*n)++)]=1;
566 dest[((*n)++)]=1;
567 dest[((*n)++)]=0;
568 dest[((*n)++)]=0;
569 dest[((*n)++)]=0;
570 dest[((*n)++)]=0;
571 dest[((*n)++)]=0;
572 dest[((*n)++)]=0;
573 dest[((*n)++)]=0;
574 }
575 }
576 }
577
578 // prepare a waveform pattern in the buffer based on the ID given then
579 // simulate a HID tag until the button is pressed
580 void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
581 {
582 int n=0, i=0;
583 /*
584 HID tag bitstream format
585 The tag contains a 44bit unique code. This is sent out MSB first in sets of 4 bits
586 A 1 bit is represented as 6 fc8 and 5 fc10 patterns
587 A 0 bit is represented as 5 fc10 and 6 fc8 patterns
588 A fc8 is inserted before every 4 bits
589 A special start of frame pattern is used consisting a0b0 where a and b are neither 0
590 nor 1 bits, they are special patterns (a = set of 12 fc8 and b = set of 10 fc10)
591 */
592
593 if (hi>0xFFF) {
594 DbpString("Tags can only have 44 bits.");
595 return;
596 }
597 fc(0,&n);
598 // special start of frame marker containing invalid bit sequences
599 fc(8, &n); fc(8, &n); // invalid
600 fc(8, &n); fc(10, &n); // logical 0
601 fc(10, &n); fc(10, &n); // invalid
602 fc(8, &n); fc(10, &n); // logical 0
603
604 WDT_HIT();
605 // manchester encode bits 43 to 32
606 for (i=11; i>=0; i--) {
607 if ((i%4)==3) fc(0,&n);
608 if ((hi>>i)&1) {
609 fc(10, &n); fc(8, &n); // low-high transition
610 } else {
611 fc(8, &n); fc(10, &n); // high-low transition
612 }
613 }
614
615 WDT_HIT();
616 // manchester encode bits 31 to 0
617 for (i=31; i>=0; i--) {
618 if ((i%4)==3) fc(0,&n);
619 if ((lo>>i)&1) {
620 fc(10, &n); fc(8, &n); // low-high transition
621 } else {
622 fc(8, &n); fc(10, &n); // high-low transition
623 }
624 }
625
626 if (ledcontrol)
627 LED_A_ON();
628 SimulateTagLowFrequency(n, 0, ledcontrol);
629
630 if (ledcontrol)
631 LED_A_OFF();
632 }
633
634 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
635 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
636 {
637 uint8_t *dest = (uint8_t *)BigBuf;
638
639 size_t size=0; //, found=0;
640 uint32_t hi2=0, hi=0, lo=0;
641
642 // Configure to go in 125Khz listen mode
643 LFSetupFPGAForADC(95, true);
644
645 while(!BUTTON_PRESS()) {
646
647 WDT_HIT();
648 if (ledcontrol) LED_A_ON();
649
650 DoAcquisition125k_internal(-1,true);
651 size = sizeof(BigBuf);
652 if (size < 2000) continue;
653 // FSK demodulator
654
655 int bitLen = HIDdemodFSK(dest,size,&hi2,&hi,&lo);
656
657 WDT_HIT();
658
659 if (bitLen>0 && lo>0){
660 // final loop, go over previously decoded manchester data and decode into usable tag ID
661 // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
662 if (hi2 != 0){ //extra large HID tags
663 Dbprintf("TAG ID: %x%08x%08x (%d)",
664 (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
665 }else { //standard HID tags <38 bits
666 //Dbprintf("TAG ID: %x%08x (%d)",(unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF); //old print cmd
667 uint8_t bitlen = 0;
668 uint32_t fc = 0;
669 uint32_t cardnum = 0;
670 if (((hi>>5)&1)==1){//if bit 38 is set then < 37 bit format is used
671 uint32_t lo2=0;
672 lo2=(((hi & 31) << 12) | (lo>>20)); //get bits 21-37 to check for format len bit
673 uint8_t idx3 = 1;
674 while(lo2>1){ //find last bit set to 1 (format len bit)
675 lo2=lo2>>1;
676 idx3++;
677 }
678 bitlen =idx3+19;
679 fc =0;
680 cardnum=0;
681 if(bitlen==26){
682 cardnum = (lo>>1)&0xFFFF;
683 fc = (lo>>17)&0xFF;
684 }
685 if(bitlen==37){
686 cardnum = (lo>>1)&0x7FFFF;
687 fc = ((hi&0xF)<<12)|(lo>>20);
688 }
689 if(bitlen==34){
690 cardnum = (lo>>1)&0xFFFF;
691 fc= ((hi&1)<<15)|(lo>>17);
692 }
693 if(bitlen==35){
694 cardnum = (lo>>1)&0xFFFFF;
695 fc = ((hi&1)<<11)|(lo>>21);
696 }
697 }
698 else { //if bit 38 is not set then 37 bit format is used
699 bitlen= 37;
700 fc =0;
701 cardnum=0;
702 if(bitlen==37){
703 cardnum = (lo>>1)&0x7FFFF;
704 fc = ((hi&0xF)<<12)|(lo>>20);
705 }
706 }
707 //Dbprintf("TAG ID: %x%08x (%d)",
708 // (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
709 Dbprintf("TAG ID: %x%08x (%d) - Format Len: %dbit - FC: %d - Card: %d",
710 (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF,
711 (unsigned int) bitlen, (unsigned int) fc, (unsigned int) cardnum);
712 }
713 if (findone){
714 if (ledcontrol) LED_A_OFF();
715 return;
716 }
717 // reset
718 hi2 = hi = lo = 0;
719 }
720 WDT_HIT();
721 //SpinDelay(50);
722 }
723 DbpString("Stopped");
724 if (ledcontrol) LED_A_OFF();
725 }
726
727 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
728 {
729 uint8_t *dest = (uint8_t *)BigBuf;
730
731 size_t size=0; //, found=0;
732 uint32_t bitLen=0;
733 int clk=0, invert=0, errCnt=0;
734 uint64_t lo=0;
735 // Configure to go in 125Khz listen mode
736 LFSetupFPGAForADC(95, true);
737
738 while(!BUTTON_PRESS()) {
739
740 WDT_HIT();
741 if (ledcontrol) LED_A_ON();
742
743 DoAcquisition125k_internal(-1,true);
744 size = sizeof(BigBuf);
745 if (size < 2000) continue;
746 // FSK demodulator
747 //int askmandemod(uint8_t *BinStream,uint32_t *BitLen,int *clk, int *invert);
748 bitLen=size;
749 //Dbprintf("DEBUG: Buffer got");
750 errCnt = askmandemod(dest,&bitLen,&clk,&invert); //HIDdemodFSK(dest,size,&hi2,&hi,&lo);
751 //Dbprintf("DEBUG: ASK Got");
752 WDT_HIT();
753
754 if (errCnt>=0){
755 lo = Em410xDecode(dest,bitLen);
756 //Dbprintf("DEBUG: EM GOT");
757 //printEM410x(lo);
758 if (lo>0){
759 Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",(uint32_t)(lo>>32),(uint32_t)lo,(uint32_t)(lo&0xFFFF),(uint32_t)((lo>>16LL) & 0xFF),(uint32_t)(lo & 0xFFFFFF));
760 }
761 if (findone){
762 if (ledcontrol) LED_A_OFF();
763 return;
764 }
765 } else{
766 //Dbprintf("DEBUG: No Tag");
767 }
768 WDT_HIT();
769 lo = 0;
770 clk=0;
771 invert=0;
772 errCnt=0;
773 size=0;
774 //SpinDelay(50);
775 }
776 DbpString("Stopped");
777 if (ledcontrol) LED_A_OFF();
778 }
779
780 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
781 {
782 uint8_t *dest = (uint8_t *)BigBuf;
783 size_t size=0;
784 int idx=0;
785 uint32_t code=0, code2=0;
786 uint8_t version=0;
787 uint8_t facilitycode=0;
788 uint16_t number=0;
789 // Configure to go in 125Khz listen mode
790 LFSetupFPGAForADC(95, true);
791
792 while(!BUTTON_PRESS()) {
793 WDT_HIT();
794 if (ledcontrol) LED_A_ON();
795 DoAcquisition125k_internal(-1,true);
796 size = sizeof(BigBuf);
797 //make sure buffer has data
798 if (size < 2000) continue;
799 //fskdemod and get start index
800 WDT_HIT();
801 idx = IOdemodFSK(dest,size);
802 if (idx>0){
803 //valid tag found
804
805 //Index map
806 //0 10 20 30 40 50 60
807 //| | | | | | |
808 //01234567 8 90123456 7 89012345 6 78901234 5 67890123 4 56789012 3 45678901 23
809 //-----------------------------------------------------------------------------
810 //00000000 0 11110000 1 facility 1 version* 1 code*one 1 code*two 1 ???????? 11
811 //
812 //XSF(version)facility:codeone+codetwo
813 //Handle the data
814 if(findone){ //only print binary if we are doing one
815 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx], dest[idx+1], dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
816 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
817 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
818 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
819 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
820 Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
821 Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
822 }
823 code = bytebits_to_byte(dest+idx,32);
824 code2 = bytebits_to_byte(dest+idx+32,32);
825 version = bytebits_to_byte(dest+idx+27,8); //14,4
826 facilitycode = bytebits_to_byte(dest+idx+19,8) ;
827 number = (bytebits_to_byte(dest+idx+36,8)<<8)|(bytebits_to_byte(dest+idx+45,8)); //36,9
828
829 Dbprintf("XSF(%02d)%02x:%d (%08x%08x)",version,facilitycode,number,code,code2);
830 // if we're only looking for one tag
831 if (findone){
832 if (ledcontrol) LED_A_OFF();
833 //LED_A_OFF();
834 return;
835 }
836 code=code2=0;
837 version=facilitycode=0;
838 number=0;
839 idx=0;
840 }
841 WDT_HIT();
842 }
843 DbpString("Stopped");
844 if (ledcontrol) LED_A_OFF();
845 }
846
847 /*------------------------------
848 * T5555/T5557/T5567 routines
849 *------------------------------
850 */
851
852 /* T55x7 configuration register definitions */
853 #define T55x7_POR_DELAY 0x00000001
854 #define T55x7_ST_TERMINATOR 0x00000008
855 #define T55x7_PWD 0x00000010
856 #define T55x7_MAXBLOCK_SHIFT 5
857 #define T55x7_AOR 0x00000200
858 #define T55x7_PSKCF_RF_2 0
859 #define T55x7_PSKCF_RF_4 0x00000400
860 #define T55x7_PSKCF_RF_8 0x00000800
861 #define T55x7_MODULATION_DIRECT 0
862 #define T55x7_MODULATION_PSK1 0x00001000
863 #define T55x7_MODULATION_PSK2 0x00002000
864 #define T55x7_MODULATION_PSK3 0x00003000
865 #define T55x7_MODULATION_FSK1 0x00004000
866 #define T55x7_MODULATION_FSK2 0x00005000
867 #define T55x7_MODULATION_FSK1a 0x00006000
868 #define T55x7_MODULATION_FSK2a 0x00007000
869 #define T55x7_MODULATION_MANCHESTER 0x00008000
870 #define T55x7_MODULATION_BIPHASE 0x00010000
871 #define T55x7_BITRATE_RF_8 0
872 #define T55x7_BITRATE_RF_16 0x00040000
873 #define T55x7_BITRATE_RF_32 0x00080000
874 #define T55x7_BITRATE_RF_40 0x000C0000
875 #define T55x7_BITRATE_RF_50 0x00100000
876 #define T55x7_BITRATE_RF_64 0x00140000
877 #define T55x7_BITRATE_RF_100 0x00180000
878 #define T55x7_BITRATE_RF_128 0x001C0000
879
880 /* T5555 (Q5) configuration register definitions */
881 #define T5555_ST_TERMINATOR 0x00000001
882 #define T5555_MAXBLOCK_SHIFT 0x00000001
883 #define T5555_MODULATION_MANCHESTER 0
884 #define T5555_MODULATION_PSK1 0x00000010
885 #define T5555_MODULATION_PSK2 0x00000020
886 #define T5555_MODULATION_PSK3 0x00000030
887 #define T5555_MODULATION_FSK1 0x00000040
888 #define T5555_MODULATION_FSK2 0x00000050
889 #define T5555_MODULATION_BIPHASE 0x00000060
890 #define T5555_MODULATION_DIRECT 0x00000070
891 #define T5555_INVERT_OUTPUT 0x00000080
892 #define T5555_PSK_RF_2 0
893 #define T5555_PSK_RF_4 0x00000100
894 #define T5555_PSK_RF_8 0x00000200
895 #define T5555_USE_PWD 0x00000400
896 #define T5555_USE_AOR 0x00000800
897 #define T5555_BITRATE_SHIFT 12
898 #define T5555_FAST_WRITE 0x00004000
899 #define T5555_PAGE_SELECT 0x00008000
900
901 /*
902 * Relevant times in microsecond
903 * To compensate antenna falling times shorten the write times
904 * and enlarge the gap ones.
905 */
906 #define START_GAP 250
907 #define WRITE_GAP 160
908 #define WRITE_0 144 // 192
909 #define WRITE_1 400 // 432 for T55x7; 448 for E5550
910
911 // Write one bit to card
912 void T55xxWriteBit(int bit)
913 {
914 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
915 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
916 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
917 if (bit == 0)
918 SpinDelayUs(WRITE_0);
919 else
920 SpinDelayUs(WRITE_1);
921 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
922 SpinDelayUs(WRITE_GAP);
923 }
924
925 // Write one card block in page 0, no lock
926 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
927 {
928 //unsigned int i; //enio adjustment 12/10/14
929 uint32_t i;
930
931 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
932 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
933 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
934
935 // Give it a bit of time for the resonant antenna to settle.
936 // And for the tag to fully power up
937 SpinDelay(150);
938
939 // Now start writting
940 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
941 SpinDelayUs(START_GAP);
942
943 // Opcode
944 T55xxWriteBit(1);
945 T55xxWriteBit(0); //Page 0
946 if (PwdMode == 1){
947 // Pwd
948 for (i = 0x80000000; i != 0; i >>= 1)
949 T55xxWriteBit(Pwd & i);
950 }
951 // Lock bit
952 T55xxWriteBit(0);
953
954 // Data
955 for (i = 0x80000000; i != 0; i >>= 1)
956 T55xxWriteBit(Data & i);
957
958 // Block
959 for (i = 0x04; i != 0; i >>= 1)
960 T55xxWriteBit(Block & i);
961
962 // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
963 // so wait a little more)
964 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
965 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
966 SpinDelay(20);
967 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
968 }
969
970 // Read one card block in page 0
971 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
972 {
973 uint8_t *dest = (uint8_t *)BigBuf;
974 //int m=0, i=0; //enio adjustment 12/10/14
975 uint32_t m=0, i=0;
976 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
977 m = sizeof(BigBuf);
978 // Clear destination buffer before sending the command
979 memset(dest, 128, m);
980 // Connect the A/D to the peak-detected low-frequency path.
981 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
982 // Now set up the SSC to get the ADC samples that are now streaming at us.
983 FpgaSetupSsc();
984
985 LED_D_ON();
986 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
987 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
988
989 // Give it a bit of time for the resonant antenna to settle.
990 // And for the tag to fully power up
991 SpinDelay(150);
992
993 // Now start writting
994 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
995 SpinDelayUs(START_GAP);
996
997 // Opcode
998 T55xxWriteBit(1);
999 T55xxWriteBit(0); //Page 0
1000 if (PwdMode == 1){
1001 // Pwd
1002 for (i = 0x80000000; i != 0; i >>= 1)
1003 T55xxWriteBit(Pwd & i);
1004 }
1005 // Lock bit
1006 T55xxWriteBit(0);
1007 // Block
1008 for (i = 0x04; i != 0; i >>= 1)
1009 T55xxWriteBit(Block & i);
1010
1011 // Turn field on to read the response
1012 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1013 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1014
1015 // Now do the acquisition
1016 i = 0;
1017 for(;;) {
1018 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1019 AT91C_BASE_SSC->SSC_THR = 0x43;
1020 }
1021 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1022 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1023 // we don't care about actual value, only if it's more or less than a
1024 // threshold essentially we capture zero crossings for later analysis
1025 // if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
1026 i++;
1027 if (i >= m) break;
1028 }
1029 }
1030
1031 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1032 LED_D_OFF();
1033 DbpString("DONE!");
1034 }
1035
1036 // Read card traceability data (page 1)
1037 void T55xxReadTrace(void){
1038 uint8_t *dest = (uint8_t *)BigBuf;
1039 int m=0, i=0;
1040
1041 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1042 m = sizeof(BigBuf);
1043 // Clear destination buffer before sending the command
1044 memset(dest, 128, m);
1045 // Connect the A/D to the peak-detected low-frequency path.
1046 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1047 // Now set up the SSC to get the ADC samples that are now streaming at us.
1048 FpgaSetupSsc();
1049
1050 LED_D_ON();
1051 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1052 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1053
1054 // Give it a bit of time for the resonant antenna to settle.
1055 // And for the tag to fully power up
1056 SpinDelay(150);
1057
1058 // Now start writting
1059 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
1060 SpinDelayUs(START_GAP);
1061
1062 // Opcode
1063 T55xxWriteBit(1);
1064 T55xxWriteBit(1); //Page 1
1065
1066 // Turn field on to read the response
1067 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1068 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1069
1070 // Now do the acquisition
1071 i = 0;
1072 for(;;) {
1073 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1074 AT91C_BASE_SSC->SSC_THR = 0x43;
1075 }
1076 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1077 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1078 i++;
1079 if (i >= m) break;
1080 }
1081 }
1082
1083 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1084 LED_D_OFF();
1085 DbpString("DONE!");
1086 }
1087
1088 /*-------------- Cloning routines -----------*/
1089 // Copy HID id to card and setup block 0 config
1090 void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT)
1091 {
1092 int data1=0, data2=0, data3=0, data4=0, data5=0, data6=0; //up to six blocks for long format
1093 int last_block = 0;
1094
1095 if (longFMT){
1096 // Ensure no more than 84 bits supplied
1097 if (hi2>0xFFFFF) {
1098 DbpString("Tags can only have 84 bits.");
1099 return;
1100 }
1101 // Build the 6 data blocks for supplied 84bit ID
1102 last_block = 6;
1103 data1 = 0x1D96A900; // load preamble (1D) & long format identifier (9E manchester encoded)
1104 for (int i=0;i<4;i++) {
1105 if (hi2 & (1<<(19-i)))
1106 data1 |= (1<<(((3-i)*2)+1)); // 1 -> 10
1107 else
1108 data1 |= (1<<((3-i)*2)); // 0 -> 01
1109 }
1110
1111 data2 = 0;
1112 for (int i=0;i<16;i++) {
1113 if (hi2 & (1<<(15-i)))
1114 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1115 else
1116 data2 |= (1<<((15-i)*2)); // 0 -> 01
1117 }
1118
1119 data3 = 0;
1120 for (int i=0;i<16;i++) {
1121 if (hi & (1<<(31-i)))
1122 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1123 else
1124 data3 |= (1<<((15-i)*2)); // 0 -> 01
1125 }
1126
1127 data4 = 0;
1128 for (int i=0;i<16;i++) {
1129 if (hi & (1<<(15-i)))
1130 data4 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1131 else
1132 data4 |= (1<<((15-i)*2)); // 0 -> 01
1133 }
1134
1135 data5 = 0;
1136 for (int i=0;i<16;i++) {
1137 if (lo & (1<<(31-i)))
1138 data5 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1139 else
1140 data5 |= (1<<((15-i)*2)); // 0 -> 01
1141 }
1142
1143 data6 = 0;
1144 for (int i=0;i<16;i++) {
1145 if (lo & (1<<(15-i)))
1146 data6 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1147 else
1148 data6 |= (1<<((15-i)*2)); // 0 -> 01
1149 }
1150 }
1151 else {
1152 // Ensure no more than 44 bits supplied
1153 if (hi>0xFFF) {
1154 DbpString("Tags can only have 44 bits.");
1155 return;
1156 }
1157
1158 // Build the 3 data blocks for supplied 44bit ID
1159 last_block = 3;
1160
1161 data1 = 0x1D000000; // load preamble
1162
1163 for (int i=0;i<12;i++) {
1164 if (hi & (1<<(11-i)))
1165 data1 |= (1<<(((11-i)*2)+1)); // 1 -> 10
1166 else
1167 data1 |= (1<<((11-i)*2)); // 0 -> 01
1168 }
1169
1170 data2 = 0;
1171 for (int i=0;i<16;i++) {
1172 if (lo & (1<<(31-i)))
1173 data2 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1174 else
1175 data2 |= (1<<((15-i)*2)); // 0 -> 01
1176 }
1177
1178 data3 = 0;
1179 for (int i=0;i<16;i++) {
1180 if (lo & (1<<(15-i)))
1181 data3 |= (1<<(((15-i)*2)+1)); // 1 -> 10
1182 else
1183 data3 |= (1<<((15-i)*2)); // 0 -> 01
1184 }
1185 }
1186
1187 LED_D_ON();
1188 // Program the data blocks for supplied ID
1189 // and the block 0 for HID format
1190 T55xxWriteBlock(data1,1,0,0);
1191 T55xxWriteBlock(data2,2,0,0);
1192 T55xxWriteBlock(data3,3,0,0);
1193
1194 if (longFMT) { // if long format there are 6 blocks
1195 T55xxWriteBlock(data4,4,0,0);
1196 T55xxWriteBlock(data5,5,0,0);
1197 T55xxWriteBlock(data6,6,0,0);
1198 }
1199
1200 // Config for HID (RF/50, FSK2a, Maxblock=3 for short/6 for long)
1201 T55xxWriteBlock(T55x7_BITRATE_RF_50 |
1202 T55x7_MODULATION_FSK2a |
1203 last_block << T55x7_MAXBLOCK_SHIFT,
1204 0,0,0);
1205
1206 LED_D_OFF();
1207
1208 DbpString("DONE!");
1209 }
1210
1211 void CopyIOtoT55x7(uint32_t hi, uint32_t lo, uint8_t longFMT)
1212 {
1213 int data1=0, data2=0; //up to six blocks for long format
1214
1215 data1 = hi; // load preamble
1216 data2 = lo;
1217
1218 LED_D_ON();
1219 // Program the data blocks for supplied ID
1220 // and the block 0 for HID format
1221 T55xxWriteBlock(data1,1,0,0);
1222 T55xxWriteBlock(data2,2,0,0);
1223
1224 //Config Block
1225 T55xxWriteBlock(0x00147040,0,0,0);
1226 LED_D_OFF();
1227
1228 DbpString("DONE!");
1229 }
1230
1231 // Define 9bit header for EM410x tags
1232 #define EM410X_HEADER 0x1FF
1233 #define EM410X_ID_LENGTH 40
1234
1235 void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo)
1236 {
1237 int i, id_bit;
1238 uint64_t id = EM410X_HEADER;
1239 uint64_t rev_id = 0; // reversed ID
1240 int c_parity[4]; // column parity
1241 int r_parity = 0; // row parity
1242 uint32_t clock = 0;
1243
1244 // Reverse ID bits given as parameter (for simpler operations)
1245 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1246 if (i < 32) {
1247 rev_id = (rev_id << 1) | (id_lo & 1);
1248 id_lo >>= 1;
1249 } else {
1250 rev_id = (rev_id << 1) | (id_hi & 1);
1251 id_hi >>= 1;
1252 }
1253 }
1254
1255 for (i = 0; i < EM410X_ID_LENGTH; ++i) {
1256 id_bit = rev_id & 1;
1257
1258 if (i % 4 == 0) {
1259 // Don't write row parity bit at start of parsing
1260 if (i)
1261 id = (id << 1) | r_parity;
1262 // Start counting parity for new row
1263 r_parity = id_bit;
1264 } else {
1265 // Count row parity
1266 r_parity ^= id_bit;
1267 }
1268
1269 // First elements in column?
1270 if (i < 4)
1271 // Fill out first elements
1272 c_parity[i] = id_bit;
1273 else
1274 // Count column parity
1275 c_parity[i % 4] ^= id_bit;
1276
1277 // Insert ID bit
1278 id = (id << 1) | id_bit;
1279 rev_id >>= 1;
1280 }
1281
1282 // Insert parity bit of last row
1283 id = (id << 1) | r_parity;
1284
1285 // Fill out column parity at the end of tag
1286 for (i = 0; i < 4; ++i)
1287 id = (id << 1) | c_parity[i];
1288
1289 // Add stop bit
1290 id <<= 1;
1291
1292 Dbprintf("Started writing %s tag ...", card ? "T55x7":"T5555");
1293 LED_D_ON();
1294
1295 // Write EM410x ID
1296 T55xxWriteBlock((uint32_t)(id >> 32), 1, 0, 0);
1297 T55xxWriteBlock((uint32_t)id, 2, 0, 0);
1298
1299 // Config for EM410x (RF/64, Manchester, Maxblock=2)
1300 if (card) {
1301 // Clock rate is stored in bits 8-15 of the card value
1302 clock = (card & 0xFF00) >> 8;
1303 Dbprintf("Clock rate: %d", clock);
1304 switch (clock)
1305 {
1306 case 32:
1307 clock = T55x7_BITRATE_RF_32;
1308 break;
1309 case 16:
1310 clock = T55x7_BITRATE_RF_16;
1311 break;
1312 case 0:
1313 // A value of 0 is assumed to be 64 for backwards-compatibility
1314 // Fall through...
1315 case 64:
1316 clock = T55x7_BITRATE_RF_64;
1317 break;
1318 default:
1319 Dbprintf("Invalid clock rate: %d", clock);
1320 return;
1321 }
1322
1323 // Writing configuration for T55x7 tag
1324 T55xxWriteBlock(clock |
1325 T55x7_MODULATION_MANCHESTER |
1326 2 << T55x7_MAXBLOCK_SHIFT,
1327 0, 0, 0);
1328 }
1329 else
1330 // Writing configuration for T5555(Q5) tag
1331 T55xxWriteBlock(0x1F << T5555_BITRATE_SHIFT |
1332 T5555_MODULATION_MANCHESTER |
1333 2 << T5555_MAXBLOCK_SHIFT,
1334 0, 0, 0);
1335
1336 LED_D_OFF();
1337 Dbprintf("Tag %s written with 0x%08x%08x\n", card ? "T55x7":"T5555",
1338 (uint32_t)(id >> 32), (uint32_t)id);
1339 }
1340
1341 // Clone Indala 64-bit tag by UID to T55x7
1342 void CopyIndala64toT55x7(int hi, int lo)
1343 {
1344
1345 //Program the 2 data blocks for supplied 64bit UID
1346 // and the block 0 for Indala64 format
1347 T55xxWriteBlock(hi,1,0,0);
1348 T55xxWriteBlock(lo,2,0,0);
1349 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=2)
1350 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1351 T55x7_MODULATION_PSK1 |
1352 2 << T55x7_MAXBLOCK_SHIFT,
1353 0, 0, 0);
1354 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
1355 // T5567WriteBlock(0x603E1042,0);
1356
1357 DbpString("DONE!");
1358
1359 }
1360
1361 void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int uid6, int uid7)
1362 {
1363
1364 //Program the 7 data blocks for supplied 224bit UID
1365 // and the block 0 for Indala224 format
1366 T55xxWriteBlock(uid1,1,0,0);
1367 T55xxWriteBlock(uid2,2,0,0);
1368 T55xxWriteBlock(uid3,3,0,0);
1369 T55xxWriteBlock(uid4,4,0,0);
1370 T55xxWriteBlock(uid5,5,0,0);
1371 T55xxWriteBlock(uid6,6,0,0);
1372 T55xxWriteBlock(uid7,7,0,0);
1373 //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
1374 T55xxWriteBlock(T55x7_BITRATE_RF_32 |
1375 T55x7_MODULATION_PSK1 |
1376 7 << T55x7_MAXBLOCK_SHIFT,
1377 0,0,0);
1378 //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
1379 // T5567WriteBlock(0x603E10E2,0);
1380
1381 DbpString("DONE!");
1382
1383 }
1384
1385
1386 #define abs(x) ( ((x)<0) ? -(x) : (x) )
1387 #define max(x,y) ( x<y ? y:x)
1388
1389 int DemodPCF7931(uint8_t **outBlocks) {
1390 uint8_t BitStream[256];
1391 uint8_t Blocks[8][16];
1392 uint8_t *GraphBuffer = (uint8_t *)BigBuf;
1393 int GraphTraceLen = sizeof(BigBuf);
1394 int i, j, lastval, bitidx, half_switch;
1395 int clock = 64;
1396 int tolerance = clock / 8;
1397 int pmc, block_done;
1398 int lc, warnings = 0;
1399 int num_blocks = 0;
1400 int lmin=128, lmax=128;
1401 uint8_t dir;
1402
1403 AcquireRawAdcSamples125k(0);
1404
1405 lmin = 64;
1406 lmax = 192;
1407
1408 i = 2;
1409
1410 /* Find first local max/min */
1411 if(GraphBuffer[1] > GraphBuffer[0]) {
1412 while(i < GraphTraceLen) {
1413 if( !(GraphBuffer[i] > GraphBuffer[i-1]) && GraphBuffer[i] > lmax)
1414 break;
1415 i++;
1416 }
1417 dir = 0;
1418 }
1419 else {
1420 while(i < GraphTraceLen) {
1421 if( !(GraphBuffer[i] < GraphBuffer[i-1]) && GraphBuffer[i] < lmin)
1422 break;
1423 i++;
1424 }
1425 dir = 1;
1426 }
1427
1428 lastval = i++;
1429 half_switch = 0;
1430 pmc = 0;
1431 block_done = 0;
1432
1433 for (bitidx = 0; i < GraphTraceLen; i++)
1434 {
1435 if ( (GraphBuffer[i-1] > GraphBuffer[i] && dir == 1 && GraphBuffer[i] > lmax) || (GraphBuffer[i-1] < GraphBuffer[i] && dir == 0 && GraphBuffer[i] < lmin))
1436 {
1437 lc = i - lastval;
1438 lastval = i;
1439
1440 // Switch depending on lc length:
1441 // Tolerance is 1/8 of clock rate (arbitrary)
1442 if (abs(lc-clock/4) < tolerance) {
1443 // 16T0
1444 if((i - pmc) == lc) { /* 16T0 was previous one */
1445 /* It's a PMC ! */
1446 i += (128+127+16+32+33+16)-1;
1447 lastval = i;
1448 pmc = 0;
1449 block_done = 1;
1450 }
1451 else {
1452 pmc = i;
1453 }
1454 } else if (abs(lc-clock/2) < tolerance) {
1455 // 32TO
1456 if((i - pmc) == lc) { /* 16T0 was previous one */
1457 /* It's a PMC ! */
1458 i += (128+127+16+32+33)-1;
1459 lastval = i;
1460 pmc = 0;
1461 block_done = 1;
1462 }
1463 else if(half_switch == 1) {
1464 BitStream[bitidx++] = 0;
1465 half_switch = 0;
1466 }
1467 else
1468 half_switch++;
1469 } else if (abs(lc-clock) < tolerance) {
1470 // 64TO
1471 BitStream[bitidx++] = 1;
1472 } else {
1473 // Error
1474 warnings++;
1475 if (warnings > 10)
1476 {
1477 Dbprintf("Error: too many detection errors, aborting.");
1478 return 0;
1479 }
1480 }
1481
1482 if(block_done == 1) {
1483 if(bitidx == 128) {
1484 for(j=0; j<16; j++) {
1485 Blocks[num_blocks][j] = 128*BitStream[j*8+7]+
1486 64*BitStream[j*8+6]+
1487 32*BitStream[j*8+5]+
1488 16*BitStream[j*8+4]+
1489 8*BitStream[j*8+3]+
1490 4*BitStream[j*8+2]+
1491 2*BitStream[j*8+1]+
1492 BitStream[j*8];
1493 }
1494 num_blocks++;
1495 }
1496 bitidx = 0;
1497 block_done = 0;
1498 half_switch = 0;
1499 }
1500 if(i < GraphTraceLen)
1501 {
1502 if (GraphBuffer[i-1] > GraphBuffer[i]) dir=0;
1503 else dir = 1;
1504 }
1505 }
1506 if(bitidx==255)
1507 bitidx=0;
1508 warnings = 0;
1509 if(num_blocks == 4) break;
1510 }
1511 memcpy(outBlocks, Blocks, 16*num_blocks);
1512 return num_blocks;
1513 }
1514
1515 int IsBlock0PCF7931(uint8_t *Block) {
1516 // Assume RFU means 0 :)
1517 if((memcmp(Block, "\x00\x00\x00\x00\x00\x00\x00\x01", 8) == 0) && memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) // PAC enabled
1518 return 1;
1519 if((memcmp(Block+9, "\x00\x00\x00\x00\x00\x00\x00", 7) == 0) && Block[7] == 0) // PAC disabled, can it *really* happen ?
1520 return 1;
1521 return 0;
1522 }
1523
1524 int IsBlock1PCF7931(uint8_t *Block) {
1525 // Assume RFU means 0 :)
1526 if(Block[10] == 0 && Block[11] == 0 && Block[12] == 0 && Block[13] == 0)
1527 if((Block[14] & 0x7f) <= 9 && Block[15] <= 9)
1528 return 1;
1529
1530 return 0;
1531 }
1532
1533 #define ALLOC 16
1534
1535 void ReadPCF7931() {
1536 uint8_t Blocks[8][17];
1537 uint8_t tmpBlocks[4][16];
1538 int i, j, ind, ind2, n;
1539 int num_blocks = 0;
1540 int max_blocks = 8;
1541 int ident = 0;
1542 int error = 0;
1543 int tries = 0;
1544
1545 memset(Blocks, 0, 8*17*sizeof(uint8_t));
1546
1547 do {
1548 memset(tmpBlocks, 0, 4*16*sizeof(uint8_t));
1549 n = DemodPCF7931((uint8_t**)tmpBlocks);
1550 if(!n)
1551 error++;
1552 if(error==10 && num_blocks == 0) {
1553 Dbprintf("Error, no tag or bad tag");
1554 return;
1555 }
1556 else if (tries==20 || error==10) {
1557 Dbprintf("Error reading the tag");
1558 Dbprintf("Here is the partial content");
1559 goto end;
1560 }
1561
1562 for(i=0; i<n; i++)
1563 Dbprintf("(dbg) %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1564 tmpBlocks[i][0], tmpBlocks[i][1], tmpBlocks[i][2], tmpBlocks[i][3], tmpBlocks[i][4], tmpBlocks[i][5], tmpBlocks[i][6], tmpBlocks[i][7],
1565 tmpBlocks[i][8], tmpBlocks[i][9], tmpBlocks[i][10], tmpBlocks[i][11], tmpBlocks[i][12], tmpBlocks[i][13], tmpBlocks[i][14], tmpBlocks[i][15]);
1566 if(!ident) {
1567 for(i=0; i<n; i++) {
1568 if(IsBlock0PCF7931(tmpBlocks[i])) {
1569 // Found block 0 ?
1570 if(i < n-1 && IsBlock1PCF7931(tmpBlocks[i+1])) {
1571 // Found block 1!
1572 // \o/
1573 ident = 1;
1574 memcpy(Blocks[0], tmpBlocks[i], 16);
1575 Blocks[0][ALLOC] = 1;
1576 memcpy(Blocks[1], tmpBlocks[i+1], 16);
1577 Blocks[1][ALLOC] = 1;
1578 max_blocks = max((Blocks[1][14] & 0x7f), Blocks[1][15]) + 1;
1579 // Debug print
1580 Dbprintf("(dbg) Max blocks: %d", max_blocks);
1581 num_blocks = 2;
1582 // Handle following blocks
1583 for(j=i+2, ind2=2; j!=i; j++, ind2++, num_blocks++) {
1584 if(j==n) j=0;
1585 if(j==i) break;
1586 memcpy(Blocks[ind2], tmpBlocks[j], 16);
1587 Blocks[ind2][ALLOC] = 1;
1588 }
1589 break;
1590 }
1591 }
1592 }
1593 }
1594 else {
1595 for(i=0; i<n; i++) { // Look for identical block in known blocks
1596 if(memcmp(tmpBlocks[i], "\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00", 16)) { // Block is not full of 00
1597 for(j=0; j<max_blocks; j++) {
1598 if(Blocks[j][ALLOC] == 1 && !memcmp(tmpBlocks[i], Blocks[j], 16)) {
1599 // Found an identical block
1600 for(ind=i-1,ind2=j-1; ind >= 0; ind--,ind2--) {
1601 if(ind2 < 0)
1602 ind2 = max_blocks;
1603 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1604 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1605 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1606 Blocks[ind2][ALLOC] = 1;
1607 num_blocks++;
1608 if(num_blocks == max_blocks) goto end;
1609 }
1610 }
1611 for(ind=i+1,ind2=j+1; ind < n; ind++,ind2++) {
1612 if(ind2 > max_blocks)
1613 ind2 = 0;
1614 if(!Blocks[ind2][ALLOC]) { // Block ind2 not already found
1615 // Dbprintf("Tmp %d -> Block %d", ind, ind2);
1616 memcpy(Blocks[ind2], tmpBlocks[ind], 16);
1617 Blocks[ind2][ALLOC] = 1;
1618 num_blocks++;
1619 if(num_blocks == max_blocks) goto end;
1620 }
1621 }
1622 }
1623 }
1624 }
1625 }
1626 }
1627 tries++;
1628 if (BUTTON_PRESS()) return;
1629 } while (num_blocks != max_blocks);
1630 end:
1631 Dbprintf("-----------------------------------------");
1632 Dbprintf("Memory content:");
1633 Dbprintf("-----------------------------------------");
1634 for(i=0; i<max_blocks; i++) {
1635 if(Blocks[i][ALLOC]==1)
1636 Dbprintf("%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
1637 Blocks[i][0], Blocks[i][1], Blocks[i][2], Blocks[i][3], Blocks[i][4], Blocks[i][5], Blocks[i][6], Blocks[i][7],
1638 Blocks[i][8], Blocks[i][9], Blocks[i][10], Blocks[i][11], Blocks[i][12], Blocks[i][13], Blocks[i][14], Blocks[i][15]);
1639 else
1640 Dbprintf("<missing block %d>", i);
1641 }
1642 Dbprintf("-----------------------------------------");
1643
1644 return ;
1645 }
1646
1647
1648 //-----------------------------------
1649 // EM4469 / EM4305 routines
1650 //-----------------------------------
1651 #define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
1652 #define FWD_CMD_WRITE 0xA
1653 #define FWD_CMD_READ 0x9
1654 #define FWD_CMD_DISABLE 0x5
1655
1656
1657 uint8_t forwardLink_data[64]; //array of forwarded bits
1658 uint8_t * forward_ptr; //ptr for forward message preparation
1659 uint8_t fwd_bit_sz; //forwardlink bit counter
1660 uint8_t * fwd_write_ptr; //forwardlink bit pointer
1661
1662 //====================================================================
1663 // prepares command bits
1664 // see EM4469 spec
1665 //====================================================================
1666 //--------------------------------------------------------------------
1667 uint8_t Prepare_Cmd( uint8_t cmd ) {
1668 //--------------------------------------------------------------------
1669
1670 *forward_ptr++ = 0; //start bit
1671 *forward_ptr++ = 0; //second pause for 4050 code
1672
1673 *forward_ptr++ = cmd;
1674 cmd >>= 1;
1675 *forward_ptr++ = cmd;
1676 cmd >>= 1;
1677 *forward_ptr++ = cmd;
1678 cmd >>= 1;
1679 *forward_ptr++ = cmd;
1680
1681 return 6; //return number of emited bits
1682 }
1683
1684 //====================================================================
1685 // prepares address bits
1686 // see EM4469 spec
1687 //====================================================================
1688
1689 //--------------------------------------------------------------------
1690 uint8_t Prepare_Addr( uint8_t addr ) {
1691 //--------------------------------------------------------------------
1692
1693 register uint8_t line_parity;
1694
1695 uint8_t i;
1696 line_parity = 0;
1697 for(i=0;i<6;i++) {
1698 *forward_ptr++ = addr;
1699 line_parity ^= addr;
1700 addr >>= 1;
1701 }
1702
1703 *forward_ptr++ = (line_parity & 1);
1704
1705 return 7; //return number of emited bits
1706 }
1707
1708 //====================================================================
1709 // prepares data bits intreleaved with parity bits
1710 // see EM4469 spec
1711 //====================================================================
1712
1713 //--------------------------------------------------------------------
1714 uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
1715 //--------------------------------------------------------------------
1716
1717 register uint8_t line_parity;
1718 register uint8_t column_parity;
1719 register uint8_t i, j;
1720 register uint16_t data;
1721
1722 data = data_low;
1723 column_parity = 0;
1724
1725 for(i=0; i<4; i++) {
1726 line_parity = 0;
1727 for(j=0; j<8; j++) {
1728 line_parity ^= data;
1729 column_parity ^= (data & 1) << j;
1730 *forward_ptr++ = data;
1731 data >>= 1;
1732 }
1733 *forward_ptr++ = line_parity;
1734 if(i == 1)
1735 data = data_hi;
1736 }
1737
1738 for(j=0; j<8; j++) {
1739 *forward_ptr++ = column_parity;
1740 column_parity >>= 1;
1741 }
1742 *forward_ptr = 0;
1743
1744 return 45; //return number of emited bits
1745 }
1746
1747 //====================================================================
1748 // Forward Link send function
1749 // Requires: forwarLink_data filled with valid bits (1 bit per byte)
1750 // fwd_bit_count set with number of bits to be sent
1751 //====================================================================
1752 void SendForward(uint8_t fwd_bit_count) {
1753
1754 fwd_write_ptr = forwardLink_data;
1755 fwd_bit_sz = fwd_bit_count;
1756
1757 LED_D_ON();
1758
1759 //Field on
1760 FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
1761 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1762 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
1763
1764 // Give it a bit of time for the resonant antenna to settle.
1765 // And for the tag to fully power up
1766 SpinDelay(150);
1767
1768 // force 1st mod pulse (start gap must be longer for 4305)
1769 fwd_bit_sz--; //prepare next bit modulation
1770 fwd_write_ptr++;
1771 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1772 SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
1773 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1774 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1775 SpinDelayUs(16*8); //16 cycles on (8us each)
1776
1777 // now start writting
1778 while(fwd_bit_sz-- > 0) { //prepare next bit modulation
1779 if(((*fwd_write_ptr++) & 1) == 1)
1780 SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)
1781 else {
1782 //These timings work for 4469/4269/4305 (with the 55*8 above)
1783 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1784 SpinDelayUs(23*8); //16-4 cycles off (8us each)
1785 FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
1786 FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
1787 SpinDelayUs(9*8); //16 cycles on (8us each)
1788 }
1789 }
1790 }
1791
1792 void EM4xLogin(uint32_t Password) {
1793
1794 uint8_t fwd_bit_count;
1795
1796 forward_ptr = forwardLink_data;
1797 fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
1798 fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
1799
1800 SendForward(fwd_bit_count);
1801
1802 //Wait for command to complete
1803 SpinDelay(20);
1804
1805 }
1806
1807 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1808
1809 uint8_t fwd_bit_count;
1810 uint8_t *dest = (uint8_t *)BigBuf;
1811 int m=0, i=0;
1812
1813 //If password mode do login
1814 if (PwdMode == 1) EM4xLogin(Pwd);
1815
1816 forward_ptr = forwardLink_data;
1817 fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
1818 fwd_bit_count += Prepare_Addr( Address );
1819
1820 m = sizeof(BigBuf);
1821 // Clear destination buffer before sending the command
1822 memset(dest, 128, m);
1823 // Connect the A/D to the peak-detected low-frequency path.
1824 SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
1825 // Now set up the SSC to get the ADC samples that are now streaming at us.
1826 FpgaSetupSsc();
1827
1828 SendForward(fwd_bit_count);
1829
1830 // Now do the acquisition
1831 i = 0;
1832 for(;;) {
1833 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
1834 AT91C_BASE_SSC->SSC_THR = 0x43;
1835 }
1836 if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
1837 dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
1838 i++;
1839 if (i >= m) break;
1840 }
1841 }
1842 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1843 LED_D_OFF();
1844 }
1845
1846 void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
1847
1848 uint8_t fwd_bit_count;
1849
1850 //If password mode do login
1851 if (PwdMode == 1) EM4xLogin(Pwd);
1852
1853 forward_ptr = forwardLink_data;
1854 fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
1855 fwd_bit_count += Prepare_Addr( Address );
1856 fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
1857
1858 SendForward(fwd_bit_count);
1859
1860 //Wait for write to complete
1861 SpinDelay(20);
1862 FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
1863 LED_D_OFF();
1864 }
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