Fixed several issues found using a coverity-scan

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 397ea8475e8af050eab2670bece8f59b1555c0ac..74f04913e6e66760e5a617860110e412dd900192 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -15,8 +15,14 @@
 #include "crc16.h"
 #include "string.h"
 
 #include "crc16.h"
 #include "string.h"
 

-// split into two routines so we can avoid timing issues after sending commands //
-void DoAcquisition125k_internal(bool silent)
+
+/**
+* Does the sample acquisition. If threshold is specified, the actual sampling 
+* is not commenced until the threshold has been reached. 
+* @param trigger_threshold - the threshold
+* @param silent - is true, now outputs are made. If false, dbprints the status
+*/
+void DoAcquisition125k_internal(int trigger_threshold,bool silent)

 {
        uint8_t *dest = (uint8_t *)BigBuf;
        int n = sizeof(BigBuf);
 {
        uint8_t *dest = (uint8_t *)BigBuf;
        int n = sizeof(BigBuf);


@@ -31,25 +37,39 @@ void DoAcquisition125k_internal(bool silent)
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
                }
                if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
                        dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-                       i++;

                        LED_D_OFF();
                        LED_D_OFF();

-                       if (i >= n) break;
+                       if (trigger_threshold != -1 && dest[i] < trigger_threshold)
+                               continue;
+                       else
+                               trigger_threshold = -1;
+                       if (++i >= n) break;

                }
        }
                }
        }

-       if( ! silent)
+       if(!silent)

        {
                Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
                                dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
        {
                Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
                                dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);

+               

        }
 }
        }
 }

-
-void DoAcquisition125k(void)
+/**
+* Perform sample aquisition. 
+*/
+void DoAcquisition125k(int trigger_threshold)

 {
 {

-       DoAcquisition125k_internal(false);
+       DoAcquisition125k_internal(trigger_threshold, false);

 }
 
 }
 

-void SetupToAcquireRawAdcSamples(int divisor)
+/**
+* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream 
+* if not already loaded, sets divisor and starts up the antenna. 
+* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
+*                                 0 or 95 ==> 125 KHz
+*                                 
+**/
+void LFSetupFPGAForADC(int divisor, bool lf_field)

 {
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
        else if (divisor == 0)
        if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
        else if (divisor == 0)


@@ -57,48 +77,55 @@ void SetupToAcquireRawAdcSamples(int divisor)
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 
        else
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));

 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);

-

        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);
        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);

-

        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
 }
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
 }

-
+/**
+* Initializes the FPGA, and acquires the samples. 
+**/

 void AcquireRawAdcSamples125k(int divisor)
 {
 void AcquireRawAdcSamples125k(int divisor)
 {

-       SetupToAcquireRawAdcSamples(divisor);
+       LFSetupFPGAForADC(divisor, true);

        // Now call the acquisition routine
        // Now call the acquisition routine

-       DoAcquisition125k_internal(false);
+       DoAcquisition125k_internal(-1,false);
+}
+/**
+* Initializes the FPGA for snoop-mode, and acquires the samples. 
+**/
+
+void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
+{
+       LFSetupFPGAForADC(divisor, false);
+       DoAcquisition125k(trigger_threshold);

 }
 
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {
 }
 
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {

-       int at134khz;

 
        /* Make sure the tag is reset */
 
        /* Make sure the tag is reset */

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        SpinDelay(2500);
 

+
+       int divisor_used = 95; // 125 KHz

        // see if 'h' was specified
        // see if 'h' was specified

-       if (command[strlen((char *) command) - 1] == 'h')
-               at134khz = TRUE;
-       else
-               at134khz = FALSE;

 
 

-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       if (command[strlen((char *) command) - 1] == 'h')
+               divisor_used = 88; // 134.8 KHz

 
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);

 
 

+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);
        // Give it a bit of time for the resonant antenna to settle.
        SpinDelay(50);

+

        // And a little more time for the tag to fully power up
        SpinDelay(2000);
 
        // And a little more time for the tag to fully power up
        SpinDelay(2000);
 


@@ -110,12 +137,9 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
                SpinDelayUs(delay_off);

-               if (at134khz)
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-               else
-                       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 

 
 

-               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+               FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);
                LED_D_ON();
                if(*(command++) == '0')
                        SpinDelayUs(period_0);


@@ -125,15 +149,12 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
        SpinDelayUs(delay_off);

-       if (at134khz)
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-       else
-               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used); 

 
 

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // now do the read
 
        // now do the read

-       DoAcquisition125k();
+       DoAcquisition125k(-1);

 }
 
 /* blank r/w tag data stream
 }
 
 /* blank r/w tag data stream


@@ -170,6 +191,7 @@ void ReadTItag(void)
        uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
        // TI tags charge at 134.2Khz
        uint32_t threshold = (sampleslo - sampleshi + 1)>>1;
 
        // TI tags charge at 134.2Khz

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
        // Place FPGA in passthrough mode, in this mode the CROSS_LO line
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
 
        // Place FPGA in passthrough mode, in this mode the CROSS_LO line


@@ -377,6 +399,7 @@ void AcquireTiType(void)
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {
 // if not provided a valid crc will be computed from the data and written.
 void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);   

        if(crc == 0) {
                crc = update_crc16(crc, (idlo)&0xff);
                crc = update_crc16(crc, (idlo>>8)&0xff);
        if(crc == 0) {
                crc = update_crc16(crc, (idlo)&0xff);
                crc = update_crc16(crc, (idlo>>8)&0xff);


@@ -448,6 +471,7 @@ void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
        int i;
        uint8_t *tab = (uint8_t *)BigBuf;
     
        int i;
        uint8_t *tab = (uint8_t *)BigBuf;
     

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
     
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
     
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;


@@ -615,7 +639,6 @@ size_t fsk_demod(uint8_t * dest, size_t size)
        // threshold essentially we capture zero crossings for later analysis
        uint8_t threshold_value = 127;
 
        // threshold essentially we capture zero crossings for later analysis
        uint8_t threshold_value = 127;
 

-

        // sync to first lo-hi transition, and threshold
 
        //Need to threshold first sample
        // sync to first lo-hi transition, and threshold
 
        //Need to threshold first sample


@@ -688,21 +711,19 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
        size_t size=0,idx=0; //, found=0;
        uint32_t hi2=0, hi=0, lo=0;
 
        size_t size=0,idx=0; //, found=0;
        uint32_t hi2=0, hi=0, lo=0;
 

+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(95, true);

 
        while(!BUTTON_PRESS()) {
 
 
        while(!BUTTON_PRESS()) {
 

-               // Configure to go in 125Khz listen mode
-               SetupToAcquireRawAdcSamples(0);
-

                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 

-               DoAcquisition125k_internal(true);
+               DoAcquisition125k_internal(-1,true);

                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);
                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);

-               WDT_HIT();

 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 6
 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 6


@@ -723,7 +744,8 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                                idx+=sizeof(frame_marker_mask);
 
                                while(dest[idx] != dest[idx+1] && idx < size-2)
                                idx+=sizeof(frame_marker_mask);
 
                                while(dest[idx] != dest[idx+1] && idx < size-2)

-                               {       // Keep going until next frame marker (or error)
+                               {       
+                                       // Keep going until next frame marker (or error)

                                        // Shift in a bit. Start by shifting high registers
                                        hi2 = (hi2<<1)|(hi>>31);
                                        hi = (hi<<1)|(lo>>31);
                                        // Shift in a bit. Start by shifting high registers
                                        hi2 = (hi2<<1)|(hi>>31);
                                        hi = (hi<<1)|(lo>>31);


@@ -738,16 +760,20 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                                }
                                //Dbprintf("Num shifts: %d ", numshifts);
                                // Hopefully, we read a tag and  hit upon the next frame marker
                                }
                                //Dbprintf("Num shifts: %d ", numshifts);
                                // Hopefully, we read a tag and  hit upon the next frame marker

-                               if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
+                               if(idx + sizeof(frame_marker_mask) < size)

                                {
                                {

-                                       if (hi2 != 0){
-                                               Dbprintf("TAG ID: %x%08x%08x (%d)",
-                                                        (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
-                                       }
-                                       else {
-                                               Dbprintf("TAG ID: %x%08x (%d)",
-                                                (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+                                       if ( memcmp(dest+idx, frame_marker_mask, sizeof(frame_marker_mask)) == 0)
+                                       {
+                                               if (hi2 != 0){
+                                                       Dbprintf("TAG ID: %x%08x%08x (%d)",
+                                                                (unsigned int) hi2, (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+                                               }
+                                               else {
+                                                       Dbprintf("TAG ID: %x%08x (%d)",
+                                                        (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);
+                                               }

                                        }
                                        }

+

                                }
 
                                // reset
                                }
 
                                // reset


@@ -784,21 +810,20 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
        size_t size=0, idx=0;
        uint32_t code=0, code2=0;
 
        size_t size=0, idx=0;
        uint32_t code=0, code2=0;
 

+       // Configure to go in 125Khz listen mode
+       LFSetupFPGAForADC(95, true);

 
        while(!BUTTON_PRESS()) {
 
 
        while(!BUTTON_PRESS()) {
 

-               // Configure to go in 125Khz listen mode
-               SetupToAcquireRawAdcSamples(0);

 
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 
 
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 

-               DoAcquisition125k_internal(true);
+               DoAcquisition125k_internal(-1,true);

                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);
                size  = sizeof(BigBuf);
 
                // FSK demodulator
                size = fsk_demod(dest, size);

-               WDT_HIT();

 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 7
 
                // we now have a set of cycle counts, loop over previous results and aggregate data into bit patterns
                // 1->0 : fc/8 in sets of 7


@@ -911,8 +936,9 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {
 // Write one bit to card
 void T55xxWriteBit(int bit)
 {

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        if (bit == 0)
                SpinDelayUs(WRITE_0);
        else
        if (bit == 0)
                SpinDelayUs(WRITE_0);
        else


@@ -926,8 +952,9 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 {
        unsigned int i;
 
 {
        unsigned int i;
 

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up
 
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up


@@ -959,7 +986,7 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
        // Now perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
        SpinDelay(20);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }


@@ -970,6 +997,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
        uint8_t *dest = (uint8_t *)BigBuf;
        int m=0, i=0;
   
        uint8_t *dest = (uint8_t *)BigBuf;
        int m=0, i=0;
   

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
        memset(dest, 128, m);
        m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
        memset(dest, 128, m);


@@ -980,7 +1008,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up
   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up


@@ -1006,7 +1034,7 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Now do the acquisition
        i = 0;
   
        // Now do the acquisition
        i = 0;


@@ -1034,6 +1062,7 @@ void T55xxReadTrace(void){
        uint8_t *dest = (uint8_t *)BigBuf;
        int m=0, i=0;
   
        uint8_t *dest = (uint8_t *)BigBuf;
        int m=0, i=0;
   

+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

        m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
        memset(dest, 128, m);
        m = sizeof(BigBuf);
   // Clear destination buffer before sending the command
        memset(dest, 128, m);


@@ -1044,7 +1073,7 @@ void T55xxReadTrace(void){
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
        LED_D_ON();
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up
   
        // Give it a bit of time for the resonant antenna to settle.
        // And for the tag to fully power up


@@ -1060,7 +1089,7 @@ void T55xxReadTrace(void){
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   
   // Turn field on to read the response
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
        // Now do the acquisition
        i = 0;
   
        // Now do the acquisition
        i = 0;


@@ -1749,8 +1778,9 @@ void SendForward(uint8_t fwd_bit_count) {
   LED_D_ON();
   
   //Field on
   LED_D_ON();
   
   //Field on

+  FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up
   
   // Give it a bit of time for the resonant antenna to settle.
   // And for the tag to fully power up


@@ -1762,7 +1792,7 @@ void SendForward(uint8_t fwd_bit_count) {
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
   FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
   SpinDelayUs(55*8); //55 cycles off (8us each)for 4305
   FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+  FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting
   SpinDelayUs(16*8); //16 cycles on (8us each)
   
   // now start writting


@@ -1774,7 +1804,7 @@ void SendForward(uint8_t fwd_bit_count) {
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
       SpinDelayUs(23*8); //16-4 cycles off (8us each)
       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz

-      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);//field on
+      FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on

       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }
       SpinDelayUs(9*8); //16 cycles on (8us each)
     }
   }