#define rotl64(x, n) ((((u64)(x))<<((n)&63))+(((u64)(x))>>((0-(n))&63)))
// Single bit Hitag2 functions:
-
#define i4(x,a,b,c,d) ((u32)((((x)>>(a))&1)+(((x)>>(b))&1)*2+(((x)>>(c))&1)*4+(((x)>>(d))&1)*8))
static const u32 ht2_f4a = 0x2C79; // 0010 1100 0111 1001
static u32 _f20 (const u64 x)
{
- u32 i5;
+ u32 i5;
i5 = ((ht2_f4a >> i4 (x, 1, 2, 4, 5)) & 1)* 1
+ ((ht2_f4b >> i4 (x, 7,11,13,14)) & 1)* 2
static u64 _hitag2_init (const u64 key, const u32 serial, const u32 IV)
{
- u32 i;
- u64 x = ((key & 0xFFFF) << 32) + serial;
+ u32 i;
+ u64 x = ((key & 0xFFFF) << 32) + serial;
for (i = 0; i < 32; i++)
{
static u64 _hitag2_round (u64 *state)
{
- u64 x = *state;
+ u64 x = *state;
x = (x >> 1) +
((((x >> 0) ^ (x >> 2) ^ (x >> 3) ^ (x >> 6)
static u32 _hitag2_byte (u64 * x)
{
- u32 i, c;
+ u32 i, c;
for (i = 0, c = 0; i < 8; i++) c += (u32) _hitag2_round (x) << (i^7);
return c;
// Binary puls length modulation (BPLM) is used to encode the data stream
// This means that a transmission of a one takes longer than that of a zero
- // Enable modulation, which means, drop the the field
+ // Enable modulation, which means, drop the field
HIGH(GPIO_SSC_DOUT);
// Wait for 4-10 times the carrier period
}
// Send EOF
AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
- // Enable modulation, which means, drop the the field
+ // Enable modulation, which means, drop the field
HIGH(GPIO_SSC_DOUT);
// Wait for 4-10 times the carrier period
while(AT91C_BASE_TC0->TC_CV < T0*6);
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
// Clean up trace and prepare it for storing frames
- set_tracing(TRUE);
clear_trace();
+ set_tracing(TRUE);
auth_table_len = 0;
auth_table_pos = 0;
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
// Clean up trace and prepare it for storing frames
- set_tracing(TRUE);
clear_trace();
-
+ set_tracing(TRUE);
+
auth_table_len = 0;
auth_table_pos = 0;
byte_t* auth_table;
bSuccessful = false;
// Clean up trace and prepare it for storing frames
- set_tracing(TRUE);
clear_trace();
-
+ set_tracing(TRUE);
+
DbpString("Starting Hitag reader family");
// Check configuration