memset(BigBuf,0,sizeof(BigBuf));\r
\r
// Set up the synchronous serial port\r
memset(BigBuf,0,sizeof(BigBuf));\r
\r
// Set up the synchronous serial port\r
- SSC_CONTROL = SSC_CONTROL_RESET;\r
- SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
- // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
- // 48/2 = 24 MHz clock must be divided by 12\r
- SSC_CLOCK_DIVISOR = 12;\r
+ // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
+ // 48/2 = 24 MHz clock must be divided by 12\r
+ AT91C_BASE_SSC->SSC_CMR = 12;\r
- SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);\r
- SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;\r
- SSC_TRANSMIT_CLOCK_MODE = 0;\r
- SSC_TRANSMIT_FRAME_MODE = 0;\r
+ AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
+ AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
+ AT91C_BASE_SSC->SSC_TCMR = 0;\r
+ AT91C_BASE_SSC->SSC_TFMR = 0;\r
- if(SSC_STATUS & SSC_STATUS_RX_READY) {\r
- BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer\r
- i++; if(i >= TIBUFLEN) break;\r
- }\r
- WDT_HIT();\r
+ if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
+ BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
+ i++; if(i >= TIBUFLEN) break;\r
+ }\r
+ WDT_HIT();\r
- PIO_DISABLE = (1<<GPIO_SSC_DOUT);\r
- PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
WriteTIbyte(0x00); // write frame lo\r
WriteTIbyte(0x03); // write frame hi\r
WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
WriteTIbyte(0x00); // write frame lo\r
WriteTIbyte(0x03); // write frame hi\r
*/\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
*/\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
/* Set up Timer 1:\r
* Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
* external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
/* Set up Timer 1:\r
* Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
* external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
- PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_TC1);\r
- PIO_PERIPHERAL_B_SEL = (1 << GPIO_SSC_FRAME);\r
- TC1_CCR = TC_CCR_CLKDIS;\r
- TC1_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_ETRGEDG_RISING | TC_CMR_ABETRG |\r
- TC_CMR_LDRA_RISING | TC_CMR_LDRB_RISING;\r
- TC1_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
+ AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
+ AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
+ AT91C_TC_ETRGEDG_RISING |\r
+ AT91C_TC_ABETRG |\r
+ AT91C_TC_LDRA_RISING |\r
+ AT91C_TC_LDRB_RISING;\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
+ AT91C_TC_SWTRG;\r
/* Minor nuisance: In Capture mode, the timer can not be\r
* stopped by a Compare C. There's no way to stop the clock\r
* in software, so we'll just have to note the fact that an\r
* overflow happened and the next loaded timer value might\r
* have wrapped. Also, this marks the end of frame, and the\r
* still running counter can be used to determine the correct\r
/* Minor nuisance: In Capture mode, the timer can not be\r
* stopped by a Compare C. There's no way to stop the clock\r
* in software, so we'll just have to note the fact that an\r
* overflow happened and the next loaded timer value might\r
* have wrapped. Also, this marks the end of frame, and the\r
* still running counter can be used to determine the correct\r
\r
}\r
static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
{\r
OPEN_COIL();\r
\r
}\r
static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
{\r
OPEN_COIL();\r
\r
/* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
* not that since the clock counts since the rising edge, but T_wresp is\r
* with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
\r
/* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
* not that since the clock counts since the rising edge, but T_wresp is\r
* with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
- int saved_cmr = TC1_CMR;\r
- TC1_CMR &= ~TC_CMR_ETRGEDG; /* Disable external trigger for the clock */\r
- TC1_CCR = TC_CCR_SWTRG; /* Reset the clock and use it for response timing */\r
+ int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
+ AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
// we don't care about actual value, only if it's more or less than a\r
// threshold essentially we capture zero crossings for later analysis\r
if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
// we don't care about actual value, only if it's more or less than a\r
// threshold essentially we capture zero crossings for later analysis\r
if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
projects / proxmark3-svn / blobdiff