#include "hitag2.h"\r
#include "../common/crc16.c"\r
\r
+int sprintf(char *dest, const char *fmt, ...);\r
+\r
void AcquireRawAdcSamples125k(BOOL at134khz)\r
{\r
- if(at134khz) {\r
+ if (at134khz)\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- } else {\r
+ else\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- }\r
+\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
\r
// Connect the A/D to the peak-detected low-frequency path.\r
SetAdcMuxFor(GPIO_MUXSEL_LOPKD);\r
FpgaSetupSsc();\r
\r
// Now call the acquisition routine\r
- DoAcquisition125k(at134khz);\r
+ DoAcquisition125k();\r
}\r
\r
// split into two routines so we can avoid timing issues after sending commands //\r
-void DoAcquisition125k(BOOL at134khz)\r
+void DoAcquisition125k(void)\r
{\r
BYTE *dest = (BYTE *)BigBuf;\r
int n = sizeof(BigBuf);\r
int i;\r
-\r
- memset(dest,0,n);\r
+ \r
+ memset(dest, 0, n);\r
i = 0;\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
LED_D_ON();\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- dest[i] = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
+ dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
i++;\r
LED_D_OFF();\r
- if(i >= n) {\r
- break;\r
- }\r
+ if (i >= n) break;\r
}\r
}\r
- DbpIntegers(dest[0], dest[1], at134khz);\r
+ Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",\r
+ dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);\r
}\r
\r
-void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYTE *command)\r
+void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, BYTE *command)\r
{\r
BOOL at134khz;\r
\r
SpinDelay(2500);\r
\r
// see if 'h' was specified\r
- if(command[strlen((char *) command) - 1] == 'h')\r
- at134khz= TRUE;\r
+ if (command[strlen((char *) command) - 1] == 'h')\r
+ at134khz = TRUE;\r
else\r
- at134khz= FALSE;\r
+ at134khz = FALSE;\r
\r
- if(at134khz) {\r
+ if (at134khz)\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- } else {\r
+ else\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- }\r
+\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
\r
// Give it a bit of time for the resonant antenna to settle.\r
SpinDelay(50);\r
FpgaSetupSsc();\r
\r
// now modulate the reader field\r
- while(*command != '\0' && *command != ' ')\r
- {\r
+ while(*command != '\0' && *command != ' ') {\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
LED_D_OFF();\r
SpinDelayUs(delay_off);\r
- if(at134khz) {\r
+ if (at134khz)\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- } else {\r
+ else\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- }\r
+\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
LED_D_ON();\r
- if(*(command++) == '0') {\r
+ if(*(command++) == '0')\r
SpinDelayUs(period_0);\r
- } else {\r
+ else\r
SpinDelayUs(period_1);\r
- }\r
- }\r
+ }\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);\r
LED_D_OFF();\r
SpinDelayUs(delay_off);\r
- if(at134khz) {\r
+ if (at134khz)\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- } else {\r
+ else\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz\r
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
- }\r
+\r
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER);\r
\r
// now do the read\r
- DoAcquisition125k(at134khz);\r
+ DoAcquisition125k();\r
}\r
\r
/* blank r/w tag data stream\r
\r
[5555fe852c5555555555555555fe0000]\r
*/\r
-void ReadTItag()\r
+void ReadTItag(void)\r
{\r
// some hardcoded initial params\r
// when we read a TI tag we sample the zerocross line at 2Mhz\r
crc = update_crc16(crc, (shift1>>16)&0xff);\r
crc = update_crc16(crc, (shift1>>24)&0xff);\r
\r
- DbpString("Info: Tag data_hi, data_lo, crc = ");\r
- DbpIntegers(shift1, shift0, shift2&0xffff);\r
+ Dbprintf("Info: Tag data: %x%08x, crc=%x",\r
+ (unsigned int)shift1, (unsigned int)shift0, (unsigned int)shift2 & 0xFFFF);\r
if (crc != (shift2&0xffff)) {\r
- DbpString("Error: CRC mismatch, expected");\r
- DbpIntegers(0, 0, crc);\r
+ Dbprintf("Error: CRC mismatch, expected %x", (unsigned int)crc);\r
} else {\r
DbpString("Info: CRC is good");\r
}\r
{\r
if (b&(1<<i)) {\r
// stop modulating antenna\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ LOW(GPIO_SSC_DOUT);\r
SpinDelayUs(1000);\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelayUs(1000);\r
} else {\r
// stop modulating antenna\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ LOW(GPIO_SSC_DOUT);\r
SpinDelayUs(300);\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelayUs(1700);\r
}\r
}\r
memset(BigBuf,0,sizeof(BigBuf));\r
\r
// Set up the synchronous serial port\r
- PIO_DISABLE = (1<<GPIO_SSC_DIN);\r
- PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN);\r
+ AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;\r
+ AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN;\r
\r
// steal this pin from the SSP and use it to control the modulation\r
- PIO_ENABLE = (1<<GPIO_SSC_DOUT);\r
- PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
\r
- SSC_CONTROL = SSC_CONTROL_RESET;\r
- SSC_CONTROL = SSC_CONTROL_RX_ENABLE | SSC_CONTROL_TX_ENABLE;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_SWRST;\r
+ AT91C_BASE_SSC->SSC_CR = AT91C_SSC_RXEN | AT91C_SSC_TXEN;\r
\r
- // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
- // 48/2 = 24 MHz clock must be divided by 12\r
- SSC_CLOCK_DIVISOR = 12;\r
+ // Sample at 2 Mbit/s, so TI tags are 16.2 vs. 14.9 clocks long\r
+ // 48/2 = 24 MHz clock must be divided by 12\r
+ AT91C_BASE_SSC->SSC_CMR = 12;\r
\r
- SSC_RECEIVE_CLOCK_MODE = SSC_CLOCK_MODE_SELECT(0);\r
- SSC_RECEIVE_FRAME_MODE = SSC_FRAME_MODE_BITS_IN_WORD(32) | SSC_FRAME_MODE_MSB_FIRST;\r
- SSC_TRANSMIT_CLOCK_MODE = 0;\r
- SSC_TRANSMIT_FRAME_MODE = 0;\r
+ AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(0);\r
+ AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(32) | AT91C_SSC_MSBF;\r
+ AT91C_BASE_SSC->SSC_TCMR = 0;\r
+ AT91C_BASE_SSC->SSC_TFMR = 0;\r
\r
LED_D_ON();\r
\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
\r
// Charge TI tag for 50ms.\r
SpinDelay(50);\r
\r
// stop modulating antenna and listen\r
- PIO_OUTPUT_DATA_CLEAR = (1<<GPIO_SSC_DOUT);\r
+ LOW(GPIO_SSC_DOUT);\r
\r
LED_D_OFF();\r
\r
i = 0;\r
for(;;) {\r
- if(SSC_STATUS & SSC_STATUS_RX_READY) {\r
- BigBuf[i] = SSC_RECEIVE_HOLDING; // store 32 bit values in buffer\r
- i++; if(i >= TIBUFLEN) break;\r
- }\r
- WDT_HIT();\r
+ if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {\r
+ BigBuf[i] = AT91C_BASE_SSC->SSC_RHR; // store 32 bit values in buffer\r
+ i++; if(i >= TIBUFLEN) break;\r
+ }\r
+ WDT_HIT();\r
}\r
\r
// return stolen pin to SSP\r
- PIO_DISABLE = (1<<GPIO_SSC_DOUT);\r
- PIO_PERIPHERAL_A_SEL = (1<<GPIO_SSC_DIN) | (1<<GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;\r
\r
char *dest = (char *)BigBuf;\r
n = TIBUFLEN*32;\r
// unpack buffer\r
for (i=TIBUFLEN-1; i>=0; i--) {\r
-// DbpIntegers(0, 0, BigBuf[i]);\r
for (j=0; j<32; j++) {\r
if(BigBuf[i] & (1 << j)) {\r
dest[--n] = 1;\r
// if not provided a valid crc will be computed from the data and written.\r
void WriteTItag(DWORD idhi, DWORD idlo, WORD crc)\r
{\r
-\r
- // WARNING the order of the bytes in which we calc crc below needs checking\r
- // i'm 99% sure the crc algorithm is correct, but it may need to eat the\r
- // bytes in reverse or something\r
-\r
if(crc == 0) {\r
crc = update_crc16(crc, (idlo)&0xff);\r
crc = update_crc16(crc, (idlo>>8)&0xff);\r
crc = update_crc16(crc, (idhi>>16)&0xff);\r
crc = update_crc16(crc, (idhi>>24)&0xff);\r
}\r
- DbpString("Writing the following data to tag:");\r
- DbpIntegers(idhi, idlo, crc);\r
+ Dbprintf("Writing to tag: %x%08x, crc=%x",\r
+ (unsigned int) idhi, (unsigned int) idlo, crc);\r
\r
// TI tags charge at 134.2Khz\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz\r
LED_A_ON();\r
\r
// steal this pin from the SSP and use it to control the modulation\r
- PIO_ENABLE = (1<<GPIO_SSC_DOUT);\r
- PIO_OUTPUT_ENABLE = (1<<GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
\r
// writing algorithm:\r
// a high bit consists of a field off for 1ms and field on for 1ms\r
// finish with 15ms programming time\r
\r
// modulate antenna\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelay(50); // charge time\r
\r
WriteTIbyte(0xbb); // keyword\r
WriteTIbyte( (crc>>8 )&0xff ); // crc hi\r
WriteTIbyte(0x00); // write frame lo\r
WriteTIbyte(0x03); // write frame hi\r
- PIO_OUTPUT_DATA_SET = (1<<GPIO_SSC_DOUT);\r
+ HIGH(GPIO_SSC_DOUT);\r
SpinDelay(50); // programming time\r
\r
LED_A_OFF();\r
\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
\r
- PIO_ENABLE = (1 << GPIO_SSC_DOUT) | (1 << GPIO_SSC_CLK);\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;\r
\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);\r
- PIO_OUTPUT_DISABLE = (1 << GPIO_SSC_CLK);\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
+ AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;\r
\r
#define SHORT_COIL() LOW(GPIO_SSC_DOUT)\r
-#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
+#define OPEN_COIL() HIGH(GPIO_SSC_DOUT)\r
\r
i = 0;\r
for(;;) {\r
- while(!(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK))) {\r
+ while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {\r
if(BUTTON_PRESS()) {\r
DbpString("Stopped");\r
return;\r
if (ledcontrol)\r
LED_D_OFF();\r
\r
- while(PIO_PIN_DATA_STATUS & (1<<GPIO_SSC_CLK)) {\r
+ while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {\r
if(BUTTON_PRESS()) {\r
DbpString("Stopped");\r
return;\r
hitag2_init();\r
\r
/* Set up simulator mode, frequency divisor which will drive the FPGA\r
- * and analog mux selection.
+ * and analog mux selection.\r
*/\r
FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_SIMULATOR);\r
FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);\r
/* Set up Timer 1:\r
* Capture mode, timer source MCK/2 (TIMER_CLOCK1), TIOA is external trigger,\r
* external trigger rising edge, load RA on rising edge of TIOA, load RB on rising\r
- * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)
+ * edge of TIOA. Assign PA15 to TIOA1 (peripheral B)\r
*/\r
\r
- PMC_PERIPHERAL_CLK_ENABLE = (1 << PERIPH_TC1);\r
- PIO_PERIPHERAL_B_SEL = (1 << GPIO_SSC_FRAME);\r
- TC1_CCR = TC_CCR_CLKDIS;\r
- TC1_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CMR_ETRGEDG_RISING | TC_CMR_ABETRG |\r
- TC_CMR_LDRA_RISING | TC_CMR_LDRB_RISING;\r
- TC1_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG;\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC1);\r
+ AT91C_BASE_PIOA->PIO_BSR = GPIO_SSC_FRAME;\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;\r
+ AT91C_BASE_TC1->TC_CMR = TC_CMR_TCCLKS_TIMER_CLOCK1 |\r
+ AT91C_TC_ETRGEDG_RISING |\r
+ AT91C_TC_ABETRG |\r
+ AT91C_TC_LDRA_RISING |\r
+ AT91C_TC_LDRB_RISING;\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN |\r
+ AT91C_TC_SWTRG;\r
\r
/* calculate the new value for the carrier period in terms of TC1 values */\r
t0 = t0/2;\r
int overflow = 0;\r
while(!BUTTON_PRESS()) {\r
WDT_HIT();\r
- if(TC1_SR & TC_SR_LDRAS) {\r
- int ra = TC1_RA;\r
+ if(AT91C_BASE_TC1->TC_SR & AT91C_TC_LDRAS) {\r
+ int ra = AT91C_BASE_TC1->TC_RA;\r
if((ra > t0*HITAG_T_EOF) | overflow) ra = t0*HITAG_T_EOF+1;\r
#if DEBUG_RA_VALUES\r
if(ra > 255 || overflow) ra = 255;\r
overflow = 0;\r
LED_D_ON();\r
} else {\r
- if(TC1_CV > t0*HITAG_T_EOF) {\r
+ if(AT91C_BASE_TC1->TC_CV > t0*HITAG_T_EOF) {\r
/* Minor nuisance: In Capture mode, the timer can not be\r
* stopped by a Compare C. There's no way to stop the clock\r
* in software, so we'll just have to note the fact that an\r
* overflow happened and the next loaded timer value might\r
* have wrapped. Also, this marks the end of frame, and the\r
* still running counter can be used to determine the correct\r
- * time for the start of the reply.
+ * time for the start of the reply.\r
*/ \r
overflow = 1;\r
\r
/* Manchester: Loaded, then unloaded */\r
LED_A_ON();\r
SHORT_COIL();\r
- while(TC1_CV < t0*15);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*15);\r
OPEN_COIL();\r
- while(TC1_CV < t0*31);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*31);\r
LED_A_OFF();\r
} else if(bit == 0) {\r
/* Manchester: Unloaded, then loaded */\r
LED_B_ON();\r
OPEN_COIL();\r
- while(TC1_CV < t0*15);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*15);\r
SHORT_COIL();\r
- while(TC1_CV < t0*31);\r
+ while(AT91C_BASE_TC1->TC_CV < t0*31);\r
LED_B_OFF();\r
}\r
- TC1_CCR = TC_CCR_SWTRG; /* Reset clock for the next bit */\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset clock for the next bit */\r
\r
}\r
static void hitag_send_frame(int t0, int frame_len, const char const * frame, int fdt)\r
{\r
OPEN_COIL();\r
- PIO_OUTPUT_ENABLE = (1 << GPIO_SSC_DOUT);\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;\r
\r
/* Wait for HITAG_T_WRESP carrier periods after the last reader bit,\r
* not that since the clock counts since the rising edge, but T_wresp is\r
* with respect to the falling edge, we need to wait actually (T_wresp - T_g)\r
- * periods. The gap time T_g varies (4..10).
+ * periods. The gap time T_g varies (4..10).\r
*/\r
- while(TC1_CV < t0*(fdt-8));\r
+ while(AT91C_BASE_TC1->TC_CV < t0*(fdt-8));\r
\r
- int saved_cmr = TC1_CMR;\r
- TC1_CMR &= ~TC_CMR_ETRGEDG; /* Disable external trigger for the clock */\r
- TC1_CCR = TC_CCR_SWTRG; /* Reset the clock and use it for response timing */\r
+ int saved_cmr = AT91C_BASE_TC1->TC_CMR;\r
+ AT91C_BASE_TC1->TC_CMR &= ~AT91C_TC_ETRGEDG; /* Disable external trigger for the clock */\r
+ AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG; /* Reset the clock and use it for response timing */\r
\r
int i;\r
for(i=0; i<5; i++)\r
}\r
\r
OPEN_COIL();\r
- TC1_CMR = saved_cmr;\r
+ AT91C_BASE_TC1->TC_CMR = saved_cmr;\r
}\r
\r
/* Callback structure to cleanly separate tag emulation code from the radio layer. */\r
m = sizeof(BigBuf);\r
memset(dest,128,m);\r
for(;;) {\r
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {\r
- SSC_TRANSMIT_HOLDING = 0x43;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {\r
+ AT91C_BASE_SSC->SSC_THR = 0x43;\r
if (ledcontrol)\r
LED_D_ON();\r
}\r
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {\r
- dest[i] = (BYTE)SSC_RECEIVE_HOLDING;\r
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {\r
+ dest[i] = (BYTE)AT91C_BASE_SSC->SSC_RHR;\r
// we don't care about actual value, only if it's more or less than a\r
// threshold essentially we capture zero crossings for later analysis\r
if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;\r
found=1;\r
idx+=6;\r
if (found && (hi|lo)) {\r
- DbpString("TAG ID");\r
- DbpIntegers(hi, lo, (lo>>1)&0xffff);\r
+ Dbprintf("TAG ID: %x%08x (%d)",\r
+ (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
/* if we're only looking for one tag */\r
if (findone)\r
{\r
found=1;\r
idx+=6;\r
if (found && (hi|lo)) {\r
- DbpString("TAG ID");\r
- DbpIntegers(hi, lo, (lo>>1)&0xffff);\r
+ Dbprintf("TAG ID: %x%08x (%d)",\r
+ (unsigned int) hi, (unsigned int) lo, (unsigned int) (lo>>1) & 0xFFFF);\r
/* if we're only looking for one tag */\r
if (findone)\r
{\r
projects / proxmark3-svn / blobdiff