void DoAcquisition125k_internal(int trigger_threshold,bool silent)
{
uint8_t *dest = BigBuf_get_addr();
- int n = BigBuf_max_trace_len();
+ int n = BigBuf_max_traceLen();
int i;
memset(dest, 0, n);
#define FREQHI 134200
signed char *dest = (signed char *)BigBuf_get_addr();
- uint16_t n = BigBuf_max_trace_len();
+ uint16_t n = BigBuf_max_traceLen();
// 128 bit shift register [shift3:shift2:shift1:shift0]
uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
// clear buffer
uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
- memset(BigBuf,0,BigBuf_max_trace_len()/sizeof(uint32_t));
+ memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));
// Set up the synchronous serial port
AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
{
uint8_t *dest = BigBuf_get_addr();
-
- size_t size=sizeof(BigBuf);
+ const size_t sizeOfBigBuff = BigBuf_max_traceLen();
+ size_t size = 0;
uint32_t hi2=0, hi=0, lo=0;
int idx=0;
// Configure to go in 125Khz listen mode
DoAcquisition125k_internal(-1,true);
// FSK demodulator
- idx = HIDdemodFSK(dest, BigBuf_max_trace_len(), &hi2, &hi, &lo);
- WDT_HIT();
- size = sizeof(BigBuf);
-
+ size = sizeOfBigBuff; //variable size will change after demod so re initialize it before use
idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
if (idx>0 && lo>0){
}
if (findone){
if (ledcontrol) LED_A_OFF();
+ *high = hi;
+ *low = lo;
return;
}
// reset
if (ledcontrol) LED_A_ON();
DoAcquisition125k_internal(-1,true);
- size = BigBuf_max_trace_len();
+ size = BigBuf_max_traceLen();
//Dbprintf("DEBUG: Buffer got");
//askdemod and manchester decode
errCnt = askmandemod(dest, &size, &clk, &invert);
}
if (findone){
if (ledcontrol) LED_A_OFF();
+ *high=lo>>32;
+ *low=lo & 0xFFFFFFFF;
return;
}
} else{
DoAcquisition125k_internal(-1,true);
//fskdemod and get start index
WDT_HIT();
- idx = IOdemodFSK(dest, BigBuf_max_trace_len());
+ idx = IOdemodFSK(dest, BigBuf_max_traceLen());
if (idx>0){
//valid tag found
if (findone){
if (ledcontrol) LED_A_OFF();
//LED_A_OFF();
+ *high=code;
+ *low=code2;
return;
}
code=code2=0;
//int m=0, i=0; //enio adjustment 12/10/14
uint32_t m=0, i=0;
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
- m = BigBuf_max_trace_len();
+ m = BigBuf_max_traceLen();
// Clear destination buffer before sending the command
memset(dest, 128, m);
// Connect the A/D to the peak-detected low-frequency path.
int m=0, i=0;
FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
- m = BigBuf_max_trace_len();
+ m = BigBuf_max_traceLen();
// Clear destination buffer before sending the command
memset(dest, 128, m);
// Connect the A/D to the peak-detected low-frequency path.
uint8_t BitStream[256];
uint8_t Blocks[8][16];
uint8_t *GraphBuffer = BigBuf_get_addr();
- int GraphTraceLen = BigBuf_max_trace_len();
+ int GraphTraceLen = BigBuf_max_traceLen();
int i, j, lastval, bitidx, half_switch;
int clock = 64;
int tolerance = clock / 8;
fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
fwd_bit_count += Prepare_Addr( Address );
- m = BigBuf_max_trace_len();
+ m = BigBuf_max_traceLen();
// Clear destination buffer before sending the command
memset(dest, 128, m);
// Connect the A/D to the peak-detected low-frequency path.