ADD: @bm2gii some kind of andriod fix for the lua.

[proxmark3-svn] / common / protocols.h

diff --git a/common/protocols.h b/common/protocols.h
index c3591804bc0658ef939b1b53ba72cdc12964599c..152039b9e9efefe34c3822fa4f48553592064deb 100644 (file)
--- a/common/protocols.h
+++ b/common/protocols.h
@@ -31,6 +31,9 @@ ISO14443B
        05 = REQB
        1D = ATTRIB
        50 = HALT
        05 = REQB
        1D = ATTRIB
        50 = HALT

+       
+       BA = PING (reader -> tag)
+       AB = PONG (tag -> reader)

 SRIX4K (tag does not respond to 05)
        06 00 = INITIATE
        0E xx = SELECT ID (xx = Chip-ID)
 SRIX4K (tag does not respond to 05)
        06 00 = INITIATE
        0E xx = SELECT ID (xx = Chip-ID)


@@ -88,7 +91,29 @@ NXP/Philips CUSTOM COMMANDS
        BA = Enable Privacy
        BB = 64bit Password Protection
        40 = Long Range CMD (Standard ISO/TR7003:1990)
        BA = Enable Privacy
        BB = 64bit Password Protection
        40 = Long Range CMD (Standard ISO/TR7003:1990)

-               */
+
+ISO 7816-4 Basic interindustry commands. For command APDU's.
+       B0 = READ BINARY
+       D0 = WRITE BINARY
+       D6 = UPDATE BINARY
+       0E = ERASE BINARY
+       B2 = READ RECORDS
+       D2 = WRITE RECORDS
+       E2 = APPEND RECORD
+       DC = UPDATE RECORD
+       CA = GET DATA
+       DA = PUT DATA
+       A4 = SELECT FILE
+       20 = VERIFY
+       88 = INTERNAL AUTHENTICATION
+       82 = EXTERNAL AUTHENTICATION
+       B4 = GET CHALLENGE
+       70 = MANAGE CHANNEL
+
+       For response APDU's
+       90 00 = OK
+       6x xx = ERROR
+*/

 
 #define ICLASS_CMD_ACTALL           0x0A
 #define ICLASS_CMD_READ_OR_IDENTIFY 0x0C
 
 #define ICLASS_CMD_ACTALL           0x0A
 #define ICLASS_CMD_READ_OR_IDENTIFY 0x0C


@@ -109,7 +134,7 @@ NXP/Philips CUSTOM COMMANDS
 #define ISO14443A_CMD_WUPA       0x52
 #define ISO14443A_CMD_ANTICOLL_OR_SELECT     0x93
 #define ISO14443A_CMD_ANTICOLL_OR_SELECT_2   0x95
 #define ISO14443A_CMD_WUPA       0x52
 #define ISO14443A_CMD_ANTICOLL_OR_SELECT     0x93
 #define ISO14443A_CMD_ANTICOLL_OR_SELECT_2   0x95

-#define ISO14443A_CMD_WRITEBLOCK 0xA0 // or 0xA2 ?
+#define ISO14443A_CMD_WRITEBLOCK 0xA0

 #define ISO14443A_CMD_HALT       0x50
 #define ISO14443A_CMD_RATS       0xE0
 
 #define ISO14443A_CMD_HALT       0x50
 #define ISO14443A_CMD_RATS       0xE0
 


@@ -123,20 +148,26 @@ NXP/Philips CUSTOM COMMANDS
 #define MIFARE_CMD_RESTORE      0xC2
 #define MIFARE_CMD_TRANSFER     0xB0
 
 #define MIFARE_CMD_RESTORE      0xC2
 #define MIFARE_CMD_TRANSFER     0xB0
 

-//#define MIFARE_ULC_WRITE        0xA0
+#define MIFARE_EV1_PERSONAL_UID 0x40
+#define MIFARE_EV1_SETMODE             0x43
+
+
+#define MIFARE_ULC_WRITE        0xA2
+//#define MIFARE_ULC__COMP_WRITE  0xA0

 #define MIFARE_ULC_AUTH_1       0x1A
 #define MIFARE_ULC_AUTH_2       0xAF
 #define MIFARE_ULC_AUTH_1       0x1A
 #define MIFARE_ULC_AUTH_2       0xAF

+

 #define MIFARE_ULEV1_AUTH              0x1B
 #define MIFARE_ULEV1_AUTH              0x1B

-#define MIFARE_ULEV1_VERS              0x60
+#define MIFARE_ULEV1_VERSION   0x60

 #define MIFARE_ULEV1_FASTREAD  0x3A
 #define MIFARE_ULEV1_FASTREAD  0x3A

-#define MIFARE_ULEV1_WRITE             0xA2
-//#define MIFARE_ULEV1_COMP_WRITE      0xA0

 #define MIFARE_ULEV1_READ_CNT  0x39
 #define MIFARE_ULEV1_INCR_CNT  0xA5
 #define MIFARE_ULEV1_READSIG   0x3C
 #define MIFARE_ULEV1_CHECKTEAR 0x3E
 #define MIFARE_ULEV1_VCSL              0x4B
 
 #define MIFARE_ULEV1_READ_CNT  0x39
 #define MIFARE_ULEV1_INCR_CNT  0xA5
 #define MIFARE_ULEV1_READSIG   0x3C
 #define MIFARE_ULEV1_CHECKTEAR 0x3E
 #define MIFARE_ULEV1_VCSL              0x4B
 

+
+

 /**
 06 00 = INITIATE
 0E xx = SELECT ID (xx = Chip-ID)
 /**
 06 00 = INITIATE
 0E xx = SELECT ID (xx = Chip-ID)


@@ -159,6 +190,8 @@ NXP/Philips CUSTOM COMMANDS
 #define ISO14443B_RESET        0x0C
 #define ISO14443B_COMPLETION   0x0F
 #define ISO14443B_AUTHENTICATE 0x0A
 #define ISO14443B_RESET        0x0C
 #define ISO14443B_COMPLETION   0x0F
 #define ISO14443B_AUTHENTICATE 0x0A

+#define ISO14443B_PING            0xBA
+#define ISO14443B_PONG            0xAB

 
 //First byte is 26
 #define ISO15693_INVENTORY     0x01
 
 //First byte is 26
 #define ISO15693_INVENTORY     0x01


@@ -193,10 +226,11 @@ NXP/Philips CUSTOM COMMANDS
 #define TOPAZ_WRITE_NE8                                        0x1B    // Write-no-erase (eight bytes)
 
 
 #define TOPAZ_WRITE_NE8                                        0x1B    // Write-no-erase (eight bytes)
 
 

-#define ISO_14443A 0
-#define ICLASS     1
-#define ISO_14443B 2
+#define ISO_14443A     0
+#define ICLASS         1
+#define ISO_14443B     2

 #define TOPAZ          3
 #define TOPAZ          3

+#define ISO_7816_4  4

 
 //-- Picopass fuses
 #define FUSE_FPERS   0x80
 
 //-- Picopass fuses
 #define FUSE_FPERS   0x80


@@ -208,7 +242,82 @@ NXP/Philips CUSTOM COMMANDS
 #define FUSE_FPROD0  0x02
 #define FUSE_RA      0x01
 
 #define FUSE_FPROD0  0x02
 #define FUSE_RA      0x01
 

+// ISO 7816-4 Basic interindustry commands. For command APDU's.
+#define ISO7816_READ_BINARY 0xB0
+#define ISO7816_WRITE_BINARY 0xD0
+#define ISO7816_UPDATE_BINARY 0xD6
+#define ISO7816_ERASE_BINARY 0x0E
+#define ISO7816_READ_RECORDS 0xB2
+#define ISO7816_WRITE_RECORDS 0xD2
+#define ISO7816_APPEND_RECORD 0xE2
+#define ISO7816_UPDATE_RECORD 0xDC
+#define ISO7816_GET_DATA 0xCA
+#define ISO7816_PUT_DATA 0xDA
+#define ISO7816_SELECT_FILE 0xA4
+#define ISO7816_VERIFY 0x20
+#define ISO7816_INTERNAL_AUTHENTICATION 0x88
+#define ISO7816_EXTERNAL_AUTHENTICATION 0x82
+#define ISO7816_GET_CHALLENGE 0xB4
+#define ISO7816_MANAGE_CHANNEL 0x70

 
 

+// ISO7816-4   For response APDU's
+#define ISO7816_OK     0x9000
+//     6x xx = ERROR
+       

 void printIclassDumpInfo(uint8_t* iclass_dump);
 void printIclassDumpInfo(uint8_t* iclass_dump);

+void getMemConfig(uint8_t mem_cfg, uint8_t chip_cfg, uint8_t *max_blk, uint8_t *app_areas, uint8_t *kb);
+
+/* T55x7 configuration register definitions */
+#define T55x7_POR_DELAY                                0x00000001
+#define T55x7_ST_TERMINATOR                    0x00000008
+#define T55x7_PWD                                      0x00000010
+#define T55x7_MAXBLOCK_SHIFT           5
+#define T55x7_AOR                                      0x00000200
+#define T55x7_PSKCF_RF_2                       0
+#define T55x7_PSKCF_RF_4                       0x00000400
+#define T55x7_PSKCF_RF_8                       0x00000800
+#define T55x7_MODULATION_DIRECT                0
+#define T55x7_MODULATION_PSK1          0x00001000
+#define T55x7_MODULATION_PSK2          0x00002000
+#define T55x7_MODULATION_PSK3          0x00003000
+#define T55x7_MODULATION_FSK1          0x00004000
+#define T55x7_MODULATION_FSK2          0x00005000
+#define T55x7_MODULATION_FSK1a         0x00006000
+#define T55x7_MODULATION_FSK2a         0x00007000
+#define T55x7_MODULATION_MANCHESTER    0x00008000
+#define T55x7_MODULATION_BIPHASE       0x00010000
+#define T55x7_MODULATION_DIPHASE       0x00018000
+#define T55x7_BITRATE_RF_8                     0
+#define T55x7_BITRATE_RF_16                    0x00040000
+#define T55x7_BITRATE_RF_32                    0x00080000
+#define T55x7_BITRATE_RF_40                    0x000C0000
+#define T55x7_BITRATE_RF_50                    0x00100000
+#define T55x7_BITRATE_RF_64                    0x00140000
+#define T55x7_BITRATE_RF_100           0x00180000
+#define T55x7_BITRATE_RF_128           0x001C0000
+
+/* T5555 (Q5) configuration register definitions */
+#define T5555_ST_TERMINATOR                    0x00000001
+#define T5555_MAXBLOCK_SHIFT           0x00000001
+#define T5555_MODULATION_MANCHESTER    0
+#define T5555_MODULATION_PSK1          0x00000010
+#define T5555_MODULATION_PSK2          0x00000020
+#define T5555_MODULATION_PSK3          0x00000030
+#define T5555_MODULATION_FSK1          0x00000040
+#define T5555_MODULATION_FSK2          0x00000050
+#define T5555_MODULATION_BIPHASE       0x00000060
+#define T5555_MODULATION_DIRECT                0x00000070
+#define T5555_INVERT_OUTPUT                    0x00000080
+#define T5555_PSK_RF_2                         0
+#define T5555_PSK_RF_4                         0x00000100
+#define T5555_PSK_RF_8                         0x00000200
+#define T5555_USE_PWD                          0x00000400
+#define T5555_USE_AOR                          0x00000800
+#define T5555_BITRATE_SHIFT                    12
+#define T5555_FAST_WRITE                       0x00004000
+#define T5555_PAGE_SELECT                      0x00008000
+
+uint32_t GetT55xxClockBit(uint32_t clock);

 
 

-#endif // PROTOCOLS_H
+#endif 
+// PROTOCOLS_H