Bugfixes for LF FDX

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index e25c6e0ba8e98d9c836082568150281f1581084e..aac68a344f74ddd9bca70e9015a03a8851d86127 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -81,11 +81,6 @@ void lsl (uint8_t *data, size_t len) {
     data[len - 1] <<= 1;
 }
 
     data[len - 1] <<= 1;
 }
 

-int32_t le24toh (uint8_t data[3])
-{
-    return (data[2] << 16) | (data[1] << 8) | data[0];
-}
-

 void LEDsoff()
 {
        LED_A_OFF();
 void LEDsoff()
 {
        LED_A_OFF();


@@ -94,6 +89,22 @@ void LEDsoff()
        LED_D_OFF();
 }
 
        LED_D_OFF();
 }
 

+void LEDson()
+{
+       LED_A_ON();
+       LED_B_ON();
+       LED_C_ON();
+       LED_D_ON();
+}
+
+void LEDsinvert()
+{
+       LED_A_INV();
+       LED_B_INV();
+       LED_C_INV();
+       LED_D_INV();
+}
+

 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 void LED(int led, int ms)
 {
 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 void LED(int led, int ms)
 {


@@ -378,13 +389,13 @@ void StartCountSspClk()
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
                                                        | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
                                                        | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
                                                        | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
                                                        | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event

-                                                       | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
+                                                       | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16 ... 13,56MHz/4)

                                                        | AT91C_TC_ENETRG                               // Enable external trigger event
                                                        | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_AEEVT_SET                    // Set TIOA1 on external event
                                                        | AT91C_TC_ACPC_CLEAR;                  // Clear TIOA1 on RC Compare
                                                        | AT91C_TC_ENETRG                               // Enable external trigger event
                                                        | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_AEEVT_SET                    // Set TIOA1 on external event
                                                        | AT91C_TC_ACPC_CLEAR;                  // Clear TIOA1 on RC Compare

-       AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
+       AT91C_BASE_TC1->TC_RC = 0x02;                                                   // RC Compare value = 0x02

 
        // use TC0 to count TIOA1 pulses
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0
 
        // use TC0 to count TIOA1 pulses
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0


@@ -407,7 +418,7 @@ void StartCountSspClk()
        AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
 
        //
        AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
 
        //

-       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14443 mode, otherwise SSC_FRAME and SSC_CLK signals would not be present 
+       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in a FPGA mode with SSC transfer, otherwise SSC_FRAME and SSC_CLK signals would not be present 

        //
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
        //
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low


@@ -435,44 +446,65 @@ void ResetSspClk(void) {
 }
 
 
 }
 
 

-uint32_t RAMFUNC GetCountSspClk(){
-       uint32_t tmp_count;
-       tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
-       if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
-               return (AT91C_BASE_TC2->TC_CV << 16);
-       } 
-       else {
-               return tmp_count;
-       }
+uint32_t GetCountSspClk(){
+       uint32_t hi, lo;
+
+       do {
+               hi = AT91C_BASE_TC2->TC_CV;
+               lo = AT91C_BASE_TC0->TC_CV;
+       } while(hi != AT91C_BASE_TC2->TC_CV);
+
+       return (hi << 16) | lo;

 }
 
 
 //  -------------------------------------------------------------------------
 }
 
 
 //  -------------------------------------------------------------------------

-//  Timer for bitbanging,  or LF stuff when you need a very precis timer
+//  Timer for bitbanging, or LF stuff when you need a very precis timer

 //  1us = 1.5ticks
 //  -------------------------------------------------------------------------
 void StartTicks(void){
 //  1us = 1.5ticks
 //  -------------------------------------------------------------------------
 void StartTicks(void){

-       //initialization of the timer
-       // tc1 is higher 0xFFFF0000
-       // tc0 is lower 0x0000FFFF
+       // initialization of the timer

        AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
        AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;

+
+       // disable TC0 and TC1 for re-configuration

        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;

+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+
+       // first configure TC1 (higher, 0xFFFF0000) 16 bit counter
+       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // just connect to TIOA0 from TC0
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
+
+       // second configure TC0 (lower, 0x0000FFFF) 16 bit counter

        AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32 
        AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32 

-                                                               AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
-                                                               AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
-       AT91C_BASE_TC0->TC_RA = 1;
-       AT91C_BASE_TC0->TC_RC = 0; 
+                                AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
+                                AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
+                                AT91C_TC_ACPC_SET |   // RC comperator sets TIOA (carry bit)
+                                AT91C_TC_ASWTRG_SET;  // SWTriger sets TIOA (carry bit)
+       AT91C_BASE_TC0->TC_RC  = 0; // set TIOA (carry bit) on overflow, return to zero
+       AT91C_BASE_TC0->TC_RA  = 1; // clear carry bit on next clock cycle
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer
+
+       // synchronized startup procedure
+       while (AT91C_BASE_TC0->TC_CV > 0); // wait until TC0 returned to zero
+       while (AT91C_BASE_TC0->TC_CV < 2); // and has started (TC_CV > TC_RA, now TC1 is cleared)
+
+       // return to zero
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC0->TC_CV > 0);
+}

 
 

-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;       // timer disable  
-       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from TC0
-       
-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
-       AT91C_BASE_TCB->TCB_BCR = 1;
-       
-       // wait until timer becomes zero.
-       while (AT91C_BASE_TC1->TC_CV > 0);
+
+uint32_t GetTicks(void) {
+       uint32_t hi, lo;
+
+       do {
+               hi = AT91C_BASE_TC1->TC_CV;
+               lo = AT91C_BASE_TC0->TC_CV;
+       } while(hi != AT91C_BASE_TC1->TC_CV);
+
+       return (hi << 16) | lo;

 }
 
 
 }
 
 


@@ -480,30 +512,28 @@ void StartTicks(void){
 // if called with a high number, this will trigger the WDT...
 void WaitTicks(uint32_t ticks){
        if ( ticks == 0 ) return;
 // if called with a high number, this will trigger the WDT...
 void WaitTicks(uint32_t ticks){
        if ( ticks == 0 ) return;

-       ticks += GET_TICKS;     
-       while (GET_TICKS < ticks);
+       ticks += GetTicks();
+       while (GetTicks() < ticks);

 }
 
 
 // Wait / Spindelay in us (microseconds) 
 // 1us = 1.5ticks.
 void WaitUS(uint16_t us){
 }
 
 
 // Wait / Spindelay in us (microseconds) 
 // 1us = 1.5ticks.
 void WaitUS(uint16_t us){

-       if ( us == 0 ) return;
-       WaitTicks(  (uint32_t)(us * 1.5) );
+       WaitTicks( (uint32_t)us * 3 / 2 ) ;

 }
 
 
 void WaitMS(uint16_t ms){
 }
 
 
 void WaitMS(uint16_t ms){

-       if (ms == 0) return;
-       WaitTicks( (uint32_t)(ms * 1500) );
+       WaitTicks( (uint32_t)ms * 1500 );

 }
 
 
 // Starts Clock and waits until its reset
 void ResetTicks(void){
 }
 
 
 // Starts Clock and waits until its reset
 void ResetTicks(void){

-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;

        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;

-       while (AT91C_BASE_TC1->TC_CV > 0);
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC0->TC_CV > 0);

 }
 
 
 }