Merge branch 'master' into fix_iclass_sim

[proxmark3-svn] / fpga / hi_simulate.v

diff --git a/fpga/hi_simulate.v b/fpga/hi_simulate.v
index c04ade80b098a474218fa8693c537ebe17729a14..5fc2e11354807d5ef96164e319303492b035047e 100644 (file)
--- a/fpga/hi_simulate.v
+++ b/fpga/hi_simulate.v
@@ -17,98 +17,129 @@
 //-----------------------------------------------------------------------------
 
 module hi_simulate(
 //-----------------------------------------------------------------------------
 
 module hi_simulate(

-    pck0, ck_1356meg, ck_1356megb,
+    ck_1356meg,

     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
     adc_d, adc_clk,
     ssp_frame, ssp_din, ssp_dout, ssp_clk,
     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
     adc_d, adc_clk,
     ssp_frame, ssp_din, ssp_dout, ssp_clk,

-    cross_hi, cross_lo,

     dbg,
     mod_type
 );
     dbg,
     mod_type
 );

-    input pck0, ck_1356meg, ck_1356megb;
+    input ck_1356meg;

     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
     input [7:0] adc_d;
     output adc_clk;
     input ssp_dout;
     output ssp_frame, ssp_din, ssp_clk;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
     input [7:0] adc_d;
     output adc_clk;
     input ssp_dout;
     output ssp_frame, ssp_din, ssp_clk;

-    input cross_hi, cross_lo;

     output dbg;
     input [2:0] mod_type;
 
     output dbg;
     input [2:0] mod_type;
 

-// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
-// always be low.
-assign pwr_hi = 1'b0;
-assign pwr_lo = 1'b0;
+assign adc_clk = ck_1356meg;

 
 // The comparator with hysteresis on the output from the peak detector.
 reg after_hysteresis;
 
 // The comparator with hysteresis on the output from the peak detector.
 reg after_hysteresis;

-assign adc_clk = ck_1356meg;
+reg [11:0] has_been_low_for;

 
 always @(negedge adc_clk)
 begin
 
 always @(negedge adc_clk)
 begin

-    if(& adc_d[7:5]) after_hysteresis = 1'b1;
-    else if(~(| adc_d[7:5])) after_hysteresis = 1'b0;
+    if (& adc_d[7:5]) after_hysteresis <= 1'b1;           // if (adc_d >= 224)
+    else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0;   // if (adc_d <= 31)
+
+       if (adc_d >= 224)
+    begin
+        has_been_low_for <= 12'd0;
+    end
+    else
+    begin
+        if (has_been_low_for == 12'd4095)
+        begin
+            has_been_low_for <= 12'd0;
+            after_hysteresis <= 1'b1;
+        end
+        else
+               begin
+            has_been_low_for <= has_been_low_for + 1;
+               end     
+    end

 end
 
 end
 

-// Divide 13.56 MHz by 32 to produce the SSP_CLK
-// The register is bigger to allow higher division factors of up to /128
-reg [6:0] ssp_clk_divider;
-always @(posedge adc_clk)
+
+// Divide 13.56 MHz to produce various frequencies for SSP_CLK
+// and modulation.
+reg [8:0] ssp_clk_divider;
+
+always @(negedge adc_clk)

     ssp_clk_divider <= (ssp_clk_divider + 1);
     ssp_clk_divider <= (ssp_clk_divider + 1);

-assign ssp_clk = ssp_clk_divider[4];
-
-// Divide SSP_CLK by 8 to produce the byte framing signal; the phase of
-// this is arbitrary, because it's just a bitstream.
-// One nasty issue, though: I can't make it work with both rx and tx at
-// once. The phase wrt ssp_clk must be changed. TODO to find out why
-// that is and make a better fix.
-reg [2:0] ssp_frame_divider_to_arm;
-always @(posedge ssp_clk)
-    ssp_frame_divider_to_arm <= (ssp_frame_divider_to_arm + 1);
-reg [2:0] ssp_frame_divider_from_arm;
-always @(negedge ssp_clk)
-    ssp_frame_divider_from_arm <= (ssp_frame_divider_from_arm + 1);

 
 

-reg ssp_frame;
-always @(ssp_frame_divider_to_arm or ssp_frame_divider_from_arm or mod_type)
-    if(mod_type == 3'b000) // not modulating, so listening, to ARM
-        ssp_frame = (ssp_frame_divider_to_arm == 3'b000);
+reg ssp_clk;
+
+always @(negedge adc_clk)
+begin
+    if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
+      // Get bit every at 53KHz (every 8th carrier bit of 424kHz)
+      ssp_clk <= ~ssp_clk_divider[7];
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
+      // Get next bit at 212kHz
+      ssp_clk <= ~ssp_clk_divider[5];

     else
     else

-        ssp_frame = (ssp_frame_divider_from_arm == 3'b000);
+      // Get next bit at 424Khz
+      ssp_clk <= ~ssp_clk_divider[4];
+end
+
+
+// Produce the byte framing signal; the phase of this signal 
+// is arbitrary, because it's just a bit stream in this module.
+reg ssp_frame;
+always @(negedge adc_clk)
+begin
+       if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
+       begin
+               if (ssp_clk_divider[8:5] == 4'd1)
+                       ssp_frame <= 1'b1;
+               if (ssp_clk_divider[8:5] == 4'd5)
+                       ssp_frame <= 1'b0;
+       end
+       else
+       begin
+               if (ssp_clk_divider[7:4] == 4'd1)
+                       ssp_frame <= 1'b1;
+               if (ssp_clk_divider[7:4] == 4'd5)
+                       ssp_frame <= 1'b0;
+       end
+end
+

 
 // Synchronize up the after-hysteresis signal, to produce DIN.
 reg ssp_din;
 always @(posedge ssp_clk)
     ssp_din = after_hysteresis;
 
 
 // Synchronize up the after-hysteresis signal, to produce DIN.
 reg ssp_din;
 always @(posedge ssp_clk)
     ssp_din = after_hysteresis;
 

-// Modulating carrier frequency is fc/16, reuse ssp_clk divider for that
+// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.

 reg modulating_carrier;
 reg modulating_carrier;

-always @(mod_type or ssp_clk or ssp_dout)
-    if(mod_type == 3'b000)
+always @(*)
+    if (mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)

         modulating_carrier <= 1'b0;                          // no modulation
         modulating_carrier <= 1'b0;                          // no modulation

-    else if(mod_type == 3'b001)
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)

         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
         modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK

-    else if(mod_type == 3'b010)
-       modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
-    else if(mod_type == 3'b100)
-       modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
+        modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
+    else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
+        modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off

     else
         modulating_carrier <= 1'b0;                           // yet unused
 
     else
         modulating_carrier <= 1'b0;                           // yet unused
 

-// This one is all LF, so doesn't matter
-assign pwr_oe2 = modulating_carrier;

 
 

-// Toggle only one of these, since we are already producing much deeper
+// Load modulation. Toggle only one of these, since we are already producing much deeper

 // modulation than a real tag would.
 // modulation than a real tag would.

-assign pwr_oe1 = modulating_carrier;
-assign pwr_oe4 = modulating_carrier;
+assign pwr_hi = 1'b0;                   // HF antenna connected to GND
+assign pwr_oe3 = 1'b0;                  // 10k Load
+assign pwr_oe1 = 1'b0;                  // 33 Ohms Load
+assign pwr_oe4 = modulating_carrier;    // 33 Ohms Load
+
+// This is all LF and doesn't matter
+assign pwr_lo = 1'b0;
+assign pwr_oe2 = 1'b0;

 
 

-// This one is always on, so that we can watch the carrier.
-assign pwr_oe3 = 1'b0;

 
 

-assign dbg = after_hysteresis;
-//reg dbg;
-//always @(ssp_dout)
-//    dbg <= ssp_dout;
+assign dbg = ssp_frame;

 
 endmodule
 
 endmodule