lf hid fskdemod bug

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 9bea9e7efbcddc3c5adf29b21a30090afc9cfc7e..674f1b91f5ef76d129fa3b200eeb0605ef49b364 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -11,6 +11,27 @@
 #include "proxmark3.h"
 #include "util.h"
 #include "string.h"
 #include "proxmark3.h"
 #include "util.h"
 #include "string.h"

+#include "apps.h"
+
+
+
+void print_result(char *name, uint8_t *buf, size_t len) {
+   uint8_t *p = buf;
+
+   if ( len % 16 == 0 ) {
+          for(; p-buf < len; p += 16)
+       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+                               name,
+                               p-buf,
+                               len,
+                               p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7],p[8], p[9], p[10], p[11], p[12], p[13], p[14], p[15]
+          );
+   }
+   else {
+   for(; p-buf < len; p += 8)
+       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+   }
+}

 
 size_t nbytes(size_t nbits) {
        return (nbits/8)+((nbits%8)>0);
 
 size_t nbytes(size_t nbits) {
        return (nbits/8)+((nbits%8)>0);


@@ -44,6 +65,26 @@ uint64_t bytes_to_num(uint8_t* src, size_t len)
        return num;
 }
 
        return num;
 }
 

+// RotateLeft - Ultralight, Desfire
+void rol(uint8_t *data, const size_t len){
+    uint8_t first = data[0];
+    for (size_t i = 0; i < len-1; i++) {
+        data[i] = data[i+1];
+    }
+    data[len-1] = first;
+}
+void lsl (uint8_t *data, size_t len) {
+    for (size_t n = 0; n < len - 1; n++) {
+        data[n] = (data[n] << 1) | (data[n+1] >> 7);
+    }
+    data[len - 1] <<= 1;
+}
+
+int32_t le24toh (uint8_t data[3])
+{
+    return (data[2] << 16) | (data[1] << 8) | data[0];
+}
+

 void LEDsoff()
 {
        LED_A_OFF();
 void LEDsoff()
 {
        LED_A_OFF();


@@ -224,29 +265,29 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 {
        struct version_information *v = (struct version_information*)version_information;
        dst[0] = 0;
 {
        struct version_information *v = (struct version_information*)version_information;
        dst[0] = 0;

-       strncat(dst, prefix, len);
+       strncat(dst, prefix, len-1);

        if(v->magic != VERSION_INFORMATION_MAGIC) {
        if(v->magic != VERSION_INFORMATION_MAGIC) {

-               strncat(dst, "Missing/Invalid version information", len);
+               strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);

                return;
        }
        if(v->versionversion != 1) {
                return;
        }
        if(v->versionversion != 1) {

-               strncat(dst, "Version information not understood", len);
+               strncat(dst, "Version information not understood", len - strlen(dst) - 1);

                return;
        }
        if(!v->present) {
                return;
        }
        if(!v->present) {

-               strncat(dst, "Version information not available", len);
+               strncat(dst, "Version information not available", len - strlen(dst) - 1);

                return;
        }
 
                return;
        }
 

-       strncat(dst, v->svnversion, len);
+       strncat(dst, v->gitversion, len - strlen(dst) - 1);

        if(v->clean == 0) {
        if(v->clean == 0) {

-               strncat(dst, "-unclean", len);
+               strncat(dst, "-unclean", len - strlen(dst) - 1);

        } else if(v->clean == 2) {
        } else if(v->clean == 2) {

-               strncat(dst, "-suspect", len);
+               strncat(dst, "-suspect", len - strlen(dst) - 1);

        }
 
        }
 

-       strncat(dst, " ", len);
-       strncat(dst, v->buildtime, len);
+       strncat(dst, " ", len - strlen(dst) - 1);
+       strncat(dst, v->buildtime, len - strlen(dst) - 1);

 }
 
 //  -------------------------------------------------------------------------
 }
 
 //  -------------------------------------------------------------------------


@@ -315,9 +356,9 @@ uint32_t RAMFUNC GetDeltaCountUS(){
 
 
 //  -------------------------------------------------------------------------
 
 
 //  -------------------------------------------------------------------------

-//  Mifare timer. Uses ssp_clk from FPGA 
+//  Timer for iso14443 commands. Uses ssp_clk from FPGA 

 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------

-void StartCountMifare()
+void StartCountSspClk()

 {
        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
 {
        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1


@@ -329,7 +370,7 @@ void StartCountMifare()
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
                                                        | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
                                                        | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
                                                        | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
                                                        | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event

-                                                       | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssc_clk from FPGA = 13,56MHz / 16)
+                                                       | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)

                                                        | AT91C_TC_ENETRG                               // Enable external trigger event
                                                        | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_ENETRG                               // Enable external trigger event
                                                        | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
                                                        | AT91C_TC_WAVE                                 // Waveform Mode


@@ -338,7 +379,7 @@ void StartCountMifare()
        AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
 
        // use TC0 to count TIOA1 pulses
        AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
 
        // use TC0 to count TIOA1 pulses

-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0  
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0

        AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0                              // TC0 clock = XC0 clock = TIOA1
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP                   // just count
        AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0                              // TC0 clock = XC0 clock = TIOA1
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP                   // just count


@@ -353,21 +394,38 @@ void StartCountMifare()
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP;                  // just count
        
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP;                  // just count
        

-       

        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
        AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
        AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2

+
+       //
+       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
+       //
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
+       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
+       // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
+       // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge

        AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
        AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)

+       // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
+       // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
+       // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
+       // (just started with the transfer of the 4th Bit).
+       // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
+       // we can use the counter.
+       while (AT91C_BASE_TC0->TC_CV < 0xFFF0);

 }
 
 
 }
 
 

-uint32_t RAMFUNC GetCountMifare(){
+uint32_t RAMFUNC GetCountSspClk(){

        uint32_t tmp_count;
        tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
        uint32_t tmp_count;
        tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;

-       if ((tmp_count & 0xffff) == 0) { //small chance that we may have missed an increment in TC2
+       if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2

                return (AT91C_BASE_TC2->TC_CV << 16);
        } 
        else {
                return tmp_count;
        }
 }
                return (AT91C_BASE_TC2->TC_CV << 16);
        } 
        else {
                return tmp_count;
        }
 }

+
+