Added a lf acquisition-mode which can do decimation and quantization, in order to...

[proxmark3-svn] / fpga / hi_read_tx.v

diff --git a/fpga/hi_read_tx.v b/fpga/hi_read_tx.v
index 5ddc974daf9e54d860beece320554a94eb5e0c17..f12e64eb65c2f8fea1adf6eba8dd211a8ff33a61 100644 (file)
--- a/fpga/hi_read_tx.v
+++ b/fpga/hi_read_tx.v
@@ -1,89 +1,89 @@
-//-----------------------------------------------------------------------------\r
-// The way that we connect things when transmitting a command to an ISO\r
-// 15693 tag, using 100% modulation only for now.\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-\r
-module hi_read_tx(\r
-    pck0, ck_1356meg, ck_1356megb,\r
-    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
-    adc_d, adc_clk,\r
-    ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
-    cross_hi, cross_lo,\r
-    dbg,\r
-    shallow_modulation\r
-);\r
-    input pck0, ck_1356meg, ck_1356megb;\r
-    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
-    input [7:0] adc_d;\r
-    output adc_clk;\r
-    input ssp_dout;\r
-    output ssp_frame, ssp_din, ssp_clk;\r
-    input cross_hi, cross_lo;\r
-    output dbg;\r
-    input shallow_modulation;\r
-\r
-// The high-frequency stuff. For now, for testing, just bring out the carrier,\r
-// and allow the ARM to modulate it over the SSP.\r
-reg pwr_hi;\r
-reg pwr_oe1;\r
-reg pwr_oe2;\r
-reg pwr_oe3;\r
-reg pwr_oe4;\r
-always @(ck_1356megb or ssp_dout or shallow_modulation)\r
-begin\r
-    if(shallow_modulation)\r
-    begin\r
-        pwr_hi <= ck_1356megb;\r
-        pwr_oe1 <= ~ssp_dout;\r
-        pwr_oe2 <= ~ssp_dout;\r
-        pwr_oe3 <= ~ssp_dout;\r
-        pwr_oe4 <= 1'b0;\r
-    end\r
-    else\r
-    begin\r
-        pwr_hi <= ck_1356megb & ssp_dout;\r
-        pwr_oe1 <= 1'b0;\r
-        pwr_oe2 <= 1'b0;\r
-        pwr_oe3 <= 1'b0;\r
-        pwr_oe4 <= 1'b0;\r
-    end\r
-end\r
-\r
-// Then just divide the 13.56 MHz clock down to produce appropriate clocks\r
-// for the synchronous serial port.\r
-\r
-reg [6:0] hi_div_by_128;\r
-\r
-always @(posedge ck_1356meg)\r
-    hi_div_by_128 <= hi_div_by_128 + 1;\r
-\r
-assign ssp_clk = hi_div_by_128[6];\r
-\r
-reg [2:0] hi_byte_div;\r
-\r
-always @(negedge ssp_clk)\r
-    hi_byte_div <= hi_byte_div + 1;\r
-\r
-assign ssp_frame = (hi_byte_div == 3'b000);\r
-\r
-// Implement a hysteresis to give out the received signal on\r
-// ssp_din. Sample at fc.\r
-assign adc_clk = ck_1356meg;\r
-\r
-// ADC data appears on the rising edge, so sample it on the falling edge\r
-reg after_hysteresis;\r
-always @(negedge adc_clk)\r
-begin\r
-    if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
-    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
-end\r
-\r
-\r
-assign ssp_din = after_hysteresis;\r
-\r
-assign pwr_lo = 1'b0;\r
-assign dbg = ssp_din;\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+// The way that we connect things when transmitting a command to an ISO
+// 15693 tag, using 100% modulation only for now.
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module hi_read_tx(
+    pck0, ck_1356meg, ck_1356megb,
+    pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+    adc_d, adc_clk,
+    ssp_frame, ssp_din, ssp_dout, ssp_clk,
+    cross_hi, cross_lo,
+    dbg,
+    shallow_modulation
+);
+    input pck0, ck_1356meg, ck_1356megb;
+    output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+    input [7:0] adc_d;
+    output adc_clk;
+    input ssp_dout;
+    output ssp_frame, ssp_din, ssp_clk;
+    input cross_hi, cross_lo;
+    output dbg;
+    input shallow_modulation;
+
+// The high-frequency stuff. For now, for testing, just bring out the carrier,
+// and allow the ARM to modulate it over the SSP.
+reg pwr_hi;
+reg pwr_oe1;
+reg pwr_oe2;
+reg pwr_oe3;
+reg pwr_oe4;
+always @(ck_1356megb or ssp_dout or shallow_modulation)
+begin
+    if(shallow_modulation)
+    begin
+        pwr_hi <= ck_1356megb;
+        pwr_oe1 <= ~ssp_dout;
+        pwr_oe2 <= ~ssp_dout;
+        pwr_oe3 <= ~ssp_dout;
+        pwr_oe4 <= 1'b0;
+    end
+    else
+    begin
+        pwr_hi <= ck_1356megb & ssp_dout;
+        pwr_oe1 <= 1'b0;
+        pwr_oe2 <= 1'b0;
+        pwr_oe3 <= 1'b0;
+        pwr_oe4 <= 1'b0;
+    end
+end
+
+// Then just divide the 13.56 MHz clock down to produce appropriate clocks
+// for the synchronous serial port.
+
+reg [6:0] hi_div_by_128;
+
+always @(posedge ck_1356meg)
+    hi_div_by_128 <= hi_div_by_128 + 1;
+
+assign ssp_clk = hi_div_by_128[6];
+
+reg [2:0] hi_byte_div;
+
+always @(negedge ssp_clk)
+    hi_byte_div <= hi_byte_div + 1;
+
+assign ssp_frame = (hi_byte_div == 3'b000);
+
+// Implement a hysteresis to give out the received signal on
+// ssp_din. Sample at fc.
+assign adc_clk = ck_1356meg;
+
+// ADC data appears on the rising edge, so sample it on the falling edge
+reg after_hysteresis;
+always @(negedge adc_clk)
+begin
+    if(& adc_d[7:0]) after_hysteresis <= 1'b1;
+    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
+end
+
+
+assign ssp_din = after_hysteresis;
+
+assign pwr_lo = 1'b0;
+assign dbg = ssp_din;
+
+endmodule