0x01, // bNumEndpoints\r
0x02, // bInterfaceClass\r
0x02, // bInterfaceSubclass\r
- 0x01, // bInterfaceProtocol\r
+ 0x00, // bInterfaceProtocol\r
0x00, // iInterface\r
\r
/* Header Functional Descriptor */\r
void usb_disable() {\r
// Disconnect the USB device\r
AT91C_BASE_PIOA->PIO_ODR = GPIO_USB_PU;\r
-// SpinDelay(100);\r
\r
// Clear all lingering interrupts\r
if(pUdp->UDP_ISR & AT91C_UDP_ENDBUSRES) {\r
//* \brief This function Activates the USB device\r
//*----------------------------------------------------------------------------\r
void usb_enable() {\r
- // Set the PLL USB Divider\r
- AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ;\r
- \r
- // Specific Chip USB Initialisation\r
- // Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock\r
- AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;\r
- AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);\r
- \r
- // Enable UDP PullUp (USB_DP_PUP) : enable & Clear of the corresponding PIO\r
- // Set in PIO mode and Configure in Output\r
- AT91C_BASE_PIOA->PIO_PER = GPIO_USB_PU; // Set in PIO mode\r
+ // Set the PLL USB Divider\r
+ AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ;\r
+\r
+ // Specific Chip USB Initialisation\r
+ // Enables the 48MHz USB clock UDPCK and System Peripheral USB Clock\r
+ AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_UDP;\r
+ AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_UDP);\r
+\r
+ // Enable UDP PullUp (USB_DP_PUP) : enable & Clear of the corresponding PIO\r
+ // Set in PIO mode and Configure in Output\r
+ AT91C_BASE_PIOA->PIO_PER = GPIO_USB_PU; // Set in PIO mode\r
AT91C_BASE_PIOA->PIO_OER = GPIO_USB_PU; // Configure as Output\r
- \r
- // Clear for set the Pullup resistor\r
+\r
+ // Clear for set the Pullup resistor\r
AT91C_BASE_PIOA->PIO_CODR = GPIO_USB_PU;\r
- \r
- // Disconnect and reconnect USB controller for 100ms\r
- usb_disable();\r
- \r
- // Wait for a short while\r
- for (volatile size_t i=0; i<0x100000; i++);\r
-// SpinDelay(100);\r
\r
- // Reconnect USB reconnect\r
- AT91C_BASE_PIOA->PIO_SODR = GPIO_USB_PU;\r
- AT91C_BASE_PIOA->PIO_OER = GPIO_USB_PU;\r
+ // Disconnect and reconnect USB controller for 100ms\r
+ usb_disable();\r
+\r
+ // Wait for a short while\r
+ for (volatile size_t i=0; i<0x100000; i++);\r
+ //sleep(1);\r
+ \r
+ // Reconnect USB reconnect\r
+ AT91C_BASE_PIOA->PIO_SODR = GPIO_USB_PU;\r
+ AT91C_BASE_PIOA->PIO_OER = GPIO_USB_PU;\r
}\r
\r
//*----------------------------------------------------------------------------\r
return (pUdp->UDP_CSR[AT91C_EP_OUT] & btReceiveBank);\r
}\r
\r
+/**\r
+ In github PR #129, some users appears to get a false positive from\r
+ usb_poll, which returns true, but the usb_read operation\r
+ still returns 0.\r
+ This check is basically the same as above, but also checks\r
+ that the length available to read is non-zero, thus hopefully fixes the\r
+ bug.\r
+**/\r
+bool usb_poll_validate_length()\r
+{\r
+ if (!usb_check()) return false;\r
+ if (!(pUdp->UDP_CSR[AT91C_EP_OUT] & btReceiveBank)) return false;\r
+ return (pUdp->UDP_CSR[AT91C_EP_OUT] >> 16) > 0;\r
+}\r
+\r
//*----------------------------------------------------------------------------\r
//* \fn usb_read\r
//* \brief Read available data from Endpoint OUT\r
//*----------------------------------------------------------------------------\r
uint32_t usb_read(byte_t* data, size_t len) {\r
- byte_t bank = btReceiveBank;\r
+ byte_t bank = btReceiveBank;\r
uint32_t packetSize, nbBytesRcv = 0;\r
- uint32_t time_out = 0;\r
+ uint32_t time_out = 0;\r
\r
- while (len)\r
- {\r
+ while (len) {\r
if (!usb_check()) break;\r
\r
if ( pUdp->UDP_CSR[AT91C_EP_OUT] & bank ) {\r
packetSize = MIN(pUdp->UDP_CSR[AT91C_EP_OUT] >> 16, len);\r
- len -= packetSize;\r
+ len -= packetSize;\r
while(packetSize--)\r
data[nbBytesRcv++] = pUdp->UDP_FDR[AT91C_EP_OUT];\r
+ \r
pUdp->UDP_CSR[AT91C_EP_OUT] &= ~(bank);\r
+ \r
if (bank == AT91C_UDP_RX_DATA_BK0)\r
- {\r
bank = AT91C_UDP_RX_DATA_BK1;\r
- } else {\r
- bank = AT91C_UDP_RX_DATA_BK0;\r
- }\r
+ else\r
+ bank = AT91C_UDP_RX_DATA_BK0; \r
}\r
- if (time_out++ == 0x1fff) break;\r
+ if (time_out++ == 0x1fff) break;\r
}\r
\r
btReceiveBank = bank;\r
//* \brief Send through endpoint 2\r
//*----------------------------------------------------------------------------\r
uint32_t usb_write(const byte_t* data, const size_t len) {\r
- size_t length = len;\r
+ size_t length = len;\r
uint32_t cpt = 0;\r
\r
- if (!length) return 0;\r
- if (!usb_check()) return 0;\r
+ if (!length) return 0;\r
+ if (!usb_check()) return 0;\r
\r
// Send the first packet\r
cpt = MIN(length, AT91C_EP_IN_SIZE-1);\r
cpt = MIN(length, AT91C_EP_IN_SIZE-1);\r
length -= cpt;\r
while (cpt--) pUdp->UDP_FDR[AT91C_EP_IN] = *data++;\r
- // Wait for the the first bank to be sent\r
+ // Wait for the first bank to be sent\r
while (!(pUdp->UDP_CSR[AT91C_EP_IN] & AT91C_UDP_TXCOMP)) {\r
if (!usb_check()) return length;\r
- }\r
+ }\r
pUdp->UDP_CSR[AT91C_EP_IN] &= ~(AT91C_UDP_TXCOMP);\r
+ \r
while (pUdp->UDP_CSR[AT91C_EP_IN] & AT91C_UDP_TXCOMP);\r
+ \r
pUdp->UDP_CSR[AT91C_EP_IN] |= AT91C_UDP_TXPKTRDY;\r
}\r
\r
// Wait for the end of transfer\r
while (!(pUdp->UDP_CSR[AT91C_EP_IN] & AT91C_UDP_TXCOMP)) {\r
if (!usb_check()) return length;\r
- }\r
+ }\r
\r
pUdp->UDP_CSR[AT91C_EP_IN] &= ~(AT91C_UDP_TXCOMP);\r
while (pUdp->UDP_CSR[AT91C_EP_IN] & AT91C_UDP_TXCOMP);\r
//* \fn AT91F_USB_SendData\r
//* \brief Send Data through the control endpoint\r
//*----------------------------------------------------------------------------\r
-unsigned int csrTab[100];\r
+unsigned int csrTab[100] = {0x00};\r
unsigned char csrIdx = 0;\r
\r
static void AT91F_USB_SendData(AT91PS_UDP pUdp, const char *pData, uint32_t length) {\r
projects / proxmark3-svn / blobdiff