gcc10 compiler fixes:

[proxmark3-svn] / bootrom / ldscript-flash

diff --git a/bootrom/ldscript-flash b/bootrom/ldscript-flash
index 50218d684e5cefe5e12130cecd0863032e50bb69..f1bab1494e856cc81c28299efd101350452b0f2b 100644 (file)
--- a/bootrom/ldscript-flash
+++ b/bootrom/ldscript-flash
@@ -1,32 +1,63 @@
-INCLUDE ../common/ldscript.common\r
-\r
-ENTRY(flashstart)\r
-SECTIONS\r
-{\r
-    . = 0;\r
-    \r
-    bootphase1 : {\r
-       *(.startup) \r
-       *(.bootphase1)\r
-    } >bootphase1\r
-    \r
-    bootphase2 : {\r
-       __bootphase2_start__ = .;\r
-       *(.startphase2)\r
-       *(.text)\r
-       *(.glue_7)\r
-       *(.glue_7t)\r
-       *(.rodata)\r
-        *(.data)\r
-       . = ALIGN( 32 / 8 );\r
-       __bootphase2_end__ = .;\r
-    } >ram AT>bootphase2\r
-    \r
-    .bss : {\r
-       __bss_start__ = .; \r
-       *(.bss)\r
-    } >ram\r
-    \r
-    . = ALIGN( 32 / 8 );\r
-    __bss_end__ = .;\r
-}\r
+/*
+-----------------------------------------------------------------------------
+ This code is licensed to you under the terms of the GNU GPL, version 2 or,
+ at your option, any later version. See the LICENSE.txt file for the text of
+ the license.
+-----------------------------------------------------------------------------
+ Bootrom linker script
+-----------------------------------------------------------------------------
+*/
+
+INCLUDE ../common/ldscript.common
+
+PHDRS
+{
+       phase1 PT_LOAD;
+       phase2 PT_LOAD;
+       bss PT_LOAD;
+}
+
+ENTRY(flashstart)
+SECTIONS
+{
+       .bootphase1 : {
+               *(.startup)
+
+               . = ALIGN(4);
+               _version_information_start = .;
+               KEEP(*(.version_information));
+
+               . = LENGTH(bootphase1) - 0x4;
+               LONG(_version_information_start);
+       } >bootphase1 :phase1
+
+       .bootphase2 : {
+               *(.startphase2)
+               *(.text)
+               *(.text.*)
+               *(.eh_frame)
+               *(.glue_7)
+               *(.glue_7t)
+               *(.rodata)
+               *(.rodata.*)
+               *(.data)
+               *(.data.*)
+               . = ALIGN(4);
+       } >ram AT>bootphase2 :phase2
+
+       __bootphase2_src_start__ = LOADADDR(.bootphase2);
+       __bootphase2_start__ = ADDR(.bootphase2);
+       __bootphase2_end__ = __bootphase2_start__ + SIZEOF(.bootphase2);
+
+       .bss : {
+               __bss_start__ = .;
+               *(.bss)
+               *(.bss.*)
+               . = ALIGN(4);
+               __bss_end__ = .;
+       } >ram AT>ram :bss
+
+       .commonarea (NOLOAD) : {
+               *(.commonarea)
+       } >commonarea
+}