FIX: bug in nextwatch demod, which if the found psk bits was smaller than the preamb...

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 640809e068bd4719826fe2fc134a602d70f184be..b4d3dec5994eebaf50670291ce88a41e83d73fc9 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -8,13 +8,7 @@
 // Utility functions used in many places, not specific to any piece of code.
 //-----------------------------------------------------------------------------
 
 // Utility functions used in many places, not specific to any piece of code.
 //-----------------------------------------------------------------------------
 

-#include "proxmark3.h"

 #include "util.h"
 #include "util.h"

-#include "string.h"
-#include "apps.h"
-#include "BigBuf.h"
-
-

 
 void print_result(char *name, uint8_t *buf, size_t len) {
        uint8_t *p = buf;
 
 void print_result(char *name, uint8_t *buf, size_t len) {
        uint8_t *p = buf;


@@ -50,6 +44,23 @@ uint32_t SwapBits(uint32_t value, int nrbits) {
        return newvalue;
 }
 
        return newvalue;
 }
 

+/*
+ ref  http://www.csm.ornl.gov/~dunigan/crc.html
+ Returns the value v with the bottom b [0,32] bits reflected. 
+ Example: reflect(0x3e23L,3) == 0x3e26
+*/
+uint32_t reflect(uint32_t v, int b) {
+       uint32_t t = v;
+       for ( int i = 0; i < b; ++i) {
+               if (t & 1)
+                       v |=  BITMASK((b-1)-i);
+               else
+                       v &= ~BITMASK((b-1)-i);
+               t>>=1;
+       }
+       return v;
+}
+

 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) {
        while (len--) {
                dest[len] = (uint8_t) n;
 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest) {
        while (len--) {
                dest[len] = (uint8_t) n;


@@ -82,13 +93,11 @@ void lsl (uint8_t *data, size_t len) {
     data[len - 1] <<= 1;
 }
 
     data[len - 1] <<= 1;
 }
 

-int32_t le24toh (uint8_t data[3])
-{
+int32_t le24toh (uint8_t data[3]) {

     return (data[2] << 16) | (data[1] << 8) | data[0];
 }
 
     return (data[2] << 16) | (data[1] << 8) | data[0];
 }
 

-void LEDsoff()
-{
+void LEDsoff() {

        LED_A_OFF();
        LED_B_OFF();
        LED_C_OFF();
        LED_A_OFF();
        LED_B_OFF();
        LED_C_OFF();


@@ -96,8 +105,7 @@ void LEDsoff()
 }
 
 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 }
 
 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]

-void LED(int led, int ms)
-{
+void LED(int led, int ms) {

        if (led & LED_RED)
                LED_C_ON();
        if (led & LED_ORANGE)
        if (led & LED_RED)
                LED_C_ON();
        if (led & LED_ORANGE)


@@ -122,13 +130,11 @@ void LED(int led, int ms)
                LED_D_OFF();
 }
 
                LED_D_OFF();
 }
 

-

 // Determine if a button is double clicked, single clicked,
 // not clicked, or held down (for ms || 1sec)
 // In general, don't use this function unless you expect a
 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
 // Determine if a button is double clicked, single clicked,
 // not clicked, or held down (for ms || 1sec)
 // In general, don't use this function unless you expect a
 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead

-int BUTTON_CLICKED(int ms)
-{
+int BUTTON_CLICKED(int ms) {

        // Up to 500ms in between clicks to mean a double click
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 
        // Up to 500ms in between clicks to mean a double click
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 


@@ -190,8 +196,7 @@ int BUTTON_CLICKED(int ms)
 }
 
 // Determine if a button is held down
 }
 
 // Determine if a button is held down

-int BUTTON_HELD(int ms)
-{
+int BUTTON_HELD(int ms) {

        // If button is held for one second
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 
        // If button is held for one second
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 


@@ -230,8 +235,7 @@ int BUTTON_HELD(int ms)
 
 // attempt at high resolution microsecond timer
 // beware: timer counts in 21.3uS increments (1024/48Mhz)
 
 // attempt at high resolution microsecond timer
 // beware: timer counts in 21.3uS increments (1024/48Mhz)

-void SpinDelayUs(int us)
-{
+void SpinDelayUs(int us) {

        int ticks = (48*us) >> 10;
 
        // Borrow a PWM unit for my real-time clock
        int ticks = (48*us) >> 10;
 
        // Borrow a PWM unit for my real-time clock


@@ -252,8 +256,7 @@ void SpinDelayUs(int us)
        }
 }
 
        }
 }
 

-void SpinDelay(int ms)
-{
+void SpinDelay(int ms) {

   // convert to uS and call microsecond delay function
        SpinDelayUs(ms*1000);
 }
   // convert to uS and call microsecond delay function
        SpinDelayUs(ms*1000);
 }


@@ -263,8 +266,7 @@ void SpinDelay(int ms)
  * verifies the magic properties, then stores a formatted string, prefixed by
  * prefix in dst.
  */
  * verifies the magic properties, then stores a formatted string, prefixed by
  * prefix in dst.
  */

-void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information)
-{
+void FormatVersionInformation(char *dst, int len, const char *prefix, void *version_information) {

        struct version_information *v = (struct version_information*)version_information;
        dst[0] = 0;
        strncat(dst, prefix, len-1);
        struct version_information *v = (struct version_information*)version_information;
        dst[0] = 0;
        strncat(dst, prefix, len-1);


@@ -303,8 +305,7 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 //     ti = GetTickCount() - ti;
 //     Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
 
 //     ti = GetTickCount() - ti;
 //     Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
 

-void StartTickCount()
-{
+void StartTickCount() {

        // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
        // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
     uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;                // = 16 * main clock frequency (16MHz) / slow clock frequency
        // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
        // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
     uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;                // = 16 * main clock frequency (16MHz) / slow clock frequency


@@ -323,8 +324,7 @@ uint32_t RAMFUNC GetTickCount(){
 //  -------------------------------------------------------------------------
 //  microseconds timer 
 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------
 //  microseconds timer 
 //  -------------------------------------------------------------------------

-void StartCountUS()
-{
+void StartCountUS() {

        AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
 //     AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
        AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
 //     AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;


@@ -365,8 +365,7 @@ uint32_t RAMFUNC GetCountUS(){
 //  -------------------------------------------------------------------------
 //  Timer for iso14443 commands. Uses ssp_clk from FPGA 
 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------
 //  Timer for iso14443 commands. Uses ssp_clk from FPGA 
 //  -------------------------------------------------------------------------

-void StartCountSspClk()
-{
+void StartCountSspClk() {

        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
                                                        | AT91C_TCB_TC1XC1S_NONE                // XC1 Clock = none
        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
                                                        | AT91C_TCB_TC1XC1S_NONE                // XC1 Clock = none


@@ -400,17 +399,17 @@ void StartCountSspClk()
        AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP;                  // just count
        AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP;                  // just count

-       
-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
-       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2

 
 

-       //
-       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
-       //
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC0
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC1
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC2
+
+       // synchronize the counter with the ssp_frame signal. 
+       // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 

        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high

+

        // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
        AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
        // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
        AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)


@@ -418,9 +417,16 @@ void StartCountSspClk()
        // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
        // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
        // (just started with the transfer of the 4th Bit).
        // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
        // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
        // (just started with the transfer of the 4th Bit).

-       // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
-       // we can use the counter.
-       while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+
+       // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
+       // Therefore need to wait quite some time before we can use the counter.
+       while (AT91C_BASE_TC2->TC_CV >= 1);
+}
+void ResetSspClk(void) {       
+       //enable clock of timer and software trigger
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_SWTRG;

 }
 
 uint32_t RAMFUNC GetCountSspClk(){
 }
 
 uint32_t RAMFUNC GetCountSspClk(){