chg: uncomment -DWITH EMV to compile for EMV.

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index 28927c33b1357dedd62f88603550ed7b0b391c1e..3c69770e3bd69dcf39e2550bf98d3f381865274c 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -43,7 +43,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
        uint16_t period_0 =  periods >> 16;
        uint16_t period_1 =  periods & 0xFFFF;
        
        uint16_t period_0 =  periods >> 16;
        uint16_t period_1 =  periods & 0xFFFF;
        

-       // 95 == 125 KHz  88 == 124.8 KHz
+       // 95 == 125 KHz  88 == 134.8 KHz

        int divisor_used = (useHighFreq) ? 88 : 95;
        sample_config sc = { 0,0,1, divisor_used, 0};
        setSamplingConfig(&sc);
        int divisor_used = (useHighFreq) ? 88 : 95;
        sample_config sc = { 0,0,1, divisor_used, 0};
        setSamplingConfig(&sc);


@@ -78,6 +78,8 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
 
        // now do the read
        DoAcquisition_config(false);
 
        // now do the read
        DoAcquisition_config(false);

+       
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);

 }
 
 /* blank r/w tag data stream
 }
 
 /* blank r/w tag data stream


@@ -797,7 +799,7 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 

-               DoAcquisition_default(-1,true);
+               DoAcquisition_default(0, true);

                // FSK demodulator
                size = 50*128*2; //big enough to catch 2 sequences of largest format
                idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
                // FSK demodulator
                size = 50*128*2; //big enough to catch 2 sequences of largest format
                idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);


@@ -1738,45 +1740,59 @@ void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode
        LED_D_OFF();
 }
 
        LED_D_OFF();
 }
 

-void Cotag() {
+/*
+Reading a COTAG.

 
 

-#define WAIT2200       { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2200); }
+COTAG needs the reader to send a startsequence and the card has an extreme slow datarate.
+because of this, we can "sample" the data signal but we interpreate it to Manchester direct.

 
 

-       LED_A_ON();
-       
-       //clear buffer now so it does not interfere with timing later
-       BigBuf_Clear_keep_EM();
+READER START SEQUENCE:
+burst 800 us,    gap   2.2 msecs
+burst 3.6 msecs  gap   2.2 msecs
+burst 800 us     gap   2.2 msecs
+pulse 3.6 msecs

 
 

-       // Set up FPGA, 132kHz to power up the tag
+This triggers a COTAG tag to response
+*/
+void Cotag(uint32_t arg0) {
+
+#define OFF    { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); }
+#define ON(x)   { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); }
+
+       uint8_t rawsignal = arg0 & 0xF;
+
+       LED_A_ON();     
+
+       // Switching to LF image on FPGA. This might empty BigBuff

        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);

+       
+       //clear buffer now so it does not interfere with timing later
+       BigBuf_Clear_ext(false);
+       
+       // Set up FPGA, 132kHz to power up the tag      

        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
        
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
        // Connect the A/D to the peak-detected low-frequency path.
        SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
        

-       // 50ms for the resonant antenna to settle.
-       SpinDelay(50);
-       

        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();
        // Now set up the SSC to get the ADC samples that are now streaming at us.
        FpgaSetupSsc();

-       // start a 1.5ticks is 1us
+
+       // start clock - 1.5ticks is 1us

        StartTicks();
        
        StartTicks();
        

-       //send start pulse
-       TurnReadLFOn(800);
-       WAIT2200
-       TurnReadLFOn(3600);
-       WAIT2200
-       TurnReadLFOn(800);
-       WAIT2200
-       TurnReadLFOn(3600);     
-       
-       // Turn field on to read the response
-       TurnReadLFOn(READ_GAP);
-       
-       // Acquisition
-       doT55x7Acquisition(20000);
+       //send COTAG start pulse
+       ON(740)  OFF
+       ON(3330) OFF
+       ON(740)  OFF
+       ON(1000)
+
+       switch(rawsignal) {
+               case 0: doCotagAcquisition(50000); break;
+               case 1: doCotagAcquisitionManchester(); break;
+               case 2: DoAcquisition_config(TRUE); break;
+       }

        
        // Turn the field off
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
        
        // Turn the field off
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off