CHG: has the order of varibles some impact? I re-arranged them to match.

[proxmark3-svn] / fpga / hi_read_rx_xcorr.v

diff --git a/fpga/hi_read_rx_xcorr.v b/fpga/hi_read_rx_xcorr.v
index f816199e94d8d6c0f4f87dcd60cecb9742f80d1a..4eec0894d5b15257dd6f7d7a72627860ca24283e 100644 (file)
--- a/fpga/hi_read_rx_xcorr.v
+++ b/fpga/hi_read_rx_xcorr.v
@@ -15,9 +15,9 @@ module hi_read_rx_xcorr(
     input pck0, ck_1356meg, ck_1356megb;
     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
     input [7:0] adc_d;
-    output adc_clk;
+    output adc_clk, ssp_frame, ssp_din;
     input ssp_dout;
-    output ssp_frame, ssp_din, ssp_clk;
+    output ssp_clk;
     input cross_hi, cross_lo;
     output dbg;
     input xcorr_is_848, snoop;
@@ -88,7 +88,7 @@ begin
     // These are the correlators: we correlate against in-phase and quadrature
     // versions of our reference signal, and keep the (signed) result to
     // send out later over the SSP.
-    if(corr_i_cnt == 7'd0)
+    if(corr_i_cnt == 6'd0)
     begin
         if(snoop)
         begin
@@ -123,7 +123,7 @@ begin
 
     // The logic in hi_simulate.v reports 4 samples per bit. We report two
     // (I, Q) pairs per bit, so we should do 2 samples per pair.
-    if(corr_i_cnt == 6'd31)
+    if(corr_i_cnt == 6'd32)
         after_hysteresis_prev <= after_hysteresis;
 
     // Then the result from last time is serialized and send out to the ARM.