CHG: print_hex_break now prints rownumber instead of byte position

[proxmark3-svn] / armsrc / iclass.c

diff --git a/armsrc/iclass.c b/armsrc/iclass.c
index 7a68ea6bcbb478302cd05a10c2e874293dd6e2c3..dcb672e73515414d750155f215b2b866536b18e5 100644 (file)
--- a/armsrc/iclass.c
+++ b/armsrc/iclass.c
@@ -653,8 +653,9 @@ void RAMFUNC SnoopIClass(void)
     // The DMA buffer, used to stream samples from the FPGA
     uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
  
     // The DMA buffer, used to stream samples from the FPGA
     uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
  

-       set_tracing(TRUE);

        clear_trace();
        clear_trace();

+       set_tracing(TRUE);
+       

     iso14a_set_trigger(FALSE);
 
     int lastRxCounter;
     iso14a_set_trigger(FALSE);
 
     int lastRxCounter;


@@ -985,8 +986,9 @@ void SimulateIClass(uint32_t arg0, uint32_t arg1, uint32_t arg2, uint8_t *datain
        FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
 
        // Enable and clear the trace
        FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
 
        // Enable and clear the trace

-       set_tracing(TRUE);

        clear_trace();
        clear_trace();

+       set_tracing(TRUE);
+

        //Use the emulator memory for SIM
        uint8_t *emulator = BigBuf_get_EM_addr();
 
        //Use the emulator memory for SIM
        uint8_t *emulator = BigBuf_get_EM_addr();
 


@@ -1323,10 +1325,8 @@ int doIClassSimulation( int simulationMode, uint8_t *reader_mac_buf)
                                GetParity(trace_data, trace_data_size, parity);
                                LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
                        }
                                GetParity(trace_data, trace_data_size, parity);
                                LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
                        }

-                       if(!tracing) {
+                       if(!tracing)

                                DbpString("Trace full");
                                DbpString("Trace full");

-                               //break;
-                       }

 
                }
        }
 
                }
        }


@@ -1383,33 +1383,31 @@ static int SendIClassAnswer(uint8_t *resp, int respLen, int delay)
 //-----------------------------------------------------------------------------
 static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
 {
 //-----------------------------------------------------------------------------
 static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
 {

-  int c;
-  FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
-  AT91C_BASE_SSC->SSC_THR = 0x00;
-  FpgaSetupSsc();
-
-   if (wait)
-   {
-     if(*wait < 10) *wait = 10;
-     
-  for(c = 0; c < *wait;) {
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
-      AT91C_BASE_SSC->SSC_THR = 0x00;          // For exact timing!
-      c++;
-    }
-    if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
-      volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
-      (void)r;
-    }
-    WDT_HIT();
-  }
+       int c;
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
+       AT91C_BASE_SSC->SSC_THR = 0x00;
+       FpgaSetupSsc();
+
+       if (wait) {
+               if(*wait < 10) *wait = 10;

 
 

-   }
+               for(c = 0; c < *wait;) {
+                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+                               AT91C_BASE_SSC->SSC_THR = 0x00;         // For exact timing!
+                               c++;
+                       }
+                       if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+                               volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
+                               (void)r;
+                       }
+                       WDT_HIT();
+               }
+       }

 
 
 
 

-  uint8_t sendbyte;
-  bool firstpart = TRUE;
-  c = 0;
+       uint8_t sendbyte;
+       bool firstpart = TRUE;
+       c = 0;

   for(;;) {
     if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
 
   for(;;) {
     if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
 


@@ -1437,7 +1435,7 @@ static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int
     }
     WDT_HIT();
   }
     }
     WDT_HIT();
   }

-  if (samples) *samples = (c + *wait) << 3;
+  if (samples && wait) *samples = (c + *wait) << 3;

 }
 
 
 }
 
 


@@ -1570,9 +1568,9 @@ void setupIclassReader()
 {
     FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
     // Reset trace buffer
 {
     FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
     // Reset trace buffer

-       set_tracing(TRUE);

        clear_trace();
        clear_trace();

-
+       set_tracing(TRUE);
+       

     // Setup SSC
     FpgaSetupSsc();
     // Start from off (no field generated)
     // Setup SSC
     FpgaSetupSsc();
     // Start from off (no field generated)


@@ -1693,7 +1691,9 @@ void ReaderIClass(uint8_t arg0) {
     while(!BUTTON_PRESS())
     {
                if (try_once && tryCnt > 5) break; 
     while(!BUTTON_PRESS())
     {
                if (try_once && tryCnt > 5) break; 

+               

                tryCnt++;
                tryCnt++;

+               

                if(!tracing) {
                        DbpString("Trace full");
                        break;
                if(!tracing) {
                        DbpString("Trace full");
                        break;