More CRLF -> LF conversion

[proxmark3-svn] / fpga / hi_read_tx.v

diff --git a/fpga/hi_read_tx.v b/fpga/hi_read_tx.v
index c2cec3abed400c5150e944c6b1d39cb271c71f21..5ddc974daf9e54d860beece320554a94eb5e0c17 100644 (file)
--- a/fpga/hi_read_tx.v
+++ b/fpga/hi_read_tx.v
@@ -68,9 +68,22 @@ always @(negedge ssp_clk)
 \r
 assign ssp_frame = (hi_byte_div == 3'b000);\r
 \r
 \r
 assign ssp_frame = (hi_byte_div == 3'b000);\r
 \r

-assign ssp_din = 1'b0;\r
+// Implement a hysteresis to give out the received signal on\r
+// ssp_din. Sample at fc.\r
+assign adc_clk = ck_1356meg;\r
+\r
+// ADC data appears on the rising edge, so sample it on the falling edge\r
+reg after_hysteresis;\r
+always @(negedge adc_clk)\r
+begin\r
+    if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
+    else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
+end\r
+\r
+\r
+assign ssp_din = after_hysteresis;\r

 \r
 assign pwr_lo = 1'b0;\r
 \r
 assign pwr_lo = 1'b0;\r

-assign dbg = ssp_frame;\r
+assign dbg = ssp_din;\r

 \r
 endmodule\r
 \r
 endmodule\r