-//-----------------------------------------------------------------------------\r
-//\r
-// Jonathan Westhues, April 2006\r
-//-----------------------------------------------------------------------------\r
-\r
-module hi_read_rx_xcorr(\r
- pck0, ck_1356meg, ck_1356megb,\r
- pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,\r
- adc_d, adc_clk,\r
- ssp_frame, ssp_din, ssp_dout, ssp_clk,\r
- cross_hi, cross_lo,\r
- dbg,\r
- xcorr_is_848, snoop\r
-);\r
- input pck0, ck_1356meg, ck_1356megb;\r
- output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;\r
- input [7:0] adc_d;\r
- output adc_clk;\r
- input ssp_dout;\r
- output ssp_frame, ssp_din, ssp_clk;\r
- input cross_hi, cross_lo;\r
- output dbg;\r
- input xcorr_is_848, snoop;\r
-\r
-// Carrier is steady on through this, unless we're snooping.\r
-assign pwr_hi = ck_1356megb & (~snoop);\r
-assign pwr_oe1 = 1'b0;\r
-assign pwr_oe2 = 1'b0;\r
-assign pwr_oe3 = 1'b0;\r
-assign pwr_oe4 = 1'b0;\r
-\r
-reg ssp_clk;\r
-reg ssp_frame;\r
-\r
-reg fc_div_2;\r
-always @(posedge ck_1356meg)\r
- fc_div_2 = ~fc_div_2;\r
-\r
-reg adc_clk;\r
-\r
-always @(xcorr_is_848 or fc_div_2 or ck_1356meg)\r
- if(xcorr_is_848)\r
- // The subcarrier frequency is fc/16; we will sample at fc, so that \r
- // means the subcarrier is 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 ...\r
- adc_clk <= ck_1356meg;\r
- else\r
- // The subcarrier frequency is fc/32; we will sample at fc/2, and\r
- // the subcarrier will look identical.\r
- adc_clk <= fc_div_2;\r
-\r
-// When we're a reader, we just need to do the BPSK demod; but when we're an\r
-// eavesdropper, we also need to pick out the commands sent by the reader,\r
-// using AM. Do this the same way that we do it for the simulated tag.\r
-reg after_hysteresis, after_hysteresis_prev;\r
-reg [11:0] has_been_low_for;\r
-always @(negedge adc_clk)\r
-begin\r
- if(& adc_d[7:0]) after_hysteresis <= 1'b1;\r
- else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;\r
-\r
- if(after_hysteresis)\r
- begin\r
- has_been_low_for <= 7'b0;\r
- end\r
- else\r
- begin\r
- if(has_been_low_for == 12'd4095)\r
- begin\r
- has_been_low_for <= 12'd0;\r
- after_hysteresis <= 1'b1;\r
- end\r
- else\r
- has_been_low_for <= has_been_low_for + 1;\r
- end\r
-end\r
-\r
-// Let us report a correlation every 4 subcarrier cycles, or 4*16 samples,\r
-// so we need a 6-bit counter.\r
-reg [5:0] corr_i_cnt;\r
-reg [5:0] corr_q_cnt;\r
-// And a couple of registers in which to accumulate the correlations.\r
-reg signed [15:0] corr_i_accum;\r
-reg signed [15:0] corr_q_accum;\r
-reg signed [7:0] corr_i_out;\r
-reg signed [7:0] corr_q_out;\r
-\r
-// ADC data appears on the rising edge, so sample it on the falling edge\r
-always @(negedge adc_clk)\r
-begin\r
- // These are the correlators: we correlate against in-phase and quadrature\r
- // versions of our reference signal, and keep the (signed) result to\r
- // send out later over the SSP.\r
- if(corr_i_cnt == 7'd63)\r
- begin\r
- if(snoop)\r
- begin\r
- corr_i_out <= {corr_i_accum[12:6], after_hysteresis_prev};\r
- corr_q_out <= {corr_q_accum[12:6], after_hysteresis};\r
- end\r
- else\r
- begin\r
- // Only correlations need to be delivered.\r
- corr_i_out <= corr_i_accum[13:6];\r
- corr_q_out <= corr_q_accum[13:6];\r
- end\r
-\r
- corr_i_accum <= adc_d;\r
- corr_q_accum <= adc_d;\r
- corr_q_cnt <= 4;\r
- corr_i_cnt <= 0;\r
- end\r
- else\r
- begin\r
- if(corr_i_cnt[3])\r
- corr_i_accum <= corr_i_accum - adc_d;\r
- else\r
- corr_i_accum <= corr_i_accum + adc_d;\r
-\r
- if(corr_q_cnt[3])\r
- corr_q_accum <= corr_q_accum - adc_d;\r
- else\r
- corr_q_accum <= corr_q_accum + adc_d;\r
-\r
- corr_i_cnt <= corr_i_cnt + 1;\r
- corr_q_cnt <= corr_q_cnt + 1;\r
- end\r
-\r
- // The logic in hi_simulate.v reports 4 samples per bit. We report two\r
- // (I, Q) pairs per bit, so we should do 2 samples per pair.\r
- if(corr_i_cnt == 6'd31)\r
- after_hysteresis_prev <= after_hysteresis;\r
-\r
- // Then the result from last time is serialized and send out to the ARM.\r
- // We get one report each cycle, and each report is 16 bits, so the\r
- // ssp_clk should be the adc_clk divided by 64/16 = 4.\r
-\r
- if(corr_i_cnt[1:0] == 2'b10)\r
- ssp_clk <= 1'b0;\r
-\r
- if(corr_i_cnt[1:0] == 2'b00)\r
- begin\r
- ssp_clk <= 1'b1;\r
- // Don't shift if we just loaded new data, obviously.\r
- if(corr_i_cnt != 7'd0)\r
- begin\r
- corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};\r
- corr_q_out[7:1] <= corr_q_out[6:0];\r
- end\r
- end\r
-\r
- if(corr_i_cnt[5:2] == 4'b000 || corr_i_cnt[5:2] == 4'b1000)\r
- ssp_frame = 1'b1;\r
- else\r
- ssp_frame = 1'b0;\r
-\r
-end\r
-\r
-assign ssp_din = corr_i_out[7];\r
-\r
-assign dbg = corr_i_cnt[3];\r
-\r
-// Unused.\r
-assign pwr_lo = 1'b0;\r
-\r
-endmodule\r
+//-----------------------------------------------------------------------------
+//
+// Jonathan Westhues, April 2006
+//-----------------------------------------------------------------------------
+
+module hi_read_rx_xcorr(
+ pck0, ck_1356meg, ck_1356megb,
+ pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
+ adc_d, adc_clk,
+ ssp_frame, ssp_din, ssp_dout, ssp_clk,
+ cross_hi, cross_lo,
+ dbg,
+ xcorr_is_848, snoop, xcorr_quarter_freq
+);
+ input pck0, ck_1356meg, ck_1356megb;
+ output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
+ input [7:0] adc_d;
+ output adc_clk;
+ input ssp_dout;
+ output ssp_frame, ssp_din, ssp_clk;
+ input cross_hi, cross_lo;
+ output dbg;
+ input xcorr_is_848, snoop, xcorr_quarter_freq;
+
+// Carrier is steady on through this, unless we're snooping.
+assign pwr_hi = ck_1356megb & (~snoop);
+assign pwr_oe1 = 1'b0;
+assign pwr_oe3 = 1'b0;
+assign pwr_oe4 = 1'b0;
+
+reg [2:0] fc_div;
+always @(negedge ck_1356megb)
+ fc_div <= fc_div + 1;
+
+(* clock_signal = "yes" *) reg adc_clk; // sample frequency, always 16 * fc
+always @(ck_1356megb, xcorr_is_848, xcorr_quarter_freq, fc_div)
+ if (xcorr_is_848 & ~xcorr_quarter_freq) // fc = 847.5 kHz, standard ISO14443B
+ adc_clk <= ck_1356megb;
+ else if (~xcorr_is_848 & ~xcorr_quarter_freq) // fc = 423.75 kHz
+ adc_clk <= fc_div[0];
+ else if (xcorr_is_848 & xcorr_quarter_freq) // fc = 211.875 kHz
+ adc_clk <= fc_div[1];
+ else // fc = 105.9375 kHz
+ adc_clk <= fc_div[2];
+
+// When we're a reader, we just need to do the BPSK demod; but when we're an
+// eavesdropper, we also need to pick out the commands sent by the reader,
+// using AM. Do this the same way that we do it for the simulated tag.
+reg after_hysteresis, after_hysteresis_prev, after_hysteresis_prev_prev;
+reg [11:0] has_been_low_for;
+always @(negedge adc_clk)
+begin
+ if(& adc_d[7:0]) after_hysteresis <= 1'b1;
+ else if(~(| adc_d[7:0])) after_hysteresis <= 1'b0;
+
+ if(after_hysteresis)
+ begin
+ has_been_low_for <= 7'b0;
+ end
+ else
+ begin
+ if(has_been_low_for == 12'd4095)
+ begin
+ has_been_low_for <= 12'd0;
+ after_hysteresis <= 1'b1;
+ end
+ else
+ has_been_low_for <= has_been_low_for + 1;
+ end
+end
+
+// Let us report a correlation every 4 subcarrier cycles, or 4*16=64 samples,
+// so we need a 6-bit counter.
+reg [5:0] corr_i_cnt;
+// And a couple of registers in which to accumulate the correlations.
+// We would add at most 32 times the difference between unmodulated and modulated signal. It should
+// be safe to assume that a tag will not be able to modulate the carrier signal by more than 25%.
+// 32 * 255 * 0,25 = 2040, which can be held in 11 bits. Add 1 bit for sign.
+reg signed [11:0] corr_i_accum;
+reg signed [11:0] corr_q_accum;
+// we will report maximum 8 significant bits
+reg signed [7:0] corr_i_out;
+reg signed [7:0] corr_q_out;
+// clock and frame signal for communication to ARM
+reg ssp_clk;
+reg ssp_frame;
+
+
+always @(negedge adc_clk)
+begin
+ corr_i_cnt <= corr_i_cnt + 1;
+end
+
+
+// ADC data appears on the rising edge, so sample it on the falling edge
+always @(negedge adc_clk)
+begin
+ // These are the correlators: we correlate against in-phase and quadrature
+ // versions of our reference signal, and keep the (signed) result to
+ // send out later over the SSP.
+ if(corr_i_cnt == 6'd0)
+ begin
+ if(snoop)
+ begin
+ // Send 7 most significant bits of tag signal (signed), plus 1 bit reader signal
+ corr_i_out <= {corr_i_accum[11:5], after_hysteresis_prev_prev};
+ corr_q_out <= {corr_q_accum[11:5], after_hysteresis_prev};
+ after_hysteresis_prev_prev <= after_hysteresis;
+ end
+ else
+ begin
+ // 8 bits of tag signal
+ corr_i_out <= corr_i_accum[11:4];
+ corr_q_out <= corr_q_accum[11:4];
+ end
+
+ corr_i_accum <= adc_d;
+ corr_q_accum <= adc_d;
+ end
+ else
+ begin
+ if(corr_i_cnt[3])
+ corr_i_accum <= corr_i_accum - adc_d;
+ else
+ corr_i_accum <= corr_i_accum + adc_d;
+
+ if(corr_i_cnt[3] == corr_i_cnt[2]) // phase shifted by pi/2
+ corr_q_accum <= corr_q_accum + adc_d;
+ else
+ corr_q_accum <= corr_q_accum - adc_d;
+
+ end
+
+ // The logic in hi_simulate.v reports 4 samples per bit. We report two
+ // (I, Q) pairs per bit, so we should do 2 samples per pair.
+ if(corr_i_cnt == 6'd32)
+ after_hysteresis_prev <= after_hysteresis;
+
+ // Then the result from last time is serialized and send out to the ARM.
+ // We get one report each cycle, and each report is 16 bits, so the
+ // ssp_clk should be the adc_clk divided by 64/16 = 4.
+
+ if(corr_i_cnt[1:0] == 2'b10)
+ ssp_clk <= 1'b0;
+
+ if(corr_i_cnt[1:0] == 2'b00)
+ begin
+ ssp_clk <= 1'b1;
+ // Don't shift if we just loaded new data, obviously.
+ if(corr_i_cnt != 6'd0)
+ begin
+ corr_i_out[7:0] <= {corr_i_out[6:0], corr_q_out[7]};
+ corr_q_out[7:1] <= corr_q_out[6:0];
+ end
+ end
+
+ // set ssp_frame signal for corr_i_cnt = 0..3 and corr_i_cnt = 32..35
+ // (send two frames with 8 Bits each)
+ if(corr_i_cnt[5:2] == 4'b0000 || corr_i_cnt[5:2] == 4'b1000)
+ ssp_frame = 1'b1;
+ else
+ ssp_frame = 1'b0;
+
+end
+
+assign ssp_din = corr_i_out[7];
+
+assign dbg = corr_i_cnt[3];
+
+// Unused.
+assign pwr_lo = 1'b0;
+assign pwr_oe2 = 1'b0;
+
+endmodule
projects / proxmark3-svn / blobdiff