Added Enios cool tuning-trick (LF) from forum-post: http://www.proxmark.org/forum...

[proxmark3-svn] / fpga / fpga.ucf

diff --git a/fpga/fpga.ucf b/fpga/fpga.ucf
index bf0d40bc3786b40ca2f413027499afb6d1f8db9b..f20e2da0255f1357b48c7663f3aa606143d3b44a 100644 (file)
--- a/fpga/fpga.ucf
+++ b/fpga/fpga.ucf
@@ -1,41 +1,54 @@
-# See the schematic for the pin assignment.\r
-\r
-NET "adc_d<0>"  LOC = "P62"  ; \r
-NET "adc_d<1>"  LOC = "P60"  ; \r
-NET "adc_d<2>"  LOC = "P58"  ; \r
-NET "adc_d<3>"  LOC = "P57"  ; \r
-NET "adc_d<4>"  LOC = "P56"  ; \r
-NET "adc_d<5>"  LOC = "P55"  ; \r
-NET "adc_d<6>"  LOC = "P54"  ; \r
-NET "adc_d<7>"  LOC = "P53"  ; \r
-#NET "cross_hi"  LOC = "P88"  ; \r
-#NET "miso"  LOC = "P40"  ; \r
-#PACE: Start of Constraints generated by PACE\r
-\r
-#PACE: Start of PACE I/O Pin Assignments\r
-NET "adc_clk"  LOC = "P46"  ; \r
-NET "adc_noe"  LOC = "P47"  ; \r
-NET "ck_1356meg"  LOC = "P91"  ; \r
-NET "ck_1356megb"  LOC = "P93"  ; \r
-NET "cross_lo"  LOC = "P87"  ; \r
-NET "dbg"  LOC = "P22"  ; \r
-NET "mosi"  LOC = "P43"  ; \r
-NET "ncs"  LOC = "P44"  ; \r
-NET "pck0"  LOC = "P36"  ; \r
-NET "pwr_hi"  LOC = "P80"  ; \r
-NET "pwr_lo"  LOC = "P81"  ; \r
-NET "pwr_oe1"  LOC = "P82"  ; \r
-NET "pwr_oe2"  LOC = "P83"  ; \r
-NET "pwr_oe3"  LOC = "P84"  ; \r
-NET "pwr_oe4"  LOC = "P86"  ; \r
-NET "spck"  LOC = "P39"  ; \r
-NET "ssp_clk"  LOC = "P71"  ; \r
-NET "ssp_din"  LOC = "P32"  ; \r
-NET "ssp_dout"  LOC = "P34"  ; \r
-NET "ssp_frame"  LOC = "P31"  ; \r
-\r
-#PACE: Start of PACE Area Constraints\r
-\r
-#PACE: Start of PACE Prohibit Constraints\r
-\r
-#PACE: End of Constraints generated by PACE\r
+# See the schematic for the pin assignment.
+
+NET "adc_d<0>"  LOC = "P62"  ; 
+NET "adc_d<1>"  LOC = "P60"  ; 
+NET "adc_d<2>"  LOC = "P58"  ; 
+NET "adc_d<3>"  LOC = "P57"  ; 
+NET "adc_d<4>"  LOC = "P56"  ; 
+NET "adc_d<5>"  LOC = "P55"  ; 
+NET "adc_d<6>"  LOC = "P54"  ; 
+NET "adc_d<7>"  LOC = "P53"  ; 
+#NET "cross_hi"  LOC = "P88"  ; 
+#NET "miso"  LOC = "P40"  ; 
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_clk"  LOC = "P46"  ; 
+NET "adc_noe"  LOC = "P47"  ; 
+NET "ck_1356meg"  LOC = "P91"  ; 
+NET "ck_1356megb"  LOC = "P93"  ; 
+NET "cross_lo"  LOC = "P87"  ; 
+NET "dbg"  LOC = "P22"  ; 
+NET "mosi"  LOC = "P43"  ; 
+NET "ncs"  LOC = "P44"  ; 
+NET "pck0"  LOC = "P36"  ; 
+NET "pwr_hi"  LOC = "P80"  ; 
+NET "pwr_lo"  LOC = "P81"  ; 
+NET "pwr_oe1"  LOC = "P82"  ; 
+NET "pwr_oe2"  LOC = "P83"  ; 
+NET "pwr_oe3"  LOC = "P84"  ; 
+NET "pwr_oe4"  LOC = "P86"  ; 
+NET "spck"  LOC = "P39"  ; 
+NET "ssp_clk"  LOC = "P71"  ; 
+NET "ssp_din"  LOC = "P32"  ; 
+NET "ssp_dout"  LOC = "P34"  ; 
+NET "ssp_frame"  LOC = "P31"  ; 
+
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
+#PACE: End of Constraints generated by PACE
+
+# definition of Clock nets:
+NET "ck_1356meg" TNM_NET = "clk_net_1356" ;
+NET "ck_1356megb" TNM_NET = "clk_net_1356b" ;
+NET "pck0" TNM_NET = "clk_net_pck0" ;
+NET "spck" TNM_NET = "clk_net_spck" ;
+
+# Timing specs of clock nets:
+TIMEGRP "clk_net_1356_all" = "clk_net_1356" "clk_net_1356b" ;
+TIMESPEC "TS_1356MHz" = PERIOD "clk_net_1356_all" 74 ns HIGH 37 ns ;
+TIMESPEC "TS_24MHz" = PERIOD "clk_net_pck0" 42 ns HIGH 21 ns ;
+TIMESPEC "TS_4MHz" = PERIOD "clk_net_spck" 250 ns HIGH 125 ns ;
+