#include "protocols.h"
#include "optimized_cipher.h"
#include "usb_cdc.h" // for usb_poll_validate_length
+#include "fpgaloader.h"
static int timeout = 4096;
if(!Uart.bitBuffer) {
Uart.bitBuffer = bit ^ 0xFF0;
- return FALSE;
+ return false;
}
else {
Uart.bitBuffer <<= 4;
Uart.output[Uart.byteCnt] = Uart.bitBuffer & 0xFF;
Uart.byteCnt++;
Uart.swapper = 0;
- if(Uart.byteCnt > 15) { return TRUE; }
+ if(Uart.byteCnt > 15) { return true; }
}
else {
Uart.swapper = 1;
Uart.highCnt = 0;
if(Uart.byteCnt == 0) {
// Its not straightforward to show single EOFs
- // So just leave it and do not return TRUE
+ // So just leave it and do not return true
Uart.output[0] = 0xf0;
Uart.byteCnt++;
}
else {
- return TRUE;
+ return true;
}
}
else if(Uart.state != STATE_START_OF_COMMUNICATION) {
Uart.byteCnt++;
Uart.output[Uart.byteCnt] = 0xAA;
Uart.byteCnt++;
- return TRUE;
+ return true;
}*/
}
}
}
- return FALSE;
+ return false;
}
//=============================================================================
if(Demod.buff < 3) {
Demod.buff++;
- return FALSE;
+ return false;
}
if(Demod.state==DEMOD_UNSYNCD) {
Demod.len++;
Demod.state = DEMOD_UNSYNCD;
// error = 0x0f;
- return TRUE;
+ return true;
}
else {
Demod.state = DEMOD_ERROR_WAIT;
}
Demod.state = DEMOD_UNSYNCD;
- return TRUE;
+ return true;
}
else {
Demod.output[Demod.len] = 0xad;
Demod.len++;
Demod.output[Demod.len] = 0xBB;
Demod.len++;
- return TRUE;
+ return true;
}
}
} // end (state != UNSYNCED)
- return FALSE;
+ return false;
}
//=============================================================================
// We won't start recording the frames that we acquire until we trigger;
// a good trigger condition to get started is probably when we see a
// response from the tag.
- //int triggered = FALSE; // FALSE to wait first for card
+ //int triggered = false; // false to wait first for card
// The command (reader -> tag) that we're receiving.
// The length of a received command will in most cases be no more than 18 bytes.
// The DMA buffer, used to stream samples from the FPGA
uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
- set_tracing(TRUE);
+ set_tracing(true);
clear_trace();
- iso14a_set_trigger(FALSE);
+ iso14a_set_trigger(false);
int lastRxCounter;
uint8_t *upTo;
Demod.state = DEMOD_UNSYNCD;
// Setup for the DMA.
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
upTo = dmaBuf;
lastRxCounter = DMA_BUFFER_SIZE;
FpgaSetupSscDma((uint8_t *)dmaBuf, DMA_BUFFER_SIZE);
time_stop = (GetCountSspClk()-time_0) << 4;
LED_C_ON();
- //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,TRUE)) break;
- //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, TRUE)) break;
- if(tracing) {
- uint8_t parity[MAX_PARITY_SIZE];
- GetParity(Uart.output, Uart.byteCnt, parity);
- LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, TRUE);
- }
-
+ //if(!LogTrace(Uart.output,Uart.byteCnt, rsamples, Uart.parityBits,true)) break;
+ //if(!LogTrace(NULL, 0, Uart.endTime*16 - DELAY_READER_AIR2ARM_AS_SNIFFER, 0, true)) break;
+ uint8_t parity[MAX_PARITY_SIZE];
+ GetParity(Uart.output, Uart.byteCnt, parity);
+ LogTrace(Uart.output,Uart.byteCnt, time_start, time_stop, parity, true);
/* And ready to receive another command. */
Uart.state = STATE_UNSYNCD;
rsamples = samples - Demod.samples;
LED_B_ON();
- if(tracing) {
- uint8_t parity[MAX_PARITY_SIZE];
- GetParity(Demod.output, Demod.len, parity);
- LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, FALSE);
- }
+ uint8_t parity[MAX_PARITY_SIZE];
+ GetParity(Demod.output, Demod.len, parity);
+ LogTrace(Demod.output, Demod.len, time_start, time_stop, parity, false);
// And ready to receive another response.
memset(&Demod, 0, sizeof(Demod));
AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
Dbprintf("%x %x %x", maxBehindBy, Uart.state, Uart.byteCnt);
Dbprintf("%x %x %x", Uart.byteCntMax, BigBuf_get_traceLen(), (int)Uart.output[0]);
- LED_A_OFF();
- LED_B_OFF();
- LED_C_OFF();
- LED_D_OFF();
+ LEDsoff();
}
void rotateCSN(uint8_t* originalCSN, uint8_t* rotatedCSN) {
//-----------------------------------------------------------------------------
// Wait for commands from reader
// Stop when button is pressed
-// Or return TRUE when command is captured
+// Or return true when command is captured
//-----------------------------------------------------------------------------
static int GetIClassCommandFromReader(uint8_t *received, int *len, int maxLen)
{
for(;;) {
WDT_HIT();
- if(BUTTON_PRESS()) return FALSE;
+ if(BUTTON_PRESS()) return false;
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = 0x00;
if(OutOfNDecoding(b & 0x0f)) {
*len = Uart.byteCnt;
- return TRUE;
+ return true;
}
}
}
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
// Enable and clear the trace
- set_tracing(TRUE);
+ set_tracing(true);
clear_trace();
//Use the emulator memory for SIM
uint8_t *emulator = BigBuf_get_EM_addr();
StartCountSspClk();
// We need to listen to the high-frequency, peak-detected path.
SetAdcMuxFor(GPIO_MUXSEL_HIPKD);
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
// To control where we are in the protocol
int cmdsRecvd = 0;
t2r_time = GetCountSspClk();
}
- if (tracing) {
- uint8_t parity[MAX_PARITY_SIZE];
- GetParity(receivedCmd, len, parity);
- LogTrace(receivedCmd,len, (r2t_time-time_0)<< 4, (r2t_time-time_0) << 4, parity, TRUE);
-
- if (trace_data != NULL) {
- GetParity(trace_data, trace_data_size, parity);
- LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
- }
- if(!tracing) {
- DbpString("Trace full");
- //break;
- }
+ uint8_t parity[MAX_PARITY_SIZE];
+ GetParity(receivedCmd, len, parity);
+ LogTrace(receivedCmd,len, (r2t_time-time_0)<< 4, (r2t_time-time_0) << 4, parity, true);
+ if (trace_data != NULL) {
+ GetParity(trace_data, trace_data_size, parity);
+ LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, false);
+ }
+ if(!get_tracing()) {
+ DbpString("Trace full");
+ //break;
}
}
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR|FPGA_HF_SIMULATOR_MODULATE_424K_8BIT);
AT91C_BASE_SSC->SSC_THR = 0x00;
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_HF_SIMULATOR);
while(!BUTTON_PRESS()) {
if((AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)){
b = AT91C_BASE_SSC->SSC_RHR; (void) b;
int c;
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
AT91C_BASE_SSC->SSC_THR = 0x00;
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
if (wait)
{
uint8_t sendbyte;
- bool firstpart = TRUE;
+ bool firstpart = true;
c = 0;
for(;;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
LED_A_ON();
// Store reader command in buffer
- if (tracing) {
- uint8_t par[MAX_PARITY_SIZE];
- GetParity(frame, len, par);
- LogTrace(frame, len, rsamples, rsamples, par, TRUE);
- }
+ uint8_t par[MAX_PARITY_SIZE];
+ GetParity(frame, len, par);
+ LogTrace(frame, len, rsamples, rsamples, par, true);
}
//-----------------------------------------------------------------------------
// Wait a certain time for tag response
-// If a response is captured return TRUE
-// If it takes too long return FALSE
+// If a response is captured return true
+// If it takes too long return false
//-----------------------------------------------------------------------------
static int GetIClassAnswer(uint8_t *receivedResponse, int maxLen, int *samples, int *elapsed) //uint8_t *buffer
{
uint8_t b;
if (elapsed) *elapsed = 0;
- bool skip = FALSE;
+ bool skip = false;
c = 0;
for(;;) {
WDT_HIT();
- if(BUTTON_PRESS()) return FALSE;
+ if(BUTTON_PRESS()) return false;
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = 0x00; // To make use of exact timing of next command from reader!!
if (elapsed) (*elapsed)++;
}
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
- if(c < timeout) { c++; } else { return FALSE; }
+ if(c < timeout) { c++; } else { return false; }
b = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
skip = !skip;
if(skip) continue;
if(ManchesterDecoding(b & 0x0f)) {
*samples = c << 3;
- return TRUE;
+ return true;
}
}
}
int ReaderReceiveIClass(uint8_t* receivedAnswer)
{
int samples = 0;
- if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return FALSE;
+ if (!GetIClassAnswer(receivedAnswer,160,&samples,0)) return false;
rsamples += samples;
- if (tracing) {
- uint8_t parity[MAX_PARITY_SIZE];
- GetParity(receivedAnswer, Demod.len, parity);
- LogTrace(receivedAnswer,Demod.len,rsamples,rsamples,parity,FALSE);
- }
- if(samples == 0) return FALSE;
+ uint8_t parity[MAX_PARITY_SIZE];
+ GetParity(receivedAnswer, Demod.len, parity);
+ LogTrace(receivedAnswer,Demod.len,rsamples,rsamples,parity,false);
+ if(samples == 0) return false;
return Demod.len;
}
{
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
// Reset trace buffer
- set_tracing(TRUE);
+ set_tracing(true);
clear_trace();
// Setup SSC
- FpgaSetupSsc();
+ FpgaSetupSsc(FPGA_MAJOR_MODE_HF_ISO14443A);
// Start from off (no field generated)
// Signal field is off with the appropriate LED
LED_D_OFF();
// if only looking for one card try 2 times if we missed it the first time
if (try_once && tryCnt > 2) break;
tryCnt++;
- if(!tracing) {
+ if(!get_tracing()) {
DbpString("Trace full");
break;
}
uint8_t resp[ICLASS_BUFFER_SIZE];
setupIclassReader();
- set_tracing(TRUE);
+ set_tracing(true);
while(!BUTTON_PRESS()) {
WDT_HIT();
- if(!tracing) {
+ if(!get_tracing()) {
DbpString("Trace full");
break;
}
projects / proxmark3-svn / blobdiff