]> git.zerfleddert.de Git - proxmark3-svn/blobdiff - armsrc/lfops.c
syntax sugar
[proxmark3-svn] / armsrc / lfops.c
index 9290007cea43f7ad4eaa448249369f27251ac1e4..ffeb8ea12e76c2a6fec0019d61608b6da55ef179 100644 (file)
@@ -43,7 +43,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
        uint16_t period_0 =  periods >> 16;
        uint16_t period_1 =  periods & 0xFFFF;
        
-       // 95 == 125 KHz  88 == 124.8 KHz
+       // 95 == 125 KHz  88 == 134.8 KHz
        int divisor_used = (useHighFreq) ? 88 : 95;
        sample_config sc = { 0,0,1, divisor_used, 0};
        setSamplingConfig(&sc);
@@ -60,24 +60,26 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
        while(*command != '\0' && *command != ' ') {
                FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
                LED_D_OFF();
-               SpinDelayUs(delay_off);
+               WaitUS(delay_off);
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
 
                FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
                LED_D_ON();
                if(*(command++) == '0')
-                       SpinDelayUs(period_0);  // ICEMAN:  problem with (us) clock is  21.3us increments
+                       WaitUS(period_0);
                else
-                       SpinDelayUs(period_1);  // ICEMAN:  problem with (us) clock is  21.3us increments
+                       WaitUS(period_1);
        }
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_D_OFF();
-       SpinDelayUs(delay_off); // ICEMAN:  problem with (us) clock is  21.3us increments
+       WaitUS(delay_off);
        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
        // now do the read
        DoAcquisition_config(false);
+       
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 }
 
 /* blank r/w tag data stream
@@ -91,6 +93,7 @@ void ModThenAcquireRawAdcSamples125k(uint32_t delay_off, uint32_t periods, uint3
 */
 void ReadTItag(void)
 {
+       StartTicks();
        // some hardcoded initial params
        // when we read a TI tag we sample the zerocross line at 2Mhz
        // TI tags modulate a 1 as 16 cycles of 123.2Khz
@@ -216,6 +219,7 @@ void ReadTItag(void)
                        DbpString("Info: CRC is good");
                }
        }
+       StopTicks();
 }
 
 void WriteTIbyte(uint8_t b)
@@ -225,20 +229,20 @@ void WriteTIbyte(uint8_t b)
        // modulate 8 bits out to the antenna
        for (i=0; i<8; i++)
        {
-               if (b&(1<<i)) {
-                       // stop modulating antenna
+               if ( b & ( 1 << i ) ) {
+                       // stop modulating antenna 1ms
                        LOW(GPIO_SSC_DOUT);
-                       SpinDelayUs(1000);      // ICEMAN:  problem with (us) clock is  21.3us increments
-                       // modulate antenna
-                       HIGH(GPIO_SSC_DOUT);
-                       SpinDelayUs(1000);      // ICEMAN:  problem with (us) clock is  21.3us increments
+                       WaitUS(1000);
+                       // modulate antenna 1ms
+                       HIGH(GPIO_SSC_DOUT); 
+                       WaitUS(1000);
                } else {
-                       // stop modulating antenna
+                       // stop modulating antenna 1ms
                        LOW(GPIO_SSC_DOUT);
-                       SpinDelayUs(300);       // ICEMAN:  problem with (us) clock is  21.3us increments
-                       // modulate antenna
+                       WaitUS(300);
+                       // modulate antenna 1m
                        HIGH(GPIO_SSC_DOUT);
-                       SpinDelayUs(1700);      // ICEMAN:  problem with (us) clock is  21.3us increments
+                       WaitUS(1700);
                }
        }
 }
@@ -282,7 +286,7 @@ void AcquireTiType(void)
        HIGH(GPIO_SSC_DOUT);
 
        // Charge TI tag for 50ms.
-       SpinDelay(50);
+       WaitMS(50);
 
        // stop modulating antenna and listen
        LOW(GPIO_SSC_DOUT);
@@ -342,8 +346,10 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
        // whether we're modulating the antenna (high)
        // or listening to the antenna (low)
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
+       StartTicks();
+       
        LED_A_ON();
-
+       
        // steal this pin from the SSP and use it to control the modulation
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT;
        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
@@ -356,11 +362,11 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
        // then write 80 bits of data (or 64 bit data + 16 bit crc if you prefer)
        // finally end with 0x0300 (write frame)
        // all data is sent lsb first
-       // finish with 15ms programming time
+       // finish with 50ms programming time
 
        // modulate antenna
        HIGH(GPIO_SSC_DOUT);
-       SpinDelay(50);  // charge time
+       WaitMS(50);     // charge time
 
        WriteTIbyte(0xbb); // keyword
        WriteTIbyte(0xeb); // password
@@ -377,7 +383,7 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
        WriteTIbyte(0x00); // write frame lo
        WriteTIbyte(0x03); // write frame hi
        HIGH(GPIO_SSC_DOUT);
-       SpinDelay(50);  // programming time
+       WaitMS(50);     // programming time
 
        LED_A_OFF();
 
@@ -386,61 +392,82 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
 
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        DbpString("Now use `lf ti read` to check");
+       StopTicks();
 }
 
 void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
 {
        int i = 0;
-       uint8_t *tab = BigBuf_get_addr();
+       uint8_t *buf = BigBuf_get_addr();
 
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_PASSTHRU);
+       //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
+       //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_READER_FIELD);
+       //FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT | FPGA_LF_EDGE_DETECT_TOGGLE_MODE );
 
+       // set frequency,  get values from 'lf config' command
+       sample_config *sc = getSamplingConfig();
+
+       if ( (sc->divisor == 1) || (sc->divisor < 0) || (sc->divisor > 255) )
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
+       else if (sc->divisor == 0)
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       else
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc->divisor);
+       
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       
        AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DOUT | GPIO_SSC_CLK;
        AT91C_BASE_PIOA->PIO_OER = GPIO_SSC_DOUT;
        AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_CLK;
 
+       // power on antenna
+       OPEN_COIL();
+       // charge time
+       WaitMS(50);
+               
        for(;;) {
                WDT_HIT();
 
                if (ledcontrol) LED_D_ON();
                                
-               //wait until SSC_CLK goes HIGH
+               // wait until SSC_CLK goes HIGH
+               // used as a simple detection of a reader field?
                while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)) {
                        WDT_HIT();
-                       if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
-                               FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-                               LED_D_OFF();
-                               return;                         
-                       }
+                       if ( usb_poll_validate_length() || BUTTON_PRESS() )
+                               goto OUT;
                }
                
-               if(tab[i])
+               if(buf[i])
                        OPEN_COIL();
                else
                        SHORT_COIL();
-
-               if (ledcontrol) LED_D_OFF();
-               
+       
                //wait until SSC_CLK goes LOW
                while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK) {
                        WDT_HIT();
-                       if ( usb_poll_validate_length() || BUTTON_PRESS() ) {
-                               FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-                               LED_D_OFF();
-                               return;                         
-                       }
+                       if ( usb_poll_validate_length() || BUTTON_PRESS() )
+                               goto OUT;
                }
-
+                               
                i++;
                if(i == period) {
                        i = 0;
                        if (gap) {
                                WDT_HIT();
                                SHORT_COIL();
-                               SpinDelayUs(gap);       // ICEMAN:  problem with (us) clock is  21.3us increments
+                               SpinDelayUs(gap);
                        }
                }
+               
+               if (ledcontrol) LED_D_OFF();
        }
+OUT: 
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+       LED_D_OFF();
+       DbpString("Simulation stopped");
+       return; 
 }
 
 #define DEBUG_FRAME_CONTENTS 1
@@ -686,7 +713,7 @@ void CmdASKsimTag(uint16_t arg1, uint16_t arg2, size_t size, uint8_t *BitStream)
                for (i=0; i<size; i++){
                        askSimBit(BitStream[i]^invert, &n, clk, encoding);
                }
-               if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for biphase phase)
+               if (encoding==0 && BitStream[0]==BitStream[size-1]){ //run a second set inverted (for ask/raw || biphase phase)
                        for (i=0; i<size; i++){
                                askSimBit(BitStream[i]^invert^1, &n, clk, encoding);
                        }
@@ -775,7 +802,7 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                WDT_HIT();
                if (ledcontrol) LED_A_ON();
 
-               DoAcquisition_default(-1,true);
+               DoAcquisition_default(0, true);
                // FSK demodulator
                size = 50*128*2; //big enough to catch 2 sequences of largest format
                idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
@@ -843,13 +870,14 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                                if (ledcontrol) LED_A_OFF();
                                *high = hi;
                                *low = lo;
-                               return;
+                               break;
                        }
                        // reset
                }
                hi2 = hi = lo = idx = 0;
                WDT_HIT();
        }
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        DbpString("Stopped");
        if (ledcontrol) LED_A_OFF();
 }
@@ -946,13 +974,14 @@ void CmdAWIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
                                        }
                                        break;          
                        }
-                       if (findone){
-                               if (ledcontrol) LED_A_OFF();
-                               return;
-                       }
+                       if (findone)
+                               break;
+
                idx = 0;
                WDT_HIT();
        }
+
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); 
        DbpString("Stopped");
        if (ledcontrol) LED_A_OFF();
 }
@@ -986,7 +1015,7 @@ void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
        
                        errCnt = Em410xDecode(dest, &size, &idx, &hi, &lo);
                        if (errCnt){
-                               if (size>64){
+                               if (size == 128){
                                        Dbprintf("EM XL TAG ID: %06x%08x%08x - (%05d_%03d_%08d)",
                                          hi,
                                          (uint32_t)(lo>>32),
@@ -1007,13 +1036,14 @@ void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
                                if (ledcontrol) LED_A_OFF();
                                *high=lo>>32;
                                *low=lo & 0xFFFFFFFF;
-                               return;
+                               break;
                        }
                }
                WDT_HIT();
                hi = lo = size = idx = 0;
                clk = invert = errCnt = 0;
        }
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);         
        DbpString("Stopped");
        if (ledcontrol) LED_A_OFF();
 }
@@ -1063,15 +1093,15 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
                        // Checksum: 0x75
                        //XSF(version)facility:codeone+codetwo
                        //Handle the data
-                       if(findone){ //only print binary if we are doing one
-                               Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
-                               Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
-                               Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
-                               Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
-                               Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
-                               Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
-                               Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
-                       }
+                       // if(findone){ //only print binary if we are doing one
+                               // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx],   dest[idx+1],   dest[idx+2],dest[idx+3],dest[idx+4],dest[idx+5],dest[idx+6],dest[idx+7],dest[idx+8]);
+                               // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+9], dest[idx+10],dest[idx+11],dest[idx+12],dest[idx+13],dest[idx+14],dest[idx+15],dest[idx+16],dest[idx+17]);
+                               // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+18],dest[idx+19],dest[idx+20],dest[idx+21],dest[idx+22],dest[idx+23],dest[idx+24],dest[idx+25],dest[idx+26]);
+                               // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+27],dest[idx+28],dest[idx+29],dest[idx+30],dest[idx+31],dest[idx+32],dest[idx+33],dest[idx+34],dest[idx+35]);
+                               // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+36],dest[idx+37],dest[idx+38],dest[idx+39],dest[idx+40],dest[idx+41],dest[idx+42],dest[idx+43],dest[idx+44]);
+                               // Dbprintf("%d%d%d%d%d%d%d%d %d",dest[idx+45],dest[idx+46],dest[idx+47],dest[idx+48],dest[idx+49],dest[idx+50],dest[idx+51],dest[idx+52],dest[idx+53]);
+                               // Dbprintf("%d%d%d%d%d%d%d%d %d%d",dest[idx+54],dest[idx+55],dest[idx+56],dest[idx+57],dest[idx+58],dest[idx+59],dest[idx+60],dest[idx+61],dest[idx+62],dest[idx+63]);
+                       // }
                        code = bytebits_to_byte(dest+idx,32);
                        code2 = bytebits_to_byte(dest+idx+32,32);
                        version = bytebits_to_byte(dest+idx+27,8); //14,4
@@ -1092,7 +1122,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
                                if (ledcontrol) LED_A_OFF();
                                *high=code;
                                *low=code2;
-                               return;
+                               break;
                        }
                        code=code2=0;
                        version=facilitycode=0;
@@ -1101,6 +1131,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
                WDT_HIT();
        }
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);         
        DbpString("Stopped");
        if (ledcontrol) LED_A_OFF();
 }
@@ -1116,10 +1147,10 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
  * Q5 tags seems to have issues when these values changes. 
  */
 
-#define START_GAP 50*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (or 15fc)
-#define WRITE_GAP 20*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (or 10fc)
-#define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (or 24fc)
-#define WRITE_1   50*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (or 56fc)  432 for T55x7; 448 for E5550
+#define START_GAP 50*8 // was 250 // SPEC:  1*8 to 50*8 - typ 15*8 (15fc)
+#define WRITE_GAP 20*8 // was 160 // SPEC:  1*8 to 20*8 - typ 10*8 (10fc)
+#define WRITE_0   18*8 // was 144 // SPEC: 16*8 to 32*8 - typ 24*8 (24fc)
+#define WRITE_1   54*8 // was 400 // SPEC: 48*8 to 64*8 - typ 56*8 (56fc)  432 for T55x7; 448 for E5550
 #define READ_GAP  15*8 
 
 //  VALUES TAKEN FROM EM4x function: SendForward
@@ -1128,7 +1159,7 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 //  WRITE_1   = 256 32*8;  (32*8) 
 
 //  These timings work for 4469/4269/4305 (with the 55*8 above)
-//  WRITE_0 = 23*8 , 9*8  SpinDelayUs(23*8); 
+//  WRITE_0 = 23*8 , 9*8 
 
 // Sam7s has several timers, we will use the source TIMER_CLOCK1 (aka AT91C_TC_CLKS_TIMER_DIV1_CLOCK)
 // TIMER_CLOCK1 = MCK/2, MCK is running at 48 MHz, Timer is running at 48/2 = 24 MHz
@@ -1136,15 +1167,21 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 // T0 = TIMER_CLOCK1 / 125000 = 192
 // 1 Cycle = 8 microseconds(us)  == 1 field clock
 
-void TurnReadLFOn(int delay) {
+// new timer:
+//     = 1us = 1.5ticks
+// 1fc = 8us = 12ticks
+void TurnReadLFOn(uint32_t delay) {
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
-       // Give it a bit of time for the resonant antenna to settle.
 
        // measure antenna strength.
        //int adcval = ((MAX_ADC_LF_VOLTAGE * AvgAdc(ADC_CHAN_LF)) >> 10);
-       // where to save it
-       
-       SpinDelayCountUs(delay);        // ICEMAN:  problem with (us) clock is  21.3us increments
+
+       // Give it a bit of time for the resonant antenna to settle.
+       WaitUS(delay);
+}
+void TurnReadLF_off(uint32_t delay) {
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+       WaitUS(delay);
 }
 
 // Write one bit to card
@@ -1154,7 +1191,7 @@ void T55xxWriteBit(int bit) {
        else
                TurnReadLFOn(WRITE_1);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-       SpinDelayCountUs(WRITE_GAP);    // ICEMAN:  problem with (us) clock is  21.3us increments
+       WaitUS(WRITE_GAP);
 }
 
 // Send T5577 reset command then read stream (see if we can identify the start of the stream)
@@ -1168,7 +1205,7 @@ void T55xxResetRead(void) {
 
        // Trigger T55x7 in mode.
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-       SpinDelayCountUs(START_GAP);    // ICEMAN:  problem with (us) clock is  21.3us increments
+       WaitUS(START_GAP);
 
        // reset tag - op code 00
        T55xxWriteBit(0);
@@ -1198,7 +1235,7 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
        
        // Trigger T55x7 in mode.
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-       SpinDelayCountUs(START_GAP);    // ICEMAN:  problem with (us) clock is  21.3us increments
+       WaitUS(START_GAP);
 
        // Opcode 10
        T55xxWriteBit(1);
@@ -1222,10 +1259,11 @@ void T55xxWriteBlockExt(uint32_t Data, uint8_t Block, uint32_t Pwd, uint8_t arg)
        // Perform write (nominal is 5.6 ms for T55x7 and 18ms for E5550,
        // so wait a little more)
        TurnReadLFOn(20 * 1000);
-               //could attempt to do a read to confirm write took
-               // as the tag should repeat back the new block 
-               // until it is reset, but to confirm it we would 
-               // need to know the current block 0 config mode
+       
+       //could attempt to do a read to confirm write took
+       // as the tag should repeat back the new block 
+       // until it is reset, but to confirm it we would 
+       // need to know the current block 0 config mode
        
        // turn field off
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
@@ -1254,11 +1292,11 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
 
        // Set up FPGA, 125kHz to power up the tag
        LFSetupFPGAForADC(95, true);
-       SpinDelay(3);
+       //SpinDelay(3);
        
        // Trigger T55x7 Direct Access Mode with start gap
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-       SpinDelayCountUs(START_GAP);    // ICEMAN:  problem with (us) clock is  21.3us increments
+       WaitUS(START_GAP);
        
        // Opcode 1[page]
        T55xxWriteBit(1);
@@ -1281,7 +1319,7 @@ void T55xxReadBlock(uint16_t arg0, uint8_t Block, uint32_t Pwd) {
        TurnReadLFOn(READ_GAP);
        
        // Acquisition
-       doT55x7Acquisition(12000);
+       doT55x7Acquisition(7679);
        
        // Turn the field off
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
@@ -1298,7 +1336,7 @@ void T55xxWakeUp(uint32_t Pwd){
        
        // Trigger T55x7 Direct Access Mode
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-       SpinDelayCountUs(START_GAP);    // ICEMAN:  problem with (us) clock is  21.3us increments
+       WaitUS(START_GAP);
        
        // Opcode 10
        T55xxWriteBit(1);
@@ -1340,7 +1378,7 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
                data[4] = manchesterEncode2Bytes(hi & 0xFFFF);
                data[5] = manchesterEncode2Bytes(lo >> 16);
                data[6] = manchesterEncode2Bytes(lo & 0xFFFF);
-       }       else {
+       } else {
                // Ensure no more than 44 bits supplied
                if (hi > 0xFFF) {
                        DbpString("Tags can only have 44 bits.");
@@ -1357,30 +1395,24 @@ void CopyHIDtoT55x7(uint32_t hi2, uint32_t hi, uint32_t lo, uint8_t longFMT) {
        data[0] = T55x7_BITRATE_RF_50 | T55x7_MODULATION_FSK2a | last_block << T55x7_MAXBLOCK_SHIFT;
 
        //TODO add selection of chip for Q5 or T55x7
-       // data[0] = (((50-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
+       // data[0] = (((50-2)>>1)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | last_block << T5555_MAXBLOCK_SHIFT;
 
        LED_D_ON();
-       // Program the data blocks for supplied ID
-       // and the block 0 for HID format
        WriteT55xx(data, 0, last_block+1);
-
        LED_D_OFF();
-
-       DbpString("DONE!");
 }
 
 void CopyIOtoT55x7(uint32_t hi, uint32_t lo) {
        uint32_t data[] = {T55x7_BITRATE_RF_64 | T55x7_MODULATION_FSK2a | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
        //TODO add selection of chip for Q5 or T55x7
        //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
-       // data[0] = (64 << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
+       // data[0] = ( ((64-2)>>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_FSK2 | T5555_INVERT_OUTPUT | 2 << T5555_MAXBLOCK_SHIFT;
 
        LED_D_ON();
        // Program the data blocks for supplied ID
        // and the block 0 config
        WriteT55xx(data, 0, 3);
        LED_D_OFF();
-       DbpString("DONE!");
 }
 
 // Clone Indala 64-bit tag by UID to T55x7
@@ -1389,12 +1421,11 @@ void CopyIndala64toT55x7(uint32_t hi, uint32_t lo) {
        // and the Config for Indala 64 format (RF/32;PSK1 with RF/2;Maxblock=2)
        uint32_t data[] = { T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (2 << T55x7_MAXBLOCK_SHIFT), hi, lo};
        //TODO add selection of chip for Q5 or T55x7
-       // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
+       // data[0] = (((32-2)>>1)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 2 << T5555_MAXBLOCK_SHIFT;
 
        WriteT55xx(data, 0, 3);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=2;Inverse data)
        //      T5567WriteBlock(0x603E1042,0);
-       DbpString("DONE!");
 }
 // Clone Indala 224-bit tag by UID to T55x7
 void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t uid4, uint32_t uid5, uint32_t uid6, uint32_t uid7) {
@@ -1404,17 +1435,16 @@ void CopyIndala224toT55x7(uint32_t uid1, uint32_t uid2, uint32_t uid3, uint32_t
        //Config for Indala (RF/32;PSK1 with RF/2;Maxblock=7)
        data[0] = T55x7_BITRATE_RF_32 | T55x7_MODULATION_PSK1 | (7 << T55x7_MAXBLOCK_SHIFT);
        //TODO add selection of chip for Q5 or T55x7
-       // data[0] = (((32-2)/2)<<T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
+       // data[0] = (((32-2)>>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_PSK1 | 7 << T5555_MAXBLOCK_SHIFT;
        WriteT55xx(data, 0, 8);
        //Alternative config for Indala (Extended mode;RF/32;PSK1 with RF/2;Maxblock=7;Inverse data)
        //      T5567WriteBlock(0x603E10E2,0);
-       DbpString("DONE!");
 }
 // clone viking tag to T55xx
 void CopyVikingtoT55xx(uint32_t block1, uint32_t block2, uint8_t Q5) {
        uint32_t data[] = {T55x7_BITRATE_RF_32 | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT), block1, block2};
        //t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
-       if (Q5) data[0] = (32 << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
+       if (Q5) data[0] = (((32-2)>>1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | 2 << T5555_MAXBLOCK_SHIFT;
        // Program the data blocks for supplied ID and the block 0 config
        WriteT55xx(data, 0, 3);
        LED_D_OFF();
@@ -1498,8 +1528,8 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
                }
                data[0] = clock | T55x7_MODULATION_MANCHESTER | (2 << T55x7_MAXBLOCK_SHIFT);
        } else { //t5555 (Q5)
-               clock = (clock-2)>>1;  //n = (RF-2)/2
-               data[0] = (clock << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
+               // t5555 (Q5) BITRATE = (RF-2)/2 (iceman)
+               data[0] = ( ((clock-2) >> 1) << T5555_BITRATE_SHIFT) | T5555_MODULATION_MANCHESTER | (2 << T5555_MAXBLOCK_SHIFT);
        }
  
        WriteT55xx(data, 0, 3);
@@ -1514,9 +1544,11 @@ void WriteEM410x(uint32_t card, uint32_t id_hi, uint32_t id_lo) {
 //-----------------------------------
 // EM4469 / EM4305 routines
 //-----------------------------------
-#define FWD_CMD_LOGIN 0xC //including the even parity, binary mirrored
-#define FWD_CMD_WRITE 0xA
-#define FWD_CMD_READ 0x9
+// Below given command set. 
+// Commands are including the even parity, binary mirrored
+#define FWD_CMD_LOGIN   0xC 
+#define FWD_CMD_WRITE   0xA
+#define FWD_CMD_READ    0x9
 #define FWD_CMD_DISABLE 0x5
 
 uint8_t forwardLink_data[64]; //array of forwarded bits
@@ -1535,7 +1567,7 @@ uint8_t * fwd_write_ptr; //forwardlink bit pointer
 //  WRITE_1   = 256 32*8;  (32*8) 
 
 //  These timings work for 4469/4269/4305 (with the 55*8 above)
-//  WRITE_0 = 23*8 , 9*8  SpinDelayUs(23*8); 
+//  WRITE_0 = 23*8 , 9*8
 
 uint8_t Prepare_Cmd( uint8_t cmd ) {
 
@@ -1563,7 +1595,7 @@ uint8_t Prepare_Addr( uint8_t addr ) {
 
        uint8_t i;
        line_parity = 0;
-       for(i=0;i<6;i++) {
+       for( i=0; i<6; i++ ) {
                *forward_ptr++ = addr;
                line_parity ^= addr;
                addr >>= 1;
@@ -1617,108 +1649,180 @@ uint8_t Prepare_Data( uint16_t data_low, uint16_t data_hi) {
 //====================================================================
 void SendForward(uint8_t fwd_bit_count) {
 
+// iceman,   21.3us increments for the USclock verification.
+// 55FC * 8us == 440us / 21.3 === 20.65 steps.  could be too short. Go for 56FC instead
+// 32FC * 8us == 256us / 21.3 ==  12.018 steps. ok
+// 16FC * 8us == 128us / 21.3 ==  6.009 steps. ok 
+#ifndef EM_START_GAP
+#define EM_START_GAP 55*8
+#endif
+
        fwd_write_ptr = forwardLink_data;
        fwd_bit_sz = fwd_bit_count;
 
-       LED_D_ON();
-
        // Set up FPGA, 125kHz
        LFSetupFPGAForADC(95, true);
        
        // force 1st mod pulse (start gap must be longer for 4305)
        fwd_bit_sz--; //prepare next bit modulation
        fwd_write_ptr++;
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-       SpinDelayUs(55*8); //55 cycles off (8us each)for 4305   // ICEMAN:  problem with (us) clock is  21.3us increments
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-       SpinDelayUs(16*8); //16 cycles on (8us each)    // ICEMAN:  problem with (us) clock is  21.3us increments
+       
+       TurnReadLF_off(EM_START_GAP);
+       TurnReadLFOn(18*8);
 
-       // now start writting
+       // now start writting with bitbanging the antenna.
        while(fwd_bit_sz-- > 0) { //prepare next bit modulation
-               if(((*fwd_write_ptr++) & 1) == 1)
-                       SpinDelayUs(32*8); //32 cycles at 125Khz (8us each)     // ICEMAN:  problem with (us) clock is  21.3us increments
-               else {
-                       //These timings work for 4469/4269/4305 (with the 55*8 above)
-                       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-                       SpinDelayUs(23*8); //16-4 cycles off (8us each) // ICEMAN:  problem with (us) clock is  21.3us increments
-                       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);//field on
-                       SpinDelayUs(9*8); //16 cycles on (8us each)     // ICEMAN:  problem with (us) clock is  21.3us increments
+               if(((*fwd_write_ptr++) & 1) == 1) {
+                       WaitUS(32);
+               } else {
+                       TurnReadLF_off(23*8);
+                       TurnReadLFOn(16*8);
                }
        }
 }
 
-void EM4xLogin(uint32_t Password) {
+void EM4xLogin(uint32_t pwd) {
+       uint8_t len;
+       forward_ptr = forwardLink_data;
+       len = Prepare_Cmd( FWD_CMD_LOGIN );
+       len += Prepare_Data( pwd & 0xFFFF, pwd >> 16 );
+       SendForward(len);
+       //WaitUS(20); // no wait for login command.
+       // should receive
+       // 0000 1010 ok.
+       // 0000 0001 fail
+}
 
-       uint8_t fwd_bit_count;
+void EM4xReadWord(uint8_t addr, uint32_t pwd, uint8_t usepwd) {
+
+       LED_A_ON();
+       uint8_t len;
+       
+       //clear buffer now so it does not interfere with timing later
+       BigBuf_Clear_ext(false);
+       
+       /* should we read answer from Logincommand?
+       *
+       * should receive
+       * 0000 1010 ok.
+       * 0000 0001 fail
+       **/
+       if (usepwd) EM4xLogin(pwd);
 
        forward_ptr = forwardLink_data;
-       fwd_bit_count = Prepare_Cmd( FWD_CMD_LOGIN );
-       fwd_bit_count += Prepare_Data( Password&0xFFFF, Password>>16 );
+       len = Prepare_Cmd( FWD_CMD_READ );
+       len += Prepare_Addr( addr );
 
-       SendForward(fwd_bit_count);
+       SendForward(len);
 
-       //Wait for command to complete
-       SpinDelay(20);
-}
+       WaitUS(400);
 
-void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
+       DoPartialAcquisition(20, true, 6000);
 
-       uint8_t fwd_bit_count;
-       uint8_t *dest = BigBuf_get_addr();
-       uint16_t bufsize = BigBuf_max_traceLen();
-       uint32_t i = 0;
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+       cmd_send(CMD_ACK,0,0,0,0,0);
+       LED_A_OFF();
+}
 
-       // Clear destination buffer before sending the command
-       BigBuf_Clear_ext(false);
+void EM4xWriteWord(uint32_t flag, uint32_t data, uint32_t pwd) {
+
+       LED_A_ON();
+       
+       bool usePwd = (flag & 0xF);
+       uint8_t addr = (flag >> 8) & 0xFF;
+       uint8_t len;
        
-       //If password mode do login
-       if (PwdMode == 1) EM4xLogin(Pwd);
+       //clear buffer now so it does not interfere with timing later
+       BigBuf_Clear_ext(false);
 
-       forward_ptr = forwardLink_data;
-       fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
-       fwd_bit_count += Prepare_Addr( Address );
+       /* should we read answer from Logincommand?
+       *
+       * should receive
+       * 0000 1010 ok.
+       * 0000 0001 fail
+       **/     
+       if (usePwd) EM4xLogin(pwd);
 
-       // Connect the A/D to the peak-detected low-frequency path.
-       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-       // Now set up the SSC to get the ADC samples that are now streaming at us.
-       FpgaSetupSsc();
+       forward_ptr = forwardLink_data;
+       len = Prepare_Cmd( FWD_CMD_WRITE );
+       len += Prepare_Addr( addr );
+       len += Prepare_Data( data & 0xFFFF, data >> 16 );
 
-       SendForward(fwd_bit_count);
+       SendForward(len);
 
-       // Now do the acquisition
-       i = 0;
-       for(;;) {
-               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
-                       AT91C_BASE_SSC->SSC_THR = 0x43;
-               }
-               if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
-                       dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-                       ++i;
-                       if (i >= bufsize) break;
-               }
-       }
+       //Wait 20ms for write to complete?
+       WaitMS(7);
 
-       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off    
+       //Capture response if one exists
+       DoPartialAcquisition(20, true, 6000);
+       
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        cmd_send(CMD_ACK,0,0,0,0,0);
-       LED_D_OFF();
+       LED_A_OFF();
 }
 
-void EM4xWriteWord(uint32_t Data, uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
+/*
+Reading a COTAG.
 
-       uint8_t fwd_bit_count;
+COTAG needs the reader to send a startsequence and the card has an extreme slow datarate.
+because of this, we can "sample" the data signal but we interpreate it to Manchester direct.
 
-       //If password mode do login
-       if (PwdMode == 1) EM4xLogin(Pwd);
+READER START SEQUENCE:
+burst 800 us,    gap   2.2 msecs
+burst 3.6 msecs  gap   2.2 msecs
+burst 800 us     gap   2.2 msecs
+pulse 3.6 msecs
 
-       forward_ptr = forwardLink_data;
-       fwd_bit_count = Prepare_Cmd( FWD_CMD_WRITE );
-       fwd_bit_count += Prepare_Addr( Address );
-       fwd_bit_count += Prepare_Data( Data&0xFFFF, Data>>16 );
+This triggers a COTAG tag to response
+*/
+void Cotag(uint32_t arg0) {
+#ifndef OFF
+# define OFF   { FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); WaitUS(2035); }
+#endif
+#ifndef ON
+# define ON(x)   { FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD); WaitUS((x)); }
+#endif
+       uint8_t rawsignal = arg0 & 0xF;
+
+       LED_A_ON();     
+
+       // Switching to LF image on FPGA. This might empty BigBuff
+       FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+       
+       //clear buffer now so it does not interfere with timing later
+       BigBuf_Clear_ext(false);
+       
+       // Set up FPGA, 132kHz to power up the tag      
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 89);
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
-       SendForward(fwd_bit_count);
+       // Connect the A/D to the peak-detected low-frequency path.
+       SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
+       
+       // Now set up the SSC to get the ADC samples that are now streaming at us.
+       FpgaSetupSsc();
 
-       //Wait for write to complete
-       SpinDelay(20);
+       // start clock - 1.5ticks is 1us
+       StartTicks();
+       
+       //send COTAG start pulse
+       ON(740)  OFF
+       ON(3330) OFF
+       ON(740)  OFF
+       ON(1000)
+
+       switch(rawsignal) {
+               case 0: doCotagAcquisition(50000); break;
+               case 1: doCotagAcquisitionManchester(); break;
+               case 2: DoAcquisition_config(TRUE); break;
+       }
+       
+       // Turn the field off
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
-       LED_D_OFF();
+       cmd_send(CMD_ACK,0,0,0,0,0);    
+       LED_A_OFF();
 }
+
+/*
+* EM4305 support
+*/
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