StartCountSspClk();
- volatile uint8_t b;
+ volatile uint8_t b = 0;
// clear receiving shift register and holding register
// What does this loop do? Is it TR1?
// Now run a `software UART' on the stream of incoming samples.
UartInit(received);
- b = 0;
uint8_t mask;
while( !BUTTON_PRESS() ) {
WDT_HIT();
volatile uint8_t b;
// clear receiving shift register and holding register
- while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
b = AT91C_BASE_SSC->SSC_RHR; (void) b;
- while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
b = AT91C_BASE_SSC->SSC_RHR; (void) b;
if (triggered)
LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
- /* And ready to receive another command. */
- UartReset();
- /* And also reset the demod code, which might have been */
- /* false-triggered by the commands from the reader. */
- DemodReset();
+ /* And ready to receive another command. */
+ UartReset();
+ /* And also reset the demod code, which might have been */
+ /* false-triggered by the commands from the reader. */
+ DemodReset();
} else {
time_start = GetCountSspClk() - time_0;
}
//FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
}
-}
+}
\ No newline at end of file