some cards need to have Le=0x00, some need to not have... (#651)

[proxmark3-svn] / fpga / lo_read.v

diff --git a/fpga/lo_read.v b/fpga/lo_read.v
index f2d79127c2b90ae5d5df78d193305496866dd061..a6d077b99697ea4d597c02975b53885df69490ab 100644 (file)
--- a/fpga/lo_read.v
+++ b/fpga/lo_read.v
@@ -4,6 +4,7 @@
 // The A/D samples at that same rate and the result is serialized.
 //
 // Jonathan Westhues, April 2006
 // The A/D samples at that same rate and the result is serialized.
 //
 // Jonathan Westhues, April 2006

+// iZsh <izsh at fail0verflow.com>, June 2014

 //-----------------------------------------------------------------------------
 
 module lo_read(
 //-----------------------------------------------------------------------------
 
 module lo_read(


@@ -12,7 +13,8 @@ module lo_read(
        output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
        input [7:0] adc_d, output adc_clk,
        output ssp_frame, output ssp_din, output ssp_clk,
        output pwr_oe1, output pwr_oe2, output pwr_oe3, output pwr_oe4,
        input [7:0] adc_d, output adc_clk,
        output ssp_frame, output ssp_din, output ssp_clk,

-       output dbg
+       output dbg,
+       input lf_field

 );
 
 reg [7:0] to_arm_shiftreg;
 );
 
 reg [7:0] to_arm_shiftreg;


@@ -64,7 +66,7 @@ assign pwr_oe2 = 1'b0;
 assign pwr_oe3 = 1'b0;
 assign pwr_oe4 = 1'b0;
 // this is the antenna driver signal
 assign pwr_oe3 = 1'b0;
 assign pwr_oe4 = 1'b0;
 // this is the antenna driver signal

-assign pwr_lo = pck_divclk;
+assign pwr_lo = lf_field & pck_divclk;

 // ADC clock out of phase with antenna driver
 assign adc_clk = ~pck_divclk;
 // ADC clock also routed to debug pin
 // ADC clock out of phase with antenna driver
 assign adc_clk = ~pck_divclk;
 // ADC clock also routed to debug pin