Add string.h

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 4948fce8f8a19146436d220f8aa5475335736f6c..b0cd181824a977e0ffa2410c68ba65cb521db275 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -14,7 +14,6 @@
 #include "apps.h"
 #include "BigBuf.h"
 
 #include "apps.h"
 #include "BigBuf.h"
 

-int tracing = TRUE;

 
 
 void print_result(char *name, uint8_t *buf, size_t len) {
 
 
 void print_result(char *name, uint8_t *buf, size_t len) {


@@ -22,7 +21,7 @@ void print_result(char *name, uint8_t *buf, size_t len) {
 
    if ( len % 16 == 0 ) {
           for(; p-buf < len; p += 16)
 
    if ( len % 16 == 0 ) {
           for(; p-buf < len; p += 16)

-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+          Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",

                                name,
                                p-buf,
                                len,
                                name,
                                p-buf,
                                len,


@@ -31,12 +30,12 @@ void print_result(char *name, uint8_t *buf, size_t len) {
    }
    else {
    for(; p-buf < len; p += 8)
    }
    else {
    for(; p-buf < len; p += 8)

-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+          Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);

    }
 }
 
 size_t nbytes(size_t nbits) {
    }
 }
 
 size_t nbytes(size_t nbits) {

-       return (nbits/8)+((nbits%8)>0);
+       return (nbits >> 3)+((nbits % 8) > 0);

 }
 
 uint32_t SwapBits(uint32_t value, int nrbits) {
 }
 
 uint32_t SwapBits(uint32_t value, int nrbits) {


@@ -69,22 +68,17 @@ uint64_t bytes_to_num(uint8_t* src, size_t len)
 
 // RotateLeft - Ultralight, Desfire
 void rol(uint8_t *data, const size_t len){
 
 // RotateLeft - Ultralight, Desfire
 void rol(uint8_t *data, const size_t len){

-    uint8_t first = data[0];
-    for (size_t i = 0; i < len-1; i++) {
-        data[i] = data[i+1];
-    }
-    data[len-1] = first;
+       uint8_t first = data[0];
+       for (size_t i = 0; i < len-1; i++) {
+               data[i] = data[i+1];
+       }
+       data[len-1] = first;

 }
 void lsl (uint8_t *data, size_t len) {
 }
 void lsl (uint8_t *data, size_t len) {

-    for (size_t n = 0; n < len - 1; n++) {
-        data[n] = (data[n] << 1) | (data[n+1] >> 7);
-    }
-    data[len - 1] <<= 1;
-}
-
-int32_t le24toh (uint8_t data[3])
-{
-    return (data[2] << 16) | (data[1] << 8) | data[0];
+       for (size_t n = 0; n < len - 1; n++) {
+               data[n] = (data[n] << 1) | (data[n+1] >> 7);
+       }
+       data[len - 1] <<= 1;

 }
 
 void LEDsoff()
 }
 
 void LEDsoff()


@@ -95,6 +89,22 @@ void LEDsoff()
        LED_D_OFF();
 }
 
        LED_D_OFF();
 }
 

+void LEDson()
+{
+       LED_A_ON();
+       LED_B_ON();
+       LED_C_ON();
+       LED_D_ON();
+}
+
+void LEDsinvert()
+{
+       LED_A_INV();
+       LED_B_INV();
+       LED_C_INV();
+       LED_D_INV();
+}
+

 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 void LED(int led, int ms)
 {
 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 void LED(int led, int ms)
 {


@@ -127,8 +137,7 @@ void LED(int led, int ms)
 // not clicked, or held down (for ms || 1sec)
 // In general, don't use this function unless you expect a
 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead
 // not clicked, or held down (for ms || 1sec)
 // In general, don't use this function unless you expect a
 // double click, otherwise it will waste 500ms -- use BUTTON_HELD instead

-int BUTTON_CLICKED(int ms)
-{
+int BUTTON_CLICKED(int ms) {

        // Up to 500ms in between clicks to mean a double click
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 
        // Up to 500ms in between clicks to mean a double click
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 


@@ -190,8 +199,7 @@ int BUTTON_CLICKED(int ms)
 }
 
 // Determine if a button is held down
 }
 
 // Determine if a button is held down

-int BUTTON_HELD(int ms)
-{
+int BUTTON_HELD(int ms) {

        // If button is held for one second
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 
        // If button is held for one second
        int ticks = (48000 * (ms ? ms : 1000)) >> 10;
 


@@ -208,8 +216,7 @@ int BUTTON_HELD(int ms)
 
        uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 
 
        uint16_t start = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 

-       for(;;)
-       {
+       for(;;) {

                uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 
                // As soon as our button let go, we didn't hold long enough
                uint16_t now = AT91C_BASE_PWMC_CH0->PWMC_CCNTR;
 
                // As soon as our button let go, we didn't hold long enough


@@ -217,8 +224,7 @@ int BUTTON_HELD(int ms)
                        return BUTTON_SINGLE_CLICK;
 
                // Have we waited the full second?
                        return BUTTON_SINGLE_CLICK;
 
                // Have we waited the full second?

-               else
-                       if (now == (uint16_t)(start + ticks))
+               else if (now == (uint16_t)(start + ticks))

                                return BUTTON_HOLD;
 
                WDT_HIT();
                                return BUTTON_HOLD;
 
                WDT_HIT();


@@ -230,8 +236,7 @@ int BUTTON_HELD(int ms)
 
 // attempt at high resolution microsecond timer
 // beware: timer counts in 21.3uS increments (1024/48Mhz)
 
 // attempt at high resolution microsecond timer
 // beware: timer counts in 21.3uS increments (1024/48Mhz)

-void SpinDelayUs(int us)
-{
+void SpinDelayUs(int us) {

        int ticks = (48*us) >> 10;
 
        // Borrow a PWM unit for my real-time clock
        int ticks = (48*us) >> 10;
 
        // Borrow a PWM unit for my real-time clock


@@ -252,8 +257,7 @@ void SpinDelayUs(int us)
        }
 }
 
        }
 }
 

-void SpinDelay(int ms)
-{
+void SpinDelay(int ms) {

   // convert to uS and call microsecond delay function
        SpinDelayUs(ms*1000);
 }
   // convert to uS and call microsecond delay function
        SpinDelayUs(ms*1000);
 }


@@ -269,15 +273,15 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
        dst[0] = 0;
        strncat(dst, prefix, len-1);
        if(v->magic != VERSION_INFORMATION_MAGIC) {
        dst[0] = 0;
        strncat(dst, prefix, len-1);
        if(v->magic != VERSION_INFORMATION_MAGIC) {

-               strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
+               strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);

                return;
        }
        if(v->versionversion != 1) {
                return;
        }
        if(v->versionversion != 1) {

-               strncat(dst, "Version information not understood", len - strlen(dst) - 1);
+               strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);

                return;
        }
        if(!v->present) {
                return;
        }
        if(!v->present) {

-               strncat(dst, "Version information not available", len - strlen(dst) - 1);
+               strncat(dst, "Version information not available\n", len - strlen(dst) - 1);

                return;
        }
 
                return;
        }
 


@@ -290,41 +294,44 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 
        strncat(dst, " ", len - strlen(dst) - 1);
        strncat(dst, v->buildtime, len - strlen(dst) - 1);
 
        strncat(dst, " ", len - strlen(dst) - 1);
        strncat(dst, v->buildtime, len - strlen(dst) - 1);

+       strncat(dst, "\n", len - strlen(dst) - 1);

 }
 
 }
 

+

 //  -------------------------------------------------------------------------
 //  timer lib
 //  -------------------------------------------------------------------------
 //  test procedure:
 //
 //  -------------------------------------------------------------------------
 //  timer lib
 //  -------------------------------------------------------------------------
 //  test procedure:
 //

-//     ti = GetTickCount();
-//     SpinDelay(1000);
-//     ti = GetTickCount() - ti;
-//     Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
-
-void StartTickCount()
-{
-//  must be 0x40, but on my cpu - included divider is optimal
-//  0x20 - 1 ms / bit 
-//  0x40 - 2 ms / bit
-
-       AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
+//  ti = GetTickCount();
+//  SpinDelay(1000);
+//  ti = GetTickCount() - ti;
+//  Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
+
+void StartTickCount() {
+       // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
+       // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
+       uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;     // = 16 * main clock frequency (16MHz) / slow clock frequency
+       // set RealTimeCounter divider to count at 1kHz:
+       AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
+       // note: worst case precision is approx 2.5%

 }
 
 }
 

+

 /*
 * Get the current count.
 */
 /*
 * Get the current count.
 */

-uint32_t RAMFUNC GetTickCount(){
+uint32_t RAMFUNC GetTickCount(void) {

        return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
 }
 
        return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
 }
 

+

 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------

-//  microseconds timer 
+//  microseconds timer

 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------

-void StartCountUS()
-{
+void StartCountUS(void) {

        AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
        AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);

-//     AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
+//  AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;

        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 
        // fast clock
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 
        // fast clock


@@ -334,22 +341,24 @@ void StartCountUS()
                                                                                                                AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
        AT91C_BASE_TC0->TC_RA = 1;
        AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
                                                                                                                AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
        AT91C_BASE_TC0->TC_RA = 1;
        AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000

-       
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
+
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable

        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0

-       
+

        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TCB->TCB_BCR = 1;
        }
 
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TCB->TCB_BCR = 1;
        }
 

-uint32_t RAMFUNC GetCountUS(){
-       return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
+
+uint32_t RAMFUNC GetCountUS(void) {
+       return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); //was  /15) * 10);

 }
 
 }
 

+

 static uint32_t GlobalUsCounter = 0;
 
 static uint32_t GlobalUsCounter = 0;
 

-uint32_t RAMFUNC GetDeltaCountUS(){
+uint32_t RAMFUNC GetDeltaCountUS(void) {

        uint32_t g_cnt = GetCountUS();
        uint32_t g_res = g_cnt - GlobalUsCounter;
        GlobalUsCounter = g_cnt;
        uint32_t g_cnt = GetCountUS();
        uint32_t g_res = g_cnt - GlobalUsCounter;
        GlobalUsCounter = g_cnt;


@@ -358,162 +367,201 @@ uint32_t RAMFUNC GetDeltaCountUS(){
 
 
 //  -------------------------------------------------------------------------
 
 
 //  -------------------------------------------------------------------------

-//  Timer for iso14443 commands. Uses ssp_clk from FPGA 
+//  Timer for iso14443 commands. Uses ssp_clk from FPGA

 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------

-void StartCountSspClk()
-{
+void StartCountSspClk(void) {

        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers

-       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
-                                                       | AT91C_TCB_TC1XC1S_NONE                // XC1 Clock = none
-                                                       | AT91C_TCB_TC2XC2S_TIOA0;              // XC2 Clock = TIOA0
+       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1       // XC0 Clock = TIOA1
+                                                       | AT91C_TCB_TC1XC1S_NONE        // XC1 Clock = none
+                                                       | AT91C_TCB_TC2XC2S_TIOA0;      // XC2 Clock = TIOA0

 
        // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
 
        // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:

-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC1
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;               // disable TC1

        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz

-                                                       | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
-                                                       | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event
-                                                       | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
-                                                       | AT91C_TC_ENETRG                               // Enable external trigger event
-                                                       | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
-                                                       | AT91C_TC_WAVE                                 // Waveform Mode
-                                                       | AT91C_TC_AEEVT_SET                    // Set TIOA1 on external event
-                                                       | AT91C_TC_ACPC_CLEAR;                  // Clear TIOA1 on RC Compare
-       AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
+                                                       | AT91C_TC_CPCSTOP              // Stop clock on RC compare
+                                                       | AT91C_TC_EEVTEDG_RISING       // Trigger on rising edge of Event
+                                                       | AT91C_TC_EEVT_TIOB            // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16 ... 13,56MHz/4)
+                                                       | AT91C_TC_ENETRG               // Enable external trigger event
+                                                       | AT91C_TC_WAVESEL_UP           // Upmode without automatic trigger on RC compare
+                                                       | AT91C_TC_WAVE                 // Waveform Mode
+                                                       | AT91C_TC_AEEVT_SET            // Set TIOA1 on external event
+                                                       | AT91C_TC_ACPC_CLEAR;          // Clear TIOA1 on RC Compare
+       AT91C_BASE_TC1->TC_RC = 1;                              // RC Compare value = 1; pulse width to TC0

 
        // use TC0 to count TIOA1 pulses
 
        // use TC0 to count TIOA1 pulses

-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0
-       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0                              // TC0 clock = XC0 clock = TIOA1
-                                                       | AT91C_TC_WAVE                                 // Waveform Mode
-                                                       | AT91C_TC_WAVESEL_UP                   // just count
-                                                       | AT91C_TC_ACPA_CLEAR                   // Clear TIOA0 on RA Compare
-                                                       | AT91C_TC_ACPC_SET;                    // Set TIOA0 on RC Compare
-       AT91C_BASE_TC0->TC_RA = 1;                                                              // RA Compare value = 1; pulse width to TC2
-       AT91C_BASE_TC0->TC_RC = 0;                                                              // RC Compare value = 0; increment TC2 on overflow
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;               // disable TC0
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0              // TC0 clock = XC0 clock = TIOA1
+                                                       | AT91C_TC_WAVE                 // Waveform Mode
+                                                       | AT91C_TC_WAVESEL_UP           // just count
+                                                       | AT91C_TC_ACPA_CLEAR           // Clear TIOA0 on RA Compare
+                                                       | AT91C_TC_ACPC_SET;            // Set TIOA0 on RC Compare
+       AT91C_BASE_TC0->TC_RA = 1;                              // RA Compare value = 1; pulse width to TC2
+       AT91C_BASE_TC0->TC_RC = 0;                              // RC Compare value = 0; increment TC2 on overflow

 
        // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
 
        // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)

-       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC2  
-       AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
-                                                       | AT91C_TC_WAVE                                 // Waveform Mode
-                                                       | AT91C_TC_WAVESEL_UP;                  // just count
-       
-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
-       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;               // disable TC2
+       AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2              // TC2 clock = XC2 clock = TIOA0
+                                                       | AT91C_TC_WAVE                 // Waveform Mode
+                                                       | AT91C_TC_WAVESEL_UP;          // just count
+
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                // enable TC0
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                // enable TC1
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                // enable TC2

 
        //
 
        //

-       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
+       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in a FPGA mode with SSC transfer, otherwise SSC_FRAME and SSC_CLK signals would not be present

        //
        //

-       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
-       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
-       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
-       // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
+       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);      // wait for ssp_frame to be low
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high; 1st ssp_clk after start of frame
+       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);        // wait for ssp_clk to go low;
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high; 2nd ssp_clk after start of frame
+       if ((AT91C_BASE_SSC->SSC_RFMR & SSC_FRAME_MODE_BITS_IN_WORD(32)) == SSC_FRAME_MODE_BITS_IN_WORD(16)) { // 16bit frame
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 3rd ssp_clk after start of frame
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 4th ssp_clk after start of frame
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 5th ssp_clk after start of frame
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 6th ssp_clk after start of frame
+       }

        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge

-       AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
-       // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
-       // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
-       // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
-       // (just started with the transfer of the 4th Bit).
+       AT91C_BASE_TCB->TCB_BCR = 1;                            // assert Sync (set all timers to 0 on next active clock edge)
+       // at the next (3rd/7th) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
+       // at the next (4th/8th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
+       // whenever the last three/four bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
+

        // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
        // we can use the counter.
        // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
        // we can use the counter.

-       while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+       while (AT91C_BASE_TC0->TC_CV < 0xFFFF);
+       // Note: needs one more SSP_CLK cycle (1.18 us) until TC2 resets. Don't call GetCountSspClk() that soon.

 }
 
 
 }
 
 

-uint32_t RAMFUNC GetCountSspClk(){
-       uint32_t tmp_count;
-       tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
-       if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
-               return (AT91C_BASE_TC2->TC_CV << 16);
-       } 
-       else {
-               return tmp_count;
-       }
+void ResetSspClk(void) {
+       //enable clock of timer and software trigger
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC2->TC_CV > 0);
+}
+
+uint32_t GetCountSspClk(){
+       uint32_t hi, lo;
+
+       do { 
+               hi = AT91C_BASE_TC2->TC_CV;
+               lo = AT91C_BASE_TC0->TC_CV;
+       } while (hi != AT91C_BASE_TC2->TC_CV);
+       
+       return (hi << 16) | lo;
+}
+
+//  -------------------------------------------------------------------------
+//  Timer for bitbanging, or LF stuff when you need a very precis timer
+//  1us = 1.5ticks
+//  -------------------------------------------------------------------------
+void StartTicks(void){
+       // initialization of the timer
+       AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
+       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
+
+       // disable TC0 and TC1 for re-configuration
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+
+       // first configure TC1 (higher, 0xFFFF0000) 16 bit counter
+       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // just connect to TIOA0 from TC0
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
+
+       // second configure TC0 (lower, 0x0000FFFF) 16 bit counter
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
+                                                        AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
+                                                        AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
+                                                        AT91C_TC_ACPC_SET |   // RC comperator sets TIOA (carry bit)
+                                                        AT91C_TC_ASWTRG_SET;  // SWTriger sets TIOA (carry bit)
+       AT91C_BASE_TC0->TC_RC  = 0; // set TIOA (carry bit) on overflow, return to zero
+       AT91C_BASE_TC0->TC_RA  = 1; // clear carry bit on next clock cycle
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer
+
+       // synchronized startup procedure
+       while (AT91C_BASE_TC0->TC_CV > 0); // wait until TC0 returned to zero
+       while (AT91C_BASE_TC0->TC_CV < 2); // and has started (TC_CV > TC_RA, now TC1 is cleared)
+
+       // return to zero
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_SWTRG;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC0->TC_CV > 0);

 }
 }

-void iso14a_clear_trace() {
-       clear_trace();
+
+
+uint32_t GetTicks(void) {
+       uint32_t hi, lo;
+
+       do {
+               hi = AT91C_BASE_TC1->TC_CV;
+               lo = AT91C_BASE_TC0->TC_CV;
+       } while(hi != AT91C_BASE_TC1->TC_CV);
+
+       return (hi << 16) | lo;

 }
 
 }
 

-void iso14a_set_tracing(bool enable) {
-       set_tracing(enable);
+
+// Wait - Spindelay in ticks.
+// if called with a high number, this will trigger the WDT...
+void WaitTicks(uint32_t ticks){
+       if ( ticks == 0 ) return;
+       ticks += GetTicks();
+       while (GetTicks() < ticks);

 }
 
 }
 

-void clear_trace() {
-       uint8_t *trace = BigBuf_get_addr();
-       uint16_t max_traceLen = BigBuf_max_traceLen();
-       memset(trace, 0x44, max_traceLen);
-       traceLen = 0;
+
+// Wait / Spindelay in us (microseconds)
+// 1us = 1.5ticks.
+void WaitUS(uint16_t us){
+       WaitTicks( (uint32_t)us * 3 / 2 ) ;

 }
 
 }
 

-void set_tracing(bool enable) {
-       tracing = enable;
+
+void WaitMS(uint16_t ms){
+       WaitTicks( (uint32_t)ms * 1500 );

 }
 
 }
 

-/**
-  This is a function to store traces. All protocols can use this generic tracer-function.
-  The traces produced by calling this function can be fetched on the client-side
-  by 'hf list raw', alternatively 'hf list <proto>' for protocol-specific
-  annotation of commands/responses.

 
 

-**/
-bool RAMFUNC LogTrace(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag)
-{
-       if (!tracing) return FALSE;
+// Starts Clock and waits until its reset
+void ResetTicks(void){
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC0->TC_CV > 0);
+}

 
 

-       uint8_t *trace = BigBuf_get_addr();

 
 

-       uint16_t num_paritybytes = (iLen-1)/8 + 1;      // number of valid paritybytes in *parity
-       uint16_t duration = timestamp_end - timestamp_start;
+void ResetTimer(AT91PS_TC timer){
+       timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while(timer->TC_CV > 0) ;
+}

 
 

-       // Return when trace is full
-       uint16_t max_traceLen = BigBuf_max_traceLen();

 
 

-       if (traceLen + sizeof(iLen) + sizeof(timestamp_start) + sizeof(duration) + num_paritybytes + iLen >= max_traceLen) {
-               tracing = FALSE;        // don't trace any more
-               return FALSE;
-       }
-       // Traceformat:
-       // 32 bits timestamp (little endian)
-       // 16 bits duration (little endian)
-       // 16 bits data length (little endian, Highest Bit used as readerToTag flag)
-       // y Bytes data
-       // x Bytes parity (one byte per 8 bytes data)
-
-       // timestamp (start)
-       trace[traceLen++] = ((timestamp_start >> 0) & 0xff);
-       trace[traceLen++] = ((timestamp_start >> 8) & 0xff);
-       trace[traceLen++] = ((timestamp_start >> 16) & 0xff);
-       trace[traceLen++] = ((timestamp_start >> 24) & 0xff);
-
-       // duration
-       trace[traceLen++] = ((duration >> 0) & 0xff);
-       trace[traceLen++] = ((duration >> 8) & 0xff);
-
-       // data length
-       trace[traceLen++] = ((iLen >> 0) & 0xff);
-       trace[traceLen++] = ((iLen >> 8) & 0xff);
-
-       // readerToTag flag
-       if (!readerToTag) {
-               trace[traceLen - 1] |= 0x80;
-       }
+// stop clock
+void StopTicks(void){
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;
+}

 
 

-       // data bytes
-       if (btBytes != NULL && iLen != 0) {
-               memcpy(trace + traceLen, btBytes, iLen);
-       }
-       traceLen += iLen;

 
 

-       // parity bytes
-       if (parity != NULL && iLen != 0) {
-               memcpy(trace + traceLen, parity, num_paritybytes);
-       }
-       traceLen += num_paritybytes;
+static uint64_t next_random = 1;

 
 

-       if(traceLen +4 < max_traceLen)
-       {       //If it hadn't been cleared, for whatever reason..
-               memset(trace+traceLen,0x44, 4);
+/* Generates a (non-cryptographically secure) 32-bit random number.
+ *
+ * We don't have an implementation of the "rand" function or a clock to seed it
+ * with, so we just call GetTickCount the first time to seed ourselves.
+ */
+uint32_t prand() {
+       if (next_random == 1) {
+               next_random = GetTickCount();

        }
 
        }
 

-       return TRUE;
+       next_random = next_random * 6364136223846793005 + 1;
+       return (uint32_t)(next_random >> 32) % 0xffffffff;

 }
 }

-