optimization UDOL creation. does not affect on functionality.

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index cce9bed80a471e403c7eef1ee78096f5abcf024d..e25c6e0ba8e98d9c836082568150281f1581084e 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -12,6 +12,7 @@
 #include "util.h"
 #include "string.h"
 #include "apps.h"
 #include "util.h"
 #include "string.h"
 #include "apps.h"

+#include "BigBuf.h"

 
 
 
 
 
 


@@ -34,7 +35,7 @@ void print_result(char *name, uint8_t *buf, size_t len) {
 }
 
 size_t nbytes(size_t nbits) {
 }
 
 size_t nbytes(size_t nbits) {

-       return (nbits/8)+((nbits%8)>0);
+       return (nbits >> 3)+((nbits % 8) > 0);

 }
 
 uint32_t SwapBits(uint32_t value, int nrbits) {
 }
 
 uint32_t SwapBits(uint32_t value, int nrbits) {


@@ -267,15 +268,15 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
        dst[0] = 0;
        strncat(dst, prefix, len-1);
        if(v->magic != VERSION_INFORMATION_MAGIC) {
        dst[0] = 0;
        strncat(dst, prefix, len-1);
        if(v->magic != VERSION_INFORMATION_MAGIC) {

-               strncat(dst, "Missing/Invalid version information", len - strlen(dst) - 1);
+               strncat(dst, "Missing/Invalid version information\n", len - strlen(dst) - 1);

                return;
        }
        if(v->versionversion != 1) {
                return;
        }
        if(v->versionversion != 1) {

-               strncat(dst, "Version information not understood", len - strlen(dst) - 1);
+               strncat(dst, "Version information not understood\n", len - strlen(dst) - 1);

                return;
        }
        if(!v->present) {
                return;
        }
        if(!v->present) {

-               strncat(dst, "Version information not available", len - strlen(dst) - 1);
+               strncat(dst, "Version information not available\n", len - strlen(dst) - 1);

                return;
        }
 
                return;
        }
 


@@ -288,8 +289,10 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 
        strncat(dst, " ", len - strlen(dst) - 1);
        strncat(dst, v->buildtime, len - strlen(dst) - 1);
 
        strncat(dst, " ", len - strlen(dst) - 1);
        strncat(dst, v->buildtime, len - strlen(dst) - 1);

+       strncat(dst, "\n", len - strlen(dst) - 1);

 }
 
 }
 

+

 //  -------------------------------------------------------------------------
 //  timer lib
 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------
 //  timer lib
 //  -------------------------------------------------------------------------


@@ -302,13 +305,15 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 
 void StartTickCount()
 {
 
 void StartTickCount()
 {

-//  must be 0x40, but on my cpu - included divider is optimal
-//  0x20 - 1 ms / bit 
-//  0x40 - 2 ms / bit
-
-       AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
+       // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
+       // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
+    uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;                // = 16 * main clock frequency (16MHz) / slow clock frequency
+       // set RealTimeCounter divider to count at 1kHz:
+       AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
+       // note: worst case precision is approx 2.5%

 }
 
 }
 

+

 /*
 * Get the current count.
 */
 /*
 * Get the current count.
 */


@@ -316,6 +321,7 @@ uint32_t RAMFUNC GetTickCount(){
        return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
 }
 
        return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
 }
 

+

 //  -------------------------------------------------------------------------
 //  microseconds timer 
 //  -------------------------------------------------------------------------
 //  -------------------------------------------------------------------------
 //  microseconds timer 
 //  -------------------------------------------------------------------------


@@ -341,10 +347,12 @@ void StartCountUS()
        AT91C_BASE_TCB->TCB_BCR = 1;
        }
 
        AT91C_BASE_TCB->TCB_BCR = 1;
        }
 

+

 uint32_t RAMFUNC GetCountUS(){
 uint32_t RAMFUNC GetCountUS(){

-       return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
+       return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); //was  /15) * 10);

 }
 
 }
 

+

 static uint32_t GlobalUsCounter = 0;
 
 uint32_t RAMFUNC GetDeltaCountUS(){
 static uint32_t GlobalUsCounter = 0;
 
 uint32_t RAMFUNC GetDeltaCountUS(){


@@ -399,7 +407,7 @@ void StartCountSspClk()
        AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
 
        //
        AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
 
        //

-       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14446 mode, otherwise the frame signal would not be present 
+       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14443 mode, otherwise SSC_FRAME and SSC_CLK signals would not be present 

        //
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
        //
        while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
        while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low


@@ -413,7 +421,17 @@ void StartCountSspClk()
        // (just started with the transfer of the 4th Bit).
        // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
        // we can use the counter.
        // (just started with the transfer of the 4th Bit).
        // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
        // we can use the counter.

-       while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+       while (AT91C_BASE_TC0->TC_CV < 0xFFFF);
+       // Note: needs one more SSP_CLK cycle (1.18 us) until TC2 resets. Don't call GetCountSspClk() that soon.
+}
+
+
+void ResetSspClk(void) {
+       //enable clock of timer and software trigger
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC2->TC_CV > 0);

 }
 
 
 }
 
 


@@ -428,64 +446,92 @@ uint32_t RAMFUNC GetCountSspClk(){
        }
 }
 
        }
 }
 

-/**
-  This is a function to store traces. All protocols can use this generic tracer-function.
-  The traces produced by calling this function can be fetched on the client-side
-  by 'hf list raw', alternatively 'hf list <proto>' for protocol-specific
-  annotation of commands/responses.

 
 

-**/
-bool RAMFUNC LogTrace(const uint8_t *btBytes, uint16_t iLen, uint32_t timestamp_start, uint32_t timestamp_end, uint8_t *parity, bool readerToTag)
-{
-       if (!tracing) return FALSE;
+//  -------------------------------------------------------------------------
+//  Timer for bitbanging,  or LF stuff when you need a very precis timer
+//  1us = 1.5ticks
+//  -------------------------------------------------------------------------
+void StartTicks(void){
+       //initialization of the timer
+       // tc1 is higher 0xFFFF0000
+       // tc0 is lower 0x0000FFFF
+       AT91C_BASE_PMC->PMC_PCER |= (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1);
+       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32 
+                                                               AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
+                                                               AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
+       AT91C_BASE_TC0->TC_RA = 1;
+       AT91C_BASE_TC0->TC_RC = 0; 

 
 

-       uint16_t num_paritybytes = (iLen-1)/8 + 1;      // number of valid paritybytes in *parity
-       uint16_t duration = timestamp_end - timestamp_start;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;       // timer disable  
+       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from TC0
+       
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TCB->TCB_BCR = 1;
+       
+       // wait until timer becomes zero.
+       while (AT91C_BASE_TC1->TC_CV > 0);
+}

 
 

-       // Return when trace is full
-       if (traceLen + sizeof(iLen) + sizeof(timestamp_start) + sizeof(duration) + num_paritybytes + iLen >= TRACE_SIZE) {
-               tracing = FALSE;        // don't trace any more
-               return FALSE;
-       }

 
 

-       // Traceformat:
-       // 32 bits timestamp (little endian)
-       // 16 bits duration (little endian)
-       // 16 bits data length (little endian, Highest Bit used as readerToTag flag)
-       // y Bytes data
-       // x Bytes parity (one byte per 8 bytes data)
-
-       // timestamp (start)
-       trace[traceLen++] = ((timestamp_start >> 0) & 0xff);
-       trace[traceLen++] = ((timestamp_start >> 8) & 0xff);
-       trace[traceLen++] = ((timestamp_start >> 16) & 0xff);
-       trace[traceLen++] = ((timestamp_start >> 24) & 0xff);
-
-       // duration
-       trace[traceLen++] = ((duration >> 0) & 0xff);
-       trace[traceLen++] = ((duration >> 8) & 0xff);
-
-       // data length
-       trace[traceLen++] = ((iLen >> 0) & 0xff);
-       trace[traceLen++] = ((iLen >> 8) & 0xff);
-
-       // readerToTag flag
-       if (!readerToTag) {
-               trace[traceLen - 1] |= 0x80;
-       }
+// Wait - Spindelay in ticks.
+// if called with a high number, this will trigger the WDT...
+void WaitTicks(uint32_t ticks){
+       if ( ticks == 0 ) return;
+       ticks += GET_TICKS;     
+       while (GET_TICKS < ticks);
+}

 
 

-       // data bytes
-       if (btBytes != NULL && iLen != 0) {
-               memcpy(trace + traceLen, btBytes, iLen);
-       }
-       traceLen += iLen;

 
 

-       // parity bytes
-       if (parity != NULL && iLen != 0) {
-               memcpy(trace + traceLen, parity, num_paritybytes);
-       }
-       traceLen += num_paritybytes;
+// Wait / Spindelay in us (microseconds) 
+// 1us = 1.5ticks.
+void WaitUS(uint16_t us){
+       if ( us == 0 ) return;
+       WaitTicks(  (uint32_t)(us * 1.5) );
+}
+
+
+void WaitMS(uint16_t ms){
+       if (ms == 0) return;
+       WaitTicks( (uint32_t)(ms * 1500) );
+}
+
+
+// Starts Clock and waits until its reset
+void ResetTicks(void){
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC1->TC_CV > 0);
+}

 
 

-       return TRUE;
+
+void ResetTimer(AT91PS_TC timer){
+       timer->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while(timer->TC_CV > 0) ;

 }
 
 }
 

+
+// stop clock
+void StopTicks(void){
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;       
+}
+
+
+static uint64_t next_random = 1;
+
+/* Generates a (non-cryptographically secure) 32-bit random number.
+ *
+ * We don't have an implementation of the "rand" function or a clock to seed it
+ * with, so we just call GetTickCount the first time to seed ourselves.
+ */
+uint32_t prand() {
+       if (next_random == 1) {
+               next_random = GetTickCount();
+       }
+
+       next_random = next_random * 6364136223846793005 + 1;
+       return (uint32_t)(next_random >> 32) % 0xffffffff;
+}