fix 'hf iclass snoop'

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index a1b0f1518b98e417d6c07217412bf2a746e54dc5..4bff3a26a5e03b6fb20745e009e90c8c9b075016 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -21,7 +21,7 @@ void print_result(char *name, uint8_t *buf, size_t len) {
 
    if ( len % 16 == 0 ) {
           for(; p-buf < len; p += 16)
 
    if ( len % 16 == 0 ) {
           for(; p-buf < len; p += 16)

-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",
+          Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x",

                                name,
                                p-buf,
                                len,
                                name,
                                p-buf,
                                len,


@@ -30,7 +30,7 @@ void print_result(char *name, uint8_t *buf, size_t len) {
    }
    else {
    for(; p-buf < len; p += 8)
    }
    else {
    for(; p-buf < len; p += 8)

-       Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);
+          Dbprintf("[%s:%d/%d] %02x %02x %02x %02x %02x %02x %02x %02x", name, p-buf, len, p[0], p[1], p[2], p[3], p[4], p[5], p[6], p[7]);

    }
 }
 
    }
 }
 


@@ -68,17 +68,17 @@ uint64_t bytes_to_num(uint8_t* src, size_t len)
 
 // RotateLeft - Ultralight, Desfire
 void rol(uint8_t *data, const size_t len){
 
 // RotateLeft - Ultralight, Desfire
 void rol(uint8_t *data, const size_t len){

-    uint8_t first = data[0];
-    for (size_t i = 0; i < len-1; i++) {
-        data[i] = data[i+1];
-    }
-    data[len-1] = first;
+       uint8_t first = data[0];
+       for (size_t i = 0; i < len-1; i++) {
+               data[i] = data[i+1];
+       }
+       data[len-1] = first;

 }
 void lsl (uint8_t *data, size_t len) {
 }
 void lsl (uint8_t *data, size_t len) {

-    for (size_t n = 0; n < len - 1; n++) {
-        data[n] = (data[n] << 1) | (data[n+1] >> 7);
-    }
-    data[len - 1] <<= 1;
+       for (size_t n = 0; n < len - 1; n++) {
+               data[n] = (data[n] << 1) | (data[n+1] >> 7);
+       }
+       data[len - 1] <<= 1;

 }
 
 void LEDsoff()
 }
 
 void LEDsoff()


@@ -89,6 +89,22 @@ void LEDsoff()
        LED_D_OFF();
 }
 
        LED_D_OFF();
 }
 

+void LEDson()
+{
+       LED_A_ON();
+       LED_B_ON();
+       LED_C_ON();
+       LED_D_ON();
+}
+
+void LEDsinvert()
+{
+       LED_A_INV();
+       LED_B_INV();
+       LED_C_INV();
+       LED_D_INV();
+}
+

 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 void LED(int led, int ms)
 {
 // LEDs: R(C) O(A) G(B) -- R(D) [1, 2, 4 and 8]
 void LED(int led, int ms)
 {


@@ -293,16 +309,16 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
 //  -------------------------------------------------------------------------
 //  test procedure:
 //
 //  -------------------------------------------------------------------------
 //  test procedure:
 //

-//     ti = GetTickCount();
-//     SpinDelay(1000);
-//     ti = GetTickCount() - ti;
-//     Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
+//  ti = GetTickCount();
+//  SpinDelay(1000);
+//  ti = GetTickCount() - ti;
+//  Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());

 
 void StartTickCount()
 {
        // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
        // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.
 
 void StartTickCount()
 {
        // This timer is based on the slow clock. The slow clock frequency is between 22kHz and 40kHz.
        // We can determine the actual slow clock frequency by looking at the Main Clock Frequency Register.

-    uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;                // = 16 * main clock frequency (16MHz) / slow clock frequency
+       uint16_t mainf = AT91C_BASE_PMC->PMC_MCFR & 0xffff;     // = 16 * main clock frequency (16MHz) / slow clock frequency

        // set RealTimeCounter divider to count at 1kHz:
        AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
        // note: worst case precision is approx 2.5%
        // set RealTimeCounter divider to count at 1kHz:
        AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST | ((256000 + (mainf/2)) / mainf);
        // note: worst case precision is approx 2.5%


@@ -318,12 +334,12 @@ uint32_t RAMFUNC GetTickCount(){
 
 
 //  -------------------------------------------------------------------------
 
 
 //  -------------------------------------------------------------------------

-//  microseconds timer 
+//  microseconds timer

 //  -------------------------------------------------------------------------
 void StartCountUS()
 {
        AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
 //  -------------------------------------------------------------------------
 void StartCountUS()
 {
        AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);

-//     AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
+//  AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;

        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 
        // fast clock
        AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
 
        // fast clock


@@ -333,10 +349,10 @@ void StartCountUS()
                                                                                                                AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
        AT91C_BASE_TC0->TC_RA = 1;
        AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
                                                                                                                AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
        AT91C_BASE_TC0->TC_RA = 1;
        AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000

-       
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
+
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable

        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0

-       
+

        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TCB->TCB_BCR = 1;
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
        AT91C_BASE_TCB->TCB_BCR = 1;


@@ -359,61 +375,72 @@ uint32_t RAMFUNC GetDeltaCountUS(){
 
 
 //  -------------------------------------------------------------------------
 
 
 //  -------------------------------------------------------------------------

-//  Timer for iso14443 commands. Uses ssp_clk from FPGA 
+//  Timer for iso14443 commands. Uses ssp_clk from FPGA

 //  -------------------------------------------------------------------------
 void StartCountSspClk()
 {
        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers
 //  -------------------------------------------------------------------------
 void StartCountSspClk()
 {
        AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_TC0) | (1 << AT91C_ID_TC1) | (1 << AT91C_ID_TC2);  // Enable Clock to all timers

-       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1               // XC0 Clock = TIOA1
-                                                       | AT91C_TCB_TC1XC1S_NONE                // XC1 Clock = none
-                                                       | AT91C_TCB_TC2XC2S_TIOA0;              // XC2 Clock = TIOA0
+       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_TIOA1       // XC0 Clock = TIOA1
+                                                       | AT91C_TCB_TC1XC1S_NONE        // XC1 Clock = none
+                                                       | AT91C_TCB_TC2XC2S_TIOA0;      // XC2 Clock = TIOA0

 
        // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:
 
        // configure TC1 to create a short pulse on TIOA1 when a rising edge on TIOB1 (= ssp_clk from FPGA) occurs:

-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC1
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;               // disable TC1

        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_TIMER_DIV1_CLOCK // TC1 Clock = MCK(48MHz)/2 = 24MHz

-                                                       | AT91C_TC_CPCSTOP                              // Stop clock on RC compare
-                                                       | AT91C_TC_EEVTEDG_RISING               // Trigger on rising edge of Event
-                                                       | AT91C_TC_EEVT_TIOB                    // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16)
-                                                       | AT91C_TC_ENETRG                               // Enable external trigger event
-                                                       | AT91C_TC_WAVESEL_UP                   // Upmode without automatic trigger on RC compare
-                                                       | AT91C_TC_WAVE                                 // Waveform Mode
-                                                       | AT91C_TC_AEEVT_SET                    // Set TIOA1 on external event
-                                                       | AT91C_TC_ACPC_CLEAR;                  // Clear TIOA1 on RC Compare
-       AT91C_BASE_TC1->TC_RC = 0x04;                                                   // RC Compare value = 0x04
+                                                       | AT91C_TC_CPCSTOP              // Stop clock on RC compare
+                                                       | AT91C_TC_EEVTEDG_RISING       // Trigger on rising edge of Event
+                                                       | AT91C_TC_EEVT_TIOB            // Event-Source: TIOB1 (= ssp_clk from FPGA = 13,56MHz/16 ... 13,56MHz/4)
+                                                       | AT91C_TC_ENETRG               // Enable external trigger event
+                                                       | AT91C_TC_WAVESEL_UP           // Upmode without automatic trigger on RC compare
+                                                       | AT91C_TC_WAVE                 // Waveform Mode
+                                                       | AT91C_TC_AEEVT_SET            // Set TIOA1 on external event
+                                                       | AT91C_TC_ACPC_CLEAR;          // Clear TIOA1 on RC Compare
+       AT91C_BASE_TC1->TC_RC = 0x02;                           // RC Compare value = 0x02

 
        // use TC0 to count TIOA1 pulses
 
        // use TC0 to count TIOA1 pulses

-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC0
-       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0                              // TC0 clock = XC0 clock = TIOA1
-                                                       | AT91C_TC_WAVE                                 // Waveform Mode
-                                                       | AT91C_TC_WAVESEL_UP                   // just count
-                                                       | AT91C_TC_ACPA_CLEAR                   // Clear TIOA0 on RA Compare
-                                                       | AT91C_TC_ACPC_SET;                    // Set TIOA0 on RC Compare
-       AT91C_BASE_TC0->TC_RA = 1;                                                              // RA Compare value = 1; pulse width to TC2
-       AT91C_BASE_TC0->TC_RC = 0;                                                              // RC Compare value = 0; increment TC2 on overflow
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;               // disable TC0
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_XC0              // TC0 clock = XC0 clock = TIOA1
+                                                       | AT91C_TC_WAVE                 // Waveform Mode
+                                                       | AT91C_TC_WAVESEL_UP           // just count
+                                                       | AT91C_TC_ACPA_CLEAR           // Clear TIOA0 on RA Compare
+                                                       | AT91C_TC_ACPC_SET;            // Set TIOA0 on RC Compare
+       AT91C_BASE_TC0->TC_RA = 1;                              // RA Compare value = 1; pulse width to TC2
+       AT91C_BASE_TC0->TC_RC = 0;                              // RC Compare value = 0; increment TC2 on overflow

 
        // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)
 
        // use TC2 to count TIOA0 pulses (giving us a 32bit counter (TC0/TC2) clocked by ssp_clk)

-       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;                               // disable TC2  
-       AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2                              // TC2 clock = XC2 clock = TIOA0
-                                                       | AT91C_TC_WAVE                                 // Waveform Mode
-                                                       | AT91C_TC_WAVESEL_UP;                  // just count
-       
-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
-       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKDIS;               // disable TC2
+       AT91C_BASE_TC2->TC_CMR = AT91C_TC_CLKS_XC2              // TC2 clock = XC2 clock = TIOA0
+                                                       | AT91C_TC_WAVE                 // Waveform Mode
+                                                       | AT91C_TC_WAVESEL_UP;          // just count
+
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                // enable TC0
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                // enable TC1
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                // enable TC2

 
        //
 
        //

-       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in any iso14443 mode, otherwise SSC_FRAME and SSC_CLK signals would not be present 
+       // synchronize the counter with the ssp_frame signal. Note: FPGA must be in a FPGA mode with SSC transfer, otherwise SSC_FRAME and SSC_CLK signals would not be present

        //
        //

-       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
-       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);              // wait for ssp_frame to be low
-       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high
-       // note: up to now two ssp_clk rising edges have passed since the rising edge of ssp_frame
+       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME);      // wait for ssp_frame to be low
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_FRAME));   // wait for ssp_frame to go high (start of frame)
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high; 1st ssp_clk after start of frame
+       while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);        // wait for ssp_clk to go low;
+       while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK));     // wait for ssp_clk to go high; 2nd ssp_clk after start of frame
+       if ((AT91C_BASE_SSC->SSC_RFMR & SSC_FRAME_MODE_BITS_IN_WORD(32)) == SSC_FRAME_MODE_BITS_IN_WORD(16)) {
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 3rd ssp_clk after start of frame
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 4th ssp_clk after start of frame
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 5th ssp_clk after start of frame
+               while(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK);    // wait for ssp_clk to go low;
+               while(!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_CLK)); // wait for ssp_clk to go high; 6th ssp_clk after start of frame
+       }

        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge
        // it is now safe to assert a sync signal. This sets all timers to 0 on next active clock edge

-       AT91C_BASE_TCB->TCB_BCR = 1;                                                    // assert Sync (set all timers to 0 on next active clock edge)
-       // at the next (3rd) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
-       // at the next (4th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,
+       AT91C_BASE_TCB->TCB_BCR = 1;                            // assert Sync (set all timers to 0 on next active clock edge)
+       // at the next (3rd/7th) ssp_clk rising edge, TC1 will be reset (and not generate a clock signal to TC0)
+       // at the next (4th/8th) ssp_clk rising edge, TC0 (the low word of our counter) will be reset. From now on,

        // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.
        // whenever the last three bits of our counter go 0, we can be sure to be in the middle of a frame transfer.

-       // (just started with the transfer of the 4th Bit).
+       // (just started with the transfer of the 3rd Bit).

        // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
        // we can use the counter.
        while (AT91C_BASE_TC0->TC_CV < 0xFFFF);
        // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. Therefore need to wait quite some time before
        // we can use the counter.
        while (AT91C_BASE_TC0->TC_CV < 0xFFFF);


@@ -429,19 +456,17 @@ void ResetSspClk(void) {
        while (AT91C_BASE_TC2->TC_CV > 0);
 }
 
        while (AT91C_BASE_TC2->TC_CV > 0);
 }
 

+uint32_t GetCountSspClk(){
+       uint32_t hi, lo;

 
 

-uint32_t RAMFUNC GetCountSspClk(){
-       uint32_t tmp_count;
-       tmp_count = (AT91C_BASE_TC2->TC_CV << 16) | AT91C_BASE_TC0->TC_CV;
-       if ((tmp_count & 0x0000ffff) == 0) { //small chance that we may have missed an increment in TC2
-               return (AT91C_BASE_TC2->TC_CV << 16);
-       } 
-       else {
-               return tmp_count;
-       }
+       do { 
+               hi = AT91C_BASE_TC2->TC_CV;
+               lo = AT91C_BASE_TC0->TC_CV;
+       } while (hi != AT91C_BASE_TC2->TC_CV);
+       
+       return (hi << 16) | lo;

 }
 
 }
 

-

 //  -------------------------------------------------------------------------
 //  Timer for bitbanging, or LF stuff when you need a very precis timer
 //  1us = 1.5ticks
 //  -------------------------------------------------------------------------
 //  Timer for bitbanging, or LF stuff when you need a very precis timer
 //  1us = 1.5ticks


@@ -460,11 +485,11 @@ void StartTicks(void){
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
 
        // second configure TC0 (lower, 0x0000FFFF) 16 bit counter
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // re-enable timer and wait for TC0
 
        // second configure TC0 (lower, 0x0000FFFF) 16 bit counter

-       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32 
-                                AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
-                                AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
-                                AT91C_TC_ACPC_SET |   // RC comperator sets TIOA (carry bit)
-                                AT91C_TC_ASWTRG_SET;  // SWTriger sets TIOA (carry bit)
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz) / 32
+                                                        AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO |
+                                                        AT91C_TC_ACPA_CLEAR | // RA comperator clears TIOA (carry bit)
+                                                        AT91C_TC_ACPC_SET |   // RC comperator sets TIOA (carry bit)
+                                                        AT91C_TC_ASWTRG_SET;  // SWTriger sets TIOA (carry bit)

        AT91C_BASE_TC0->TC_RC  = 0; // set TIOA (carry bit) on overflow, return to zero
        AT91C_BASE_TC0->TC_RA  = 1; // clear carry bit on next clock cycle
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer
        AT91C_BASE_TC0->TC_RC  = 0; // set TIOA (carry bit) on overflow, return to zero
        AT91C_BASE_TC0->TC_RA  = 1; // clear carry bit on next clock cycle
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG; // reset and re-enable timer


@@ -501,7 +526,7 @@ void WaitTicks(uint32_t ticks){
 }
 
 
 }
 
 

-// Wait / Spindelay in us (microseconds) 
+// Wait / Spindelay in us (microseconds)

 // 1us = 1.5ticks.
 void WaitUS(uint16_t us){
        WaitTicks( (uint32_t)us * 3 / 2 ) ;
 // 1us = 1.5ticks.
 void WaitUS(uint16_t us){
        WaitTicks( (uint32_t)us * 3 / 2 ) ;


@@ -530,7 +555,7 @@ void ResetTimer(AT91PS_TC timer){
 // stop clock
 void StopTicks(void){
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;
 // stop clock
 void StopTicks(void){
        AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS;

-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;       
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS;

 }
 
 
 }