CHG: reordered the "hf search" internal checks. The iclass check takes 4.5sec to...

[proxmark3-svn] / include / at91sam7s512.h

diff --git a/include/at91sam7s512.h b/include/at91sam7s512.h
index 7363dd8f5b1c054b96b648d2c4d93883b1b38910..2cdcbce3873b09ed6fea4f7bf6c4c5632f1c0b6e 100644 (file)
--- a/include/at91sam7s512.h
+++ b/include/at91sam7s512.h
@@ -428,7 +428,7 @@ typedef struct _AT91S_PIO {
 #define PIO_PDR         (AT91_CAST(AT91_REG *)         0x00000004) // (PIO_PDR) PIO Disable Register
 #define PIO_PSR         (AT91_CAST(AT91_REG *)         0x00000008) // (PIO_PSR) PIO Status Register
 #define PIO_OER         (AT91_CAST(AT91_REG *)         0x00000010) // (PIO_OER) Output Enable Register
 #define PIO_PDR         (AT91_CAST(AT91_REG *)         0x00000004) // (PIO_PDR) PIO Disable Register
 #define PIO_PSR         (AT91_CAST(AT91_REG *)         0x00000008) // (PIO_PSR) PIO Status Register
 #define PIO_OER         (AT91_CAST(AT91_REG *)         0x00000010) // (PIO_OER) Output Enable Register

-#define PIO_ODR         (AT91_CAST(AT91_REG *)         0x00000014) // (PIO_ODR) Output Disable Registerr
+#define PIO_ODR         (AT91_CAST(AT91_REG *)         0x00000014) // (PIO_ODR) Output Disable Register

 #define PIO_OSR         (AT91_CAST(AT91_REG *)         0x00000018) // (PIO_OSR) Output Status Register
 #define PIO_IFER        (AT91_CAST(AT91_REG *)         0x00000020) // (PIO_IFER) Input Filter Enable Register
 #define PIO_IFDR        (AT91_CAST(AT91_REG *)         0x00000024) // (PIO_IFDR) Input Filter Disable Register
 #define PIO_OSR         (AT91_CAST(AT91_REG *)         0x00000018) // (PIO_OSR) Output Status Register
 #define PIO_IFER        (AT91_CAST(AT91_REG *)         0x00000020) // (PIO_IFER) Input Filter Enable Register
 #define PIO_IFDR        (AT91_CAST(AT91_REG *)         0x00000024) // (PIO_IFDR) Input Filter Disable Register


@@ -1415,7 +1415,7 @@ typedef struct _AT91S_TC {
 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK       (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK       (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK       (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK       (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK       (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK       (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK

-#define T91C_TC_CLKS_TIMER_DIV4_CLOCK        (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK       (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK

 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK       (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
 #define AT91C_TC_CLKS_XC0                    (0x5) // (TC) Clock selected: XC0
 #define AT91C_TC_CLKS_XC1                    (0x6) // (TC) Clock selected: XC1
 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK       (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
 #define AT91C_TC_CLKS_XC0                    (0x5) // (TC) Clock selected: XC0
 #define AT91C_TC_CLKS_XC1                    (0x6) // (TC) Clock selected: XC1