-// split into two routines so we can avoid timing issues after sending commands //
-void DoAcquisition125k(BOOL at134khz)
-{
- BYTE *dest = (BYTE *)BigBuf;
- int n = sizeof(BigBuf);
- int i;
-
- memset(dest,0,n);
- i = 0;
- for(;;) {
- if(SSC_STATUS & (SSC_STATUS_TX_READY)) {
- SSC_TRANSMIT_HOLDING = 0x43;
- LED_D_ON();
- }
- if(SSC_STATUS & (SSC_STATUS_RX_READY)) {
- dest[i] = (BYTE)SSC_RECEIVE_HOLDING;
- i++;
- LED_D_OFF();
- if(i >= n) {
- break;
- }
- }
- }
- DbpIntegers(dest[0], dest[1], at134khz);
-}
-
-void ModThenAcquireRawAdcSamples125k(int delay_off,int period_0,int period_1,BYTE *command)
-{
- BOOL at134khz;
-
- // see if 'h' was specified
- if(command[strlen(command) - 1] == 'h')
- at134khz= TRUE;
- else
- at134khz= FALSE;
-
- if(at134khz) {
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
- } else {
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
- }
-
- // Give it a bit of time for the resonant antenna to settle.
- SpinDelay(50);
-
- // Now set up the SSC to get the ADC samples that are now streaming at us.
- FpgaSetupSsc();
-
- // now modulate the reader field
- while(*command != '\0' && *command != ' ')
- {
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- LED_D_OFF();
- SpinDelayUs(delay_off);
- if(at134khz) {
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
- } else {
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);
- }
- LED_D_ON();
- if(*(command++) == '0')
- SpinDelayUs(period_0);
- else
- SpinDelayUs(period_1);
- }
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- LED_D_OFF();
- SpinDelayUs(delay_off);
- if(at134khz) {
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_134_KHZ);
- } else {
- FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
- FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_READER | FPGA_LF_READER_USE_125_KHZ);