hw tune:

[proxmark3-svn] / armsrc / appmain.c

diff --git a/armsrc/appmain.c b/armsrc/appmain.c
index e292483b80b5a6634151a11ad5243bf0ff77cf49..6476892235facc30fbf41a32b9636656ebb59d19 100644 (file)
--- a/armsrc/appmain.c
+++ b/armsrc/appmain.c
@@ -135,35 +135,28 @@ void Dbhexdump(int len, uint8_t *d, bool bAsci) {
 // return that.
 //-----------------------------------------------------------------------------
 static int ReadAdc(int ch)
 // return that.
 //-----------------------------------------------------------------------------
 static int ReadAdc(int ch)

-{
-       uint32_t d;
-
-       AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
-       AT91C_BASE_ADC->ADC_MR =
-               ADC_MODE_PRESCALE(63  /* was 32 */) |                                                   // ADC_CLK = MCK / ((63+1) * 2) = 48MHz / 128 = 375kHz
-               ADC_MODE_STARTUP_TIME(1  /* was 16 */) |                                                // Startup Time = (1+1) * 8 / ADC_CLK = 16 / 375kHz = 42,7us     Note: must be > 20us
-               ADC_MODE_SAMPLE_HOLD_TIME(15  /* was 8 */);                                     // Sample & Hold Time SHTIM = 15 / ADC_CLK = 15 / 375kHz = 40us
-
+{      

        // Note: ADC_MODE_PRESCALE and ADC_MODE_SAMPLE_HOLD_TIME are set to the maximum allowed value. 
        // Note: ADC_MODE_PRESCALE and ADC_MODE_SAMPLE_HOLD_TIME are set to the maximum allowed value. 

-       // Both AMPL_LO and AMPL_HI are very high impedance (10MOhm) outputs, the input capacitance of the ADC is 12pF (typical). This results in a time constant
-       // of RC = 10MOhm * 12pF = 120us. Even after the maximum configurable sample&hold time of 40us the input capacitor will not be fully charged. 
+       // AMPL_HI is are high impedance (10MOhm || 1MOhm) output, the input capacitance of the ADC is 12pF (typical). This results in a time constant
+       // of RC = (0.91MOhm) * 12pF = 10.9us. Even after the maximum configurable sample&hold time of 40us the input capacitor will not be fully charged. 

        // 
        // The maths are:
        // If there is a voltage v_in at the input, the voltage v_cap at the capacitor (this is what we are measuring) will be
        //
        // 
        // The maths are:
        // If there is a voltage v_in at the input, the voltage v_cap at the capacitor (this is what we are measuring) will be
        //

-       //       v_cap = v_in * (1 - exp(-RC/SHTIM))  =   v_in * (1 - exp(-3))  =  v_in * 0,95                   (i.e. an error of 5%)
-       // 
-       // Note: with the "historic" values in the comments above, the error was 34%  !!!
-       
-       AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ch);
+       //       v_cap = v_in * (1 - exp(-SHTIM/RC))  =   v_in * (1 - exp(-40us/10.9us))  =  v_in * 0,97                   (i.e. an error of 3%)

 
 

-       AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;
+       AT91C_BASE_ADC->ADC_CR = AT91C_ADC_SWRST;
+       AT91C_BASE_ADC->ADC_MR =
+               ADC_MODE_PRESCALE(63) |                                                 // ADC_CLK = MCK / ((63+1) * 2) = 48MHz / 128 = 375kHz
+               ADC_MODE_STARTUP_TIME(1) |                                              // Startup Time = (1+1) * 8 / ADC_CLK = 16 / 375kHz = 42,7us     Note: must be > 20us
+               ADC_MODE_SAMPLE_HOLD_TIME(15);                                  // Sample & Hold Time SHTIM = 15 / ADC_CLK = 15 / 375kHz = 40us

 
 

-       while(!(AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ch)))
-               ;
-       d = AT91C_BASE_ADC->ADC_CDR[ch];
+       AT91C_BASE_ADC->ADC_CHER = ADC_CHANNEL(ch);
+       AT91C_BASE_ADC->ADC_CR = AT91C_ADC_START;

 
 

-       return d;
+       while(!(AT91C_BASE_ADC->ADC_SR & ADC_END_OF_CONVERSION(ch))) {};
+       
+       return AT91C_BASE_ADC->ADC_CDR[ch];

 }
 
 int AvgAdc(int ch) // was static - merlok
 }
 
 int AvgAdc(int ch) // was static - merlok


@@ -193,6 +186,8 @@ void MeasureAntennaTuningLfOnly(int *vLf125, int *vLf134, int *peakf, int *peakv
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
        FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
        FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

+       SpinDelay(50);
+       

        for (i=255; i>=19; i--) {
                WDT_HIT();
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);
        for (i=255; i>=19; i--) {
                WDT_HIT();
                FpgaSendCommand(FPGA_CMD_SET_DIVISOR, i);


@@ -201,7 +196,7 @@ void MeasureAntennaTuningLfOnly(int *vLf125, int *vLf134, int *peakf, int *peakv
                if (i==95) *vLf125 = adcval; // voltage at 125Khz
                if (i==89) *vLf134 = adcval; // voltage at 134Khz
 
                if (i==95) *vLf125 = adcval; // voltage at 125Khz
                if (i==89) *vLf134 = adcval; // voltage at 134Khz
 

-               LF_Results[i] = adcval>>8; // scale int to fit in byte for graphing purposes
+               LF_Results[i] = adcval >> 9; // scale int to fit in byte for graphing purposes

                if(LF_Results[i] > peak) {
                        *peakv = adcval;
                        peak = LF_Results[i];
                if(LF_Results[i] > peak) {
                        *peakv = adcval;
                        peak = LF_Results[i];


@@ -249,7 +244,7 @@ void MeasureAntennaTuning(int mode)
                }
        }
 
                }
        }
 

-       cmd_send(CMD_MEASURED_ANTENNA_TUNING, vLf125 | (vLf134<<16), vHf, peakf | (peakv<<16), LF_Results, 256);
+       cmd_send(CMD_MEASURED_ANTENNA_TUNING, vLf125>>1 | (vLf134>>1<<16), vHf, peakf | (peakv>>1<<16), LF_Results, 256);

        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_B_OFF();
        return;
        FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
        LED_B_OFF();
        return;