// The DMA buffer, used to stream samples from the FPGA
uint8_t *dmaBuf = BigBuf_malloc(DMA_BUFFER_SIZE);
- set_tracing(TRUE);
clear_trace();
+ set_tracing(TRUE);
+
iso14a_set_trigger(FALSE);
int lastRxCounter;
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
// Enable and clear the trace
- set_tracing(TRUE);
clear_trace();
+ set_tracing(TRUE);
+
//Use the emulator memory for SIM
uint8_t *emulator = BigBuf_get_EM_addr();
GetParity(trace_data, trace_data_size, parity);
LogTrace(trace_data, trace_data_size, (t2r_time-time_0) << 4, (t2r_time-time_0) << 4, parity, FALSE);
}
- if(!tracing) {
+ if(!tracing)
DbpString("Trace full");
- //break;
- }
}
}
//-----------------------------------------------------------------------------
static void TransmitIClassCommand(const uint8_t *cmd, int len, int *samples, int *wait)
{
- int c;
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
- AT91C_BASE_SSC->SSC_THR = 0x00;
- FpgaSetupSsc();
-
- if (wait)
- {
- if(*wait < 10) *wait = 10;
-
- for(c = 0; c < *wait;) {
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
- AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
- c++;
- }
- if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
- volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
- (void)r;
- }
- WDT_HIT();
- }
+ int c;
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_ISO14443A | FPGA_HF_ISO14443A_READER_MOD);
+ AT91C_BASE_SSC->SSC_THR = 0x00;
+ FpgaSetupSsc();
+
+ if (wait) {
+ if(*wait < 10) *wait = 10;
- }
+ for(c = 0; c < *wait;) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0x00; // For exact timing!
+ c++;
+ }
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ volatile uint32_t r = AT91C_BASE_SSC->SSC_RHR;
+ (void)r;
+ }
+ WDT_HIT();
+ }
+ }
- uint8_t sendbyte;
- bool firstpart = TRUE;
- c = 0;
+ uint8_t sendbyte;
+ bool firstpart = TRUE;
+ c = 0;
for(;;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
}
WDT_HIT();
}
- if (samples) *samples = (c + *wait) << 3;
+ if (samples && wait) *samples = (c + *wait) << 3;
}
{
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
// Reset trace buffer
- set_tracing(TRUE);
clear_trace();
-
+ set_tracing(TRUE);
+
// Setup SSC
FpgaSetupSsc();
// Start from off (no field generated)
while(!BUTTON_PRESS())
{
if (try_once && tryCnt > 5) break;
+
tryCnt++;
+
if(!tracing) {
DbpString("Trace full");
break;