CHG: a better micro second (us) spindely function. At average it has 8-10us delay...

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 1efc2b2bfbc9c5179b6dbbccde4fbe36d96c5f13..09926747d5cf838e06c376889cf86d512754f1e0 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -56,7 +56,7 @@ uint32_t reflect(uint32_t v, int b) {
                        v |=  BITMASK((b-1)-i);
                else
                        v &= ~BITMASK((b-1)-i);
-               t>>=1;
+               t >>= 1;
        }
        return v;
 }
@@ -236,10 +236,11 @@ int BUTTON_HELD(int ms) {
 // attempt at high resolution microsecond timer
 // beware: timer counts in 21.3uS increments (1024/48Mhz)
 void SpinDelayUs(int us) {
-       int ticks = (48*us) >> 10;
+       int ticks = (48 * us) >> 10;
 
        // Borrow a PWM unit for my real-time clock
        AT91C_BASE_PWMC->PWMC_ENA = PWM_CHANNEL(0);
+       
        // 48 MHz / 1024 gives 46.875 kHz
        AT91C_BASE_PWMC_CH0->PWMC_CMR = PWM_CH_MODE_PRESCALER(10);
        AT91C_BASE_PWMC_CH0->PWMC_CDTYR = 0;
@@ -340,10 +341,12 @@ void StartCountUS() {
        AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
        AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
        
-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
        AT91C_BASE_TCB->TCB_BCR = 1;
-       }
+       
+       while (AT91C_BASE_TC1->TC_CV >= 1);
+}
 
 uint32_t RAMFUNC GetCountUS(){
        //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
@@ -351,7 +354,22 @@ uint32_t RAMFUNC GetCountUS(){
        //return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV * 2) / 3); 
        return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV << 1) / 3); 
 }
+void ResetUSClock(void) {      
+       //enable clock of timer and software trigger
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       while (AT91C_BASE_TC1->TC_CV >= 1);
+}
+// attempt at high resolution microsecond timer
+// beware: timer counts in 21.3uS increments (1024/48Mhz)
+void SpinDelayCountUs(uint32_t us) {
 
+       us += GetCountUS();
+       us -= 6;
+       
+       for(;;)
+               if ( GetCountUS() >= us ) return;
+}
 // static uint32_t GlobalUsCounter = 0;
 
 // uint32_t RAMFUNC GetDeltaCountUS(){
@@ -400,9 +418,9 @@ void StartCountSspClk() {
                                                        | AT91C_TC_WAVE                                 // Waveform Mode
                                                        | AT91C_TC_WAVESEL_UP;                  // just count
 
-       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;                                // enable TC0
-       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;                                // enable TC1
-       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN;                                // enable TC2
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC0
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC1
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;                               // enable and reset TC2
 
        // synchronize the counter with the ssp_frame signal. 
        // Note: FPGA must be in any iso14443 mode, otherwise the frame signal would not be present 
@@ -420,7 +438,13 @@ void StartCountSspClk() {
 
        // The high word of the counter (TC2) will not reset until the low word (TC0) overflows. 
        // Therefore need to wait quite some time before we can use the counter.
-       while (AT91C_BASE_TC0->TC_CV < 0xFFF0);
+       while (AT91C_BASE_TC2->TC_CV >= 1);
+}
+void ResetSspClk(void) {       
+       //enable clock of timer and software trigger
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
+       AT91C_BASE_TC2->TC_CCR = AT91C_TC_CLKEN | AT91C_TC_SWTRG;
 }
 
 uint32_t RAMFUNC GetCountSspClk(){