Merge branch 'master' of https://github.com/Proxmark/proxmark3

[proxmark3-svn] / armsrc / lfops.c

diff --git a/armsrc/lfops.c b/armsrc/lfops.c
index f5040850c50cd2b1f93dfdf979bdbd74b463cfe2..fabede413db7e891cd01f37562c70cb39ec34b02 100644 (file)
--- a/armsrc/lfops.c
+++ b/armsrc/lfops.c
@@ -15,130 +15,44 @@
 #include "crc16.h"
 #include "string.h"
 #include "lfdemod.h"
 #include "crc16.h"
 #include "string.h"
 #include "lfdemod.h"

+#include "lfsampling.h"

 
 
 /**
 
 
 /**

-* Does the sample acquisition. If threshold is specified, the actual sampling
-* is not commenced until the threshold has been reached.
-* @param trigger_threshold - the threshold
-* @param silent - is true, now outputs are made. If false, dbprints the status
-*/
-void DoAcquisition125k_internal(int trigger_threshold,bool silent)
-{
-    uint8_t *dest = (uint8_t *)BigBuf;
-    int n = sizeof(BigBuf);
-    int i;
-
-    memset(dest, 0, n);
-    i = 0;
-    for(;;) {
-        if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
-            AT91C_BASE_SSC->SSC_THR = 0x43;
-            LED_D_ON();
-        }
-        if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
-            dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
-            LED_D_OFF();
-            if (trigger_threshold != -1 && dest[i] < trigger_threshold)
-                continue;
-            else
-                trigger_threshold = -1;
-            if (++i >= n) break;
-        }
-    }
-    if(!silent)
-    {
-        Dbprintf("buffer samples: %02x %02x %02x %02x %02x %02x %02x %02x ...",
-                 dest[0], dest[1], dest[2], dest[3], dest[4], dest[5], dest[6], dest[7]);
-
-    }
-}
-/**
-* Perform sample aquisition.
-*/
-void DoAcquisition125k(int trigger_threshold)
-{
-    DoAcquisition125k_internal(trigger_threshold, false);
-}
-
-/**
-* Setup the FPGA to listen for samples. This method downloads the FPGA bitstream
-* if not already loaded, sets divisor and starts up the antenna.
-* @param divisor : 1, 88> 255 or negative ==> 134.8 KHz
-*                                 0 or 95 ==> 125 KHz
-*
-**/
-void LFSetupFPGAForADC(int divisor, bool lf_field)
-{
-    FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-    if ( (divisor == 1) || (divisor < 0) || (divisor > 255) )
-        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 88); //134.8Khz
-    else if (divisor == 0)
-        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-    else
-        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor);
-
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | (lf_field ? FPGA_LF_ADC_READER_FIELD : 0));
-
-    // Connect the A/D to the peak-detected low-frequency path.
-    SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-    // Give it a bit of time for the resonant antenna to settle.
-    SpinDelay(50);
-    // Now set up the SSC to get the ADC samples that are now streaming at us.
-    FpgaSetupSsc();
-}
-/**
-* Initializes the FPGA, and acquires the samples.
-**/
-void AcquireRawAdcSamples125k(int divisor)
-{
-    LFSetupFPGAForADC(divisor, true);
-    // Now call the acquisition routine
-    DoAcquisition125k_internal(-1,false);
-}
-/**
-* Initializes the FPGA for snoop-mode, and acquires the samples.
-**/
-
-void SnoopLFRawAdcSamples(int divisor, int trigger_threshold)
-{
-    LFSetupFPGAForADC(divisor, false);
-    DoAcquisition125k(trigger_threshold);
-}
-
+ * Function to do a modulation and then get samples.
+ * @param delay_off
+ * @param period_0
+ * @param period_1
+ * @param command
+ */

 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {
 
 void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1, uint8_t *command)
 {
 

-    /* Make sure the tag is reset */
-    FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
-    SpinDelay(2500);
-
-

     int divisor_used = 95; // 125 KHz
     // see if 'h' was specified
 
     if (command[strlen((char *) command) - 1] == 'h')
         divisor_used = 88; // 134.8 KHz
 
     int divisor_used = 95; // 125 KHz
     // see if 'h' was specified
 
     if (command[strlen((char *) command) - 1] == 'h')
         divisor_used = 88; // 134.8 KHz
 

+       sample_config sc = { 0,0,1, divisor_used, 0};
+       setSamplingConfig(&sc);

 
 

-    FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
-    // Give it a bit of time for the resonant antenna to settle.
-    SpinDelay(50);
+    /* Make sure the tag is reset */
+    FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
+    FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+    SpinDelay(2500);
+
+       LFSetupFPGAForADC(sc.divisor, 1);

 
     // And a little more time for the tag to fully power up
     SpinDelay(2000);
 
 
     // And a little more time for the tag to fully power up
     SpinDelay(2000);
 

-    // Now set up the SSC to get the ADC samples that are now streaming at us.
-    FpgaSetupSsc();
-

     // now modulate the reader field
     while(*command != '\0' && *command != ' ') {
         FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
         LED_D_OFF();
         SpinDelayUs(delay_off);
     // now modulate the reader field
     while(*command != '\0' && *command != ' ') {
         FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
         LED_D_OFF();
         SpinDelayUs(delay_off);

-        FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
+               FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);

 
         FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
         LED_D_ON();
 
         FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
         LED_D_ON();


@@ -150,12 +64,12 @@ void ModThenAcquireRawAdcSamples125k(int delay_off, int period_0, int period_1,
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
     LED_D_OFF();
     SpinDelayUs(delay_off);
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
     LED_D_OFF();
     SpinDelayUs(delay_off);

-    FpgaSendCommand(FPGA_CMD_SET_DIVISOR, divisor_used);
+       FpgaSendCommand(FPGA_CMD_SET_DIVISOR, sc.divisor);

 
     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
     // now do the read
 
     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
 
     // now do the read

-    DoAcquisition125k(-1);
+       DoAcquisition_config(false);

 }
 
 /* blank r/w tag data stream
 }
 
 /* blank r/w tag data stream


@@ -177,8 +91,8 @@ void ReadTItag(void)
  #define FREQLO 123200
  #define FREQHI 134200
 
  #define FREQLO 123200
  #define FREQHI 134200
 

-    signed char *dest = (signed char *)BigBuf;
-    int n = sizeof(BigBuf);
+    signed char *dest = (signed char *)BigBuf_get_addr();
+    uint16_t n = BigBuf_max_traceLen();

     // 128 bit shift register [shift3:shift2:shift1:shift0]
     uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
 
     // 128 bit shift register [shift3:shift2:shift1:shift0]
     uint32_t shift3 = 0, shift2 = 0, shift1 = 0, shift0 = 0;
 


@@ -330,7 +244,8 @@ void AcquireTiType(void)
  #define TIBUFLEN 1250
 
     // clear buffer
  #define TIBUFLEN 1250
 
     // clear buffer

-    memset(BigBuf,0,sizeof(BigBuf));
+       uint32_t *BigBuf = (uint32_t *)BigBuf_get_addr();
+    memset(BigBuf,0,BigBuf_max_traceLen()/sizeof(uint32_t));

 
     // Set up the synchronous serial port
     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;
 
     // Set up the synchronous serial port
     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DIN;


@@ -378,7 +293,7 @@ void AcquireTiType(void)
     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
 
     AT91C_BASE_PIOA->PIO_PDR = GPIO_SSC_DOUT;
     AT91C_BASE_PIOA->PIO_ASR = GPIO_SSC_DIN | GPIO_SSC_DOUT;
 

-    char *dest = (char *)BigBuf;
+    char *dest = (char *)BigBuf_get_addr();

     n = TIBUFLEN*32;
     // unpack buffer
     for (i=TIBUFLEN-1; i>=0; i--) {
     n = TIBUFLEN*32;
     // unpack buffer
     for (i=TIBUFLEN-1; i>=0; i--) {


@@ -464,10 +379,10 @@ void WriteTItag(uint32_t idhi, uint32_t idlo, uint16_t crc)
     DbpString("Now use tiread to check");
 }
 
     DbpString("Now use tiread to check");
 }
 

-void SimulateTagLowFrequency(int period, int gap, int ledcontrol)
+void SimulateTagLowFrequency(uint16_t period, uint32_t gap, uint8_t ledcontrol)

 {
     int i;
 {
     int i;

-    uint8_t *tab = (uint8_t *)BigBuf;
+    uint8_t *tab = BigBuf_get_addr();

 
     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);
 
     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_EDGE_DETECT);


@@ -527,7 +442,7 @@ void SimulateTagLowFrequencyBidir(int divisor, int t0)
 
 // compose fc/8 fc/10 waveform
 static void fc(int c, int *n) {
 
 // compose fc/8 fc/10 waveform
 static void fc(int c, int *n) {

-    uint8_t *dest = (uint8_t *)BigBuf;
+    uint8_t *dest = BigBuf_get_addr();

     int idx;
 
     // for when we want an fc8 pattern every 4 logical bits
     int idx;
 
     // for when we want an fc8 pattern every 4 logical bits


@@ -631,11 +546,11 @@ void CmdHIDsimTAG(int hi, int lo, int ledcontrol)
 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 {
 // loop to get raw HID waveform then FSK demodulate the TAG ID from it
 void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 {

-    uint8_t *dest = (uint8_t *)BigBuf;
-
-    size_t size=0; //, found=0;
+    uint8_t *dest = BigBuf_get_addr();
+    const size_t sizeOfBigBuff = BigBuf_max_traceLen();
+    size_t size = 0; 

     uint32_t hi2=0, hi=0, lo=0;
     uint32_t hi2=0, hi=0, lo=0;

-
+    int idx=0;

     // Configure to go in 125Khz listen mode
     LFSetupFPGAForADC(95, true);
 
     // Configure to go in 125Khz listen mode
     LFSetupFPGAForADC(95, true);
 


@@ -644,13 +559,12 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
         WDT_HIT();
         if (ledcontrol) LED_A_ON();
 
         WDT_HIT();
         if (ledcontrol) LED_A_ON();
 

-        DoAcquisition125k_internal(-1,true);
+               DoAcquisition_default(-1,true);

         // FSK demodulator
         // FSK demodulator

-               size = HIDdemodFSK(dest, sizeof(BigBuf), &hi2, &hi, &lo);
-
-        WDT_HIT();
-
-               if (size>0 && lo>0){
+        size = sizeOfBigBuff;  //variable size will change after demod so re initialize it before use
+               idx = HIDdemodFSK(dest, &size, &hi2, &hi, &lo);
+        
+               if (idx>0 && lo>0){

             // final loop, go over previously decoded manchester data and decode into usable tag ID
             // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
             if (hi2 != 0){ //extra large HID tags
             // final loop, go over previously decoded manchester data and decode into usable tag ID
             // 111000 bit pattern represent start of frame, 01 pattern represents a 1 and 10 represents a 0
             if (hi2 != 0){ //extra large HID tags


@@ -706,6 +620,8 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
             }
             if (findone){
                 if (ledcontrol)        LED_A_OFF();
             }
             if (findone){
                 if (ledcontrol)        LED_A_OFF();

+                *high = hi;
+                *low = lo;

                 return;
             }
             // reset
                 return;
             }
             // reset


@@ -719,10 +635,10 @@ void CmdHIDdemodFSK(int findone, int *high, int *low, int ledcontrol)
 
 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
 {
 
 void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
 {

-    uint8_t *dest = (uint8_t *)BigBuf;
+    uint8_t *dest = BigBuf_get_addr();

 
 

-       size_t size=0;
-    int clk=0, invert=0, errCnt=0;
+       size_t size=0, idx=0;
+    int clk=0, invert=0, errCnt=0, maxErr=20;

     uint64_t lo=0;
     // Configure to go in 125Khz listen mode
     LFSetupFPGAForADC(95, true);
     uint64_t lo=0;
     // Configure to go in 125Khz listen mode
     LFSetupFPGAForADC(95, true);


@@ -732,16 +648,16 @@ void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
         WDT_HIT();
         if (ledcontrol) LED_A_ON();
 
         WDT_HIT();
         if (ledcontrol) LED_A_ON();
 

-        DoAcquisition125k_internal(-1,true);
-        size  = sizeof(BigBuf);
+               DoAcquisition_default(-1,true);
+        size  = BigBuf_max_traceLen();

         //Dbprintf("DEBUG: Buffer got");
                //askdemod and manchester decode
         //Dbprintf("DEBUG: Buffer got");
                //askdemod and manchester decode

-               errCnt = askmandemod(dest, &size, &clk, &invert);
+               errCnt = askmandemod(dest, &size, &clk, &invert, maxErr);

         //Dbprintf("DEBUG: ASK Got");
         WDT_HIT();
 
         if (errCnt>=0){
         //Dbprintf("DEBUG: ASK Got");
         WDT_HIT();
 
         if (errCnt>=0){

-                       lo = Em410xDecode(dest,size);
+                       lo = Em410xDecode(dest, &size, &idx);

             //Dbprintf("DEBUG: EM GOT");
             if (lo>0){
                                Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",
             //Dbprintf("DEBUG: EM GOT");
             if (lo>0){
                                Dbprintf("EM TAG ID: %02x%08x - (%05d_%03d_%08d)",


@@ -753,6 +669,8 @@ void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
             }
             if (findone){
                 if (ledcontrol)        LED_A_OFF();
             }
             if (findone){
                 if (ledcontrol)        LED_A_OFF();

+                *high=lo>>32;
+                *low=lo & 0xFFFFFFFF;

                 return;
             }
         } else{
                 return;
             }
         } else{


@@ -771,7 +689,7 @@ void CmdEM410xdemod(int findone, int *high, int *low, int ledcontrol)
 
 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 {
 
 void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
 {

-    uint8_t *dest = (uint8_t *)BigBuf;
+    uint8_t *dest = BigBuf_get_addr();

     int idx=0;
     uint32_t code=0, code2=0;
     uint8_t version=0;
     int idx=0;
     uint32_t code=0, code2=0;
     uint8_t version=0;


@@ -783,10 +701,10 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
     while(!BUTTON_PRESS()) {
         WDT_HIT();
         if (ledcontrol) LED_A_ON();
     while(!BUTTON_PRESS()) {
         WDT_HIT();
         if (ledcontrol) LED_A_ON();

-        DoAcquisition125k_internal(-1,true);
+               DoAcquisition_default(-1,true);

         //fskdemod and get start index
         WDT_HIT();
         //fskdemod and get start index
         WDT_HIT();

-        idx = IOdemodFSK(dest,sizeof(BigBuf));
+        idx = IOdemodFSK(dest, BigBuf_max_traceLen());

         if (idx>0){
             //valid tag found
 
         if (idx>0){
             //valid tag found
 


@@ -819,6 +737,8 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
             if (findone){
                 if (ledcontrol)        LED_A_OFF();
                 //LED_A_OFF();
             if (findone){
                 if (ledcontrol)        LED_A_OFF();
                 //LED_A_OFF();

+                *high=code;
+                *low=code2;

                 return;
             }
             code=code2=0;
                 return;
             }
             code=code2=0;


@@ -891,10 +811,20 @@ void CmdIOdemodFSK(int findone, int *high, int *low, int ledcontrol)
  * To compensate antenna falling times shorten the write times
  * and enlarge the gap ones.
  */
  * To compensate antenna falling times shorten the write times
  * and enlarge the gap ones.
  */

-#define START_GAP 250
-#define WRITE_GAP 160
-#define WRITE_0   144 // 192
-#define WRITE_1   400 // 432 for T55x7; 448 for E5550
+#define START_GAP 30*8 // 10 - 50fc 250
+#define WRITE_GAP 20*8 //  8 - 30fc
+#define WRITE_0   24*8 // 16 - 31fc 24fc 192
+#define WRITE_1   54*8 // 48 - 63fc 54fc 432 for T55x7; 448 for E5550
+
+//  VALUES TAKEN FROM EM4x function: SendForward
+//  START_GAP = 440;       (55*8) cycles at 125Khz (8us = 1cycle)
+//  WRITE_GAP = 128;       (16*8)
+//  WRITE_1   = 256 32*8;  (32*8) 
+
+//  These timings work for 4469/4269/4305 (with the 55*8 above)
+//  WRITE_0 = 23*8 , 9*8  SpinDelayUs(23*8); 
+
+#define T55xx_SAMPLES_SIZE             12000 // 32 x 32 x 10  (32 bit times numofblock (7), times clock skip..)

 
 // Write one bit to card
 void T55xxWriteBit(int bit)
 
 // Write one bit to card
 void T55xxWriteBit(int bit)


@@ -902,7 +832,7 @@ void T55xxWriteBit(int bit)
     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
     FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
     FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
     FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

-    if (bit == 0)
+       if (!bit)

         SpinDelayUs(WRITE_0);
     else
         SpinDelayUs(WRITE_1);
         SpinDelayUs(WRITE_0);
     else
         SpinDelayUs(WRITE_1);


@@ -913,16 +843,11 @@ void T55xxWriteBit(int bit)
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {
 // Write one card block in page 0, no lock
 void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {

-    //unsigned int i;  //enio adjustment 12/10/14
-    uint32_t i;
-
-    FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-    FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       uint32_t i = 0;

 
 

-    // Give it a bit of time for the resonant antenna to settle.
-    // And for the tag to fully power up
-    SpinDelay(150);
+       // Set up FPGA, 125kHz
+       // Wait for config.. (192+8190xPOW)x8 == 67ms
+       LFSetupFPGAForADC(0, true);

 
     // Now start writting
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
 
     // Now start writting
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);


@@ -958,27 +883,17 @@ void T55xxWriteBlock(uint32_t Data, uint32_t Block, uint32_t Pwd, uint8_t PwdMod
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {
 // Read one card block in page 0
 void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
 {

-    uint8_t *dest = (uint8_t *)BigBuf;
-    //int m=0, i=0; //enio adjustment 12/10/14
-    uint32_t m=0, i=0;
-    FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-    m = sizeof(BigBuf);
-    // Clear destination buffer before sending the command
-    memset(dest, 128, m);
-    // Connect the A/D to the peak-detected low-frequency path.
-    SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-    // Now set up the SSC to get the ADC samples that are now streaming at us.
-    FpgaSetupSsc();
-
-    LED_D_ON();
-    FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
-
-    // Give it a bit of time for the resonant antenna to settle.
-    // And for the tag to fully power up
-    SpinDelay(150);
-
-    // Now start writting
+    uint32_t i = 0;
+    uint8_t *dest = BigBuf_get_addr();
+    uint16_t bufferlength = BigBuf_max_traceLen();
+       if ( bufferlength > T55xx_SAMPLES_SIZE )
+               bufferlength = T55xx_SAMPLES_SIZE;
+
+       memset(dest, 0x80, bufferlength);
+       
+       // Set up FPGA, 125kHz
+       // Wait for config.. (192+8190xPOW)x8 == 67ms
+       LFSetupFPGAForADC(0, true);

     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
     SpinDelayUs(START_GAP);
 
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
     SpinDelayUs(START_GAP);
 


@@ -997,53 +912,40 @@ void T55xxReadBlock(uint32_t Block, uint32_t Pwd, uint8_t PwdMode)
         T55xxWriteBit(Block & i);
 
     // Turn field on to read the response
         T55xxWriteBit(Block & i);
 
     // Turn field on to read the response

-    FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       TurnReadLFOn();

 
     // Now do the acquisition
     i = 0;
     for(;;) {
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
             AT91C_BASE_SSC->SSC_THR = 0x43;
 
     // Now do the acquisition
     i = 0;
     for(;;) {
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
             AT91C_BASE_SSC->SSC_THR = 0x43;

+                       LED_D_ON();

         }
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
         }
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-            // we don't care about actual value, only if it's more or less than a
-            // threshold essentially we capture zero crossings for later analysis
-            //                 if(dest[i] < 127) dest[i] = 0; else dest[i] = 1;
-            i++;
-            if (i >= m) break;
+                       ++i;
+                       LED_D_OFF();
+                       if (i >= bufferlength) break;

         }
     }
 
         }
     }
 

+       cmd_send(CMD_ACK,0,0,0,0,0);

     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
     LED_D_OFF();
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
     LED_D_OFF();

-    DbpString("DONE!");

 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){
 }
 
 // Read card traceability data (page 1)
 void T55xxReadTrace(void){

-    uint8_t *dest = (uint8_t *)BigBuf;
-    int m=0, i=0;
-
-    FpgaDownloadAndGo(FPGA_BITSTREAM_LF);
-    m = sizeof(BigBuf);
-    // Clear destination buffer before sending the command
-    memset(dest, 128, m);
-    // Connect the A/D to the peak-detected low-frequency path.
-    SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
-    // Now set up the SSC to get the ADC samples that are now streaming at us.
-    FpgaSetupSsc();
-
-    LED_D_ON();
-    FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);

 
 

-    // Give it a bit of time for the resonant antenna to settle.
-    // And for the tag to fully power up
-    SpinDelay(150);
+       uint32_t i = 0;
+    uint8_t *dest = BigBuf_get_addr();
+    uint16_t bufferlength = BigBuf_max_traceLen();
+       if ( bufferlength > T55xx_SAMPLES_SIZE )
+               bufferlength = T55xx_SAMPLES_SIZE;

 
 

-    // Now start writting
+       memset(dest, 0x80, bufferlength);  
+  
+       LFSetupFPGAForADC(0, true);

     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
     SpinDelayUs(START_GAP);
 
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
     SpinDelayUs(START_GAP);
 


@@ -1052,25 +954,34 @@ void T55xxReadTrace(void){
     T55xxWriteBit(1); //Page 1
 
     // Turn field on to read the response
     T55xxWriteBit(1); //Page 1
 
     // Turn field on to read the response

-    FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
-    FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       TurnReadLFOn();

 
     // Now do the acquisition
 
     // Now do the acquisition

-    i = 0;

     for(;;) {
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
             AT91C_BASE_SSC->SSC_THR = 0x43;
     for(;;) {
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
             AT91C_BASE_SSC->SSC_THR = 0x43;

+                       LED_D_ON();

         }
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
         }
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-            i++;
-            if (i >= m) break;
-        }
-    }
-
+                       ++i;
+                       LED_D_OFF();
+               
+                       if (i >= bufferlength) break;
+               }
+       }
+  
+       cmd_send(CMD_ACK,0,0,0,0,0);

     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
     LED_D_OFF();
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
     LED_D_OFF();

-    DbpString("DONE!");
+}
+
+void TurnReadLFOn(){
+       //FpgaSendCommand(FPGA_CMD_SET_DIVISOR, 95); //125Khz
+       FpgaWriteConfWord(FPGA_MAJOR_MODE_LF_ADC | FPGA_LF_ADC_READER_FIELD);
+       // Give it a bit of time for the resonant antenna to settle.
+       //SpinDelay(30);
+       SpinDelayUs(9*150);

 }
 
 /*-------------- Cloning routines -----------*/
 }
 
 /*-------------- Cloning routines -----------*/


@@ -1377,8 +1288,8 @@ void CopyIndala224toT55x7(int uid1, int uid2, int uid3, int uid4, int uid5, int
 int DemodPCF7931(uint8_t **outBlocks) {
     uint8_t BitStream[256];
     uint8_t Blocks[8][16];
 int DemodPCF7931(uint8_t **outBlocks) {
     uint8_t BitStream[256];
     uint8_t Blocks[8][16];

-    uint8_t *GraphBuffer = (uint8_t *)BigBuf;
-    int GraphTraceLen = sizeof(BigBuf);
+    uint8_t *GraphBuffer = BigBuf_get_addr();
+    int GraphTraceLen = BigBuf_max_traceLen();

     int i, j, lastval, bitidx, half_switch;
     int clock = 64;
     int tolerance = clock / 8;
     int i, j, lastval, bitidx, half_switch;
     int clock = 64;
     int tolerance = clock / 8;


@@ -1388,7 +1299,9 @@ int DemodPCF7931(uint8_t **outBlocks) {
     int lmin=128, lmax=128;
     uint8_t dir;
 
     int lmin=128, lmax=128;
     uint8_t dir;
 

-    AcquireRawAdcSamples125k(0);
+       LFSetupFPGAForADC(95, true);
+       DoAcquisition_default(0, 0);
+

 
     lmin = 64;
     lmax = 192;
 
     lmin = 64;
     lmax = 192;


@@ -1794,9 +1707,14 @@ void EM4xLogin(uint32_t Password) {
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
 
 
 void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
 

+       uint8_t *dest =  BigBuf_get_addr();
+       uint16_t bufferlength = BigBuf_max_traceLen();
+       uint32_t i = 0;
+
+       // Clear destination buffer before sending the command  0x80 = average.
+       memset(dest, 0x80, bufferlength);
+       

     uint8_t fwd_bit_count;
     uint8_t fwd_bit_count;

-    uint8_t *dest = (uint8_t *)BigBuf;
-    int m=0, i=0;

 
     //If password mode do login
     if (PwdMode == 1) EM4xLogin(Pwd);
 
     //If password mode do login
     if (PwdMode == 1) EM4xLogin(Pwd);


@@ -1805,9 +1723,6 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
     fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
     fwd_bit_count += Prepare_Addr( Address );
 
     fwd_bit_count = Prepare_Cmd( FWD_CMD_READ );
     fwd_bit_count += Prepare_Addr( Address );
 

-    m = sizeof(BigBuf);
-    // Clear destination buffer before sending the command
-    memset(dest, 128, m);

     // Connect the A/D to the peak-detected low-frequency path.
     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
     // Now set up the SSC to get the ADC samples that are now streaming at us.
     // Connect the A/D to the peak-detected low-frequency path.
     SetAdcMuxFor(GPIO_MUXSEL_LOPKD);
     // Now set up the SSC to get the ADC samples that are now streaming at us.


@@ -1823,10 +1738,12 @@ void EM4xReadWord(uint8_t Address, uint32_t Pwd, uint8_t PwdMode) {
         }
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;
         }
         if (AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY) {
             dest[i] = (uint8_t)AT91C_BASE_SSC->SSC_RHR;

-            i++;
-            if (i >= m) break;
-        }
-    }
+                       ++i;
+                       if (i >= bufferlength) break;
+               }
+       }
+  
+       cmd_send(CMD_ACK,0,0,0,0,0);

     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
     LED_D_OFF();
 }
     FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF); // field off
     LED_D_OFF();
 }