Attempt to use raw writing capabilities via scripting engine. Not functional yet

[proxmark3-svn] / armsrc / util.c

diff --git a/armsrc/util.c b/armsrc/util.c
index 5a8cfeec72ba0a063cee5ba87f12a6c4b1908431..f2298290246b2174101f9175e3df4d58e768dd9f 100644 (file)
--- a/armsrc/util.c
+++ b/armsrc/util.c
@@ -12,6 +12,19 @@
 #include "util.h"
 #include "string.h"
 
+size_t nbytes(size_t nbits) {
+       return (nbits/8)+((nbits%8)>0);
+}
+
+uint32_t SwapBits(uint32_t value, int nrbits) {
+       int i;
+       uint32_t newvalue = 0;
+       for(i = 0; i < nrbits; i++) {
+               newvalue ^= ((value >> i) & 1) << (nrbits - 1 - i);
+       }
+       return newvalue;
+}
+
 void num_to_bytes(uint64_t n, size_t len, uint8_t* dest)
 {
        while (len--) {
@@ -235,3 +248,69 @@ void FormatVersionInformation(char *dst, int len, const char *prefix, void *vers
        strncat(dst, " ", len);
        strncat(dst, v->buildtime, len);
 }
+
+//  -------------------------------------------------------------------------
+//  timer lib
+//  -------------------------------------------------------------------------
+//  test procedure:
+//
+//     ti = GetTickCount();
+//     SpinDelay(1000);
+//     ti = GetTickCount() - ti;
+//     Dbprintf("timer(1s): %d t=%d", ti, GetTickCount());
+
+void StartTickCount()
+{
+//  must be 0x40, but on my cpu - included divider is optimal
+//  0x20 - 1 ms / bit 
+//  0x40 - 2 ms / bit
+
+       AT91C_BASE_RTTC->RTTC_RTMR = AT91C_RTTC_RTTRST + 0x001D; // was 0x003B
+}
+
+/*
+* Get the current count.
+*/
+uint32_t RAMFUNC GetTickCount(){
+       return AT91C_BASE_RTTC->RTTC_RTVR;// was * 2;
+}
+
+//  -------------------------------------------------------------------------
+//  microseconds timer 
+//  -------------------------------------------------------------------------
+void StartCountUS()
+{
+       AT91C_BASE_PMC->PMC_PCER |= (0x1 << 12) | (0x1 << 13) | (0x1 << 14);
+//     AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC1XC1S_TIOA0;
+       AT91C_BASE_TCB->TCB_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_TIOA0 | AT91C_TCB_TC2XC2S_NONE;
+
+       // fast clock
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKDIS; // timer disable
+       AT91C_BASE_TC0->TC_CMR = AT91C_TC_CLKS_TIMER_DIV3_CLOCK | // MCK(48MHz)/32 -- tick=1.5mks
+                                                                                                               AT91C_TC_WAVE | AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPA_CLEAR |
+                                                                                                               AT91C_TC_ACPC_SET | AT91C_TC_ASWTRG_SET;
+       AT91C_BASE_TC0->TC_RA = 1;
+       AT91C_BASE_TC0->TC_RC = 0xBFFF + 1; // 0xC000
+       
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKDIS; // timer disable  
+       AT91C_BASE_TC1->TC_CMR = AT91C_TC_CLKS_XC1; // from timer 0
+
+       AT91C_BASE_TC0->TC_CCR = AT91C_TC_CLKEN;
+       AT91C_BASE_TC1->TC_CCR = AT91C_TC_CLKEN;
+       AT91C_BASE_TCB->TCB_BCR = 1;
+}
+
+uint32_t RAMFUNC GetCountUS(){
+       return (AT91C_BASE_TC1->TC_CV * 0x8000) + ((AT91C_BASE_TC0->TC_CV / 15) * 10);
+}
+
+static uint32_t GlobalUsCounter = 0;
+
+uint32_t RAMFUNC GetDeltaCountUS(){
+       uint32_t g_cnt = GetCountUS();
+       uint32_t g_res = g_cnt - GlobalUsCounter;
+       GlobalUsCounter = g_cnt;
+       return g_res;
+}
+
+