+ //StartCountSspClk();
+ /* Bitbang the receiver */
+ AT91C_BASE_PIOA->PIO_ODR = GPIO_SSC_DIN;
+ AT91C_BASE_PIOA->PIO_PER = GPIO_SSC_DIN;
+
+ // need a way to determine which tagtype we are simulating
+
+ // hook up emulator memory
+ cardmem = BigBuf_get_EM_addr();
+
+ clear_trace();
+ set_tracing(TRUE);
+
+ crc_init(&legic_crc, 4, 0x19 >> 1, 0x5, 0);
+
+ StartTicks();
+
+ LED_B_ON();
+ DbpString("Starting Legic emulator, press button to end");
+
+ /*
+ * The mode FPGA_HF_SIMULATOR_MODULATE_212K works like this.
+ * - A 1-bit input to the FPGA becomes 8 pulses on 212kHz (fc/64) (18.88us).
+ * - A 0-bit input to the FPGA becomes an unmodulated time of 18.88us
+ *
+ * In this mode the SOF can be written as 00011101 = 0x1D
+ * The EOF can be written as 10111000 = 0xb8
+ * A logic 1 is 01
+ * A logic 0 is 10
+ volatile uint8_t b;
+ uint8_t i = 0;
+ while( !BUTTON_PRESS() ) {
+ WDT_HIT();
+
+ // not sending anything.
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0x00;
+ }
+
+ // receive
+ if ( AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY ) {
+ b = (uint8_t) AT91C_BASE_SSC->SSC_RHR;
+ bd[i] = b;
+ ++i;
+ // if(OutOfNDecoding(b & 0x0f))
+ // *len = Uart.byteCnt;
+ }
+
+ }
+ */
+
+ while(!BUTTON_PRESS() && !usb_poll_validate_length()) {
+
+ level = !!(AT91C_BASE_PIOA->PIO_PDSR & GPIO_SSC_DIN);
+
+ uint32_t time = GET_TICKS;
+
+ if (level != old_level) {
+ if (level == 1) {
+
+ //Dbprintf("start, %u ", time);
+ StartTicks();
+ // did we get a signal
+ if (FUZZ_EQUAL(time, RWD_TIME_1, RWD_TIME_FUZZ)) {
+ // 1 bit
+ emit(1);
+ active = 1;
+ LED_A_ON();
+ } else if (FUZZ_EQUAL(time, RWD_TIME_0, RWD_TIME_FUZZ)) {
+ // 0 bit
+ emit(0);
+ active = 1;
+ LED_A_ON();
+ } else if (active) {
+ // invalid
+ emit(-1);
+ active = 0;
+ LED_A_OFF();
+ }
+ }
+ }
+
+
+ /* Frame end */
+ if(time >= (RWD_TIME_1 + RWD_TIME_FUZZ) && active) {
+ emit(-1);
+ active = 0;
+ LED_A_OFF();
+ }
+
+ /*
+ * Disable the counter, Then wait for the clock to acknowledge the
+ * shutdown in its status register. Reading the SR has the
+ * side-effect of clearing any pending state in there.
+ */
+ //if(time >= (20*RWD_TIME_1) && (timer->TC_SR & AT91C_TC_CLKSTA))
+ if(time >= (20 * RWD_TIME_1) )
+ StopTicks();
+
+ old_level = level;
+ WDT_HIT();
+}
+
+ WDT_HIT();
+ DbpString("LEGIC Prime emulator stopped");
+ switch_off_tag_rwd();
+ FpgaDisableSscDma();
+ LEDsoff();
+ cmd_send(CMD_ACK, 1, 0, 0, 0, 0);
+}
projects / proxmark3-svn / blobdiff