optimization UDOL creation. does not affect on functionality.

[proxmark3-svn] / armsrc / ldscript

diff --git a/armsrc/ldscript b/armsrc/ldscript
index 1f5cf65ef12ab49befb3abb4395694f37b47ee25..34da26bcdfd8cee58e6bfa99cb6bfb4c57eb59af 100644 (file)
--- a/armsrc/ldscript
+++ b/armsrc/ldscript
@@ -11,8 +11,7 @@ INCLUDE ../common/ldscript.common
 
 PHDRS
 {
 
 PHDRS
 {

-       fpgaimage PT_LOAD FLAGS(4);
-       text PT_LOAD;
+       text PT_LOAD FLAGS(5);

        data PT_LOAD;
        bss PT_LOAD;
 }
        data PT_LOAD;
        bss PT_LOAD;
 }


@@ -20,15 +19,12 @@ PHDRS
 ENTRY(Vector)
 SECTIONS
 {
 ENTRY(Vector)
 SECTIONS
 {

-       .fpgaimage : {
-               *(fpga_bit.data)
-       } >fpgaimage :fpgaimage
-

        .start : {
                *(.startos)
        } >osimage :text
 
        .text : {
        .start : {
                *(.startos)
        } >osimage :text
 
        .text : {

+               KEEP(*(stage1_image))

                *(.text)
                *(.text.*)
                *(.eh_frame)
                *(.text)
                *(.text.*)
                *(.eh_frame)


@@ -39,20 +35,23 @@ SECTIONS
        .rodata : {
                *(.rodata)
                *(.rodata.*)
        .rodata : {
                *(.rodata)
                *(.rodata.*)

-               *(.version_information)
+               *(fpga_all_bit.data)
+               KEEP(*(.version_information))
+               . = ALIGN(8);

        } >osimage :text
 
        } >osimage :text
 

-       . = ALIGN(4);
-

        .data : {
        .data : {

+               KEEP(*(compressed_data))

                *(.data)
                *(.data.*)
                *(.data)
                *(.data.*)

+               *(.ramfunc)

                . = ALIGN(4);
        } >ram AT>osimage :data
 
        __data_src_start__ = LOADADDR(.data);
        __data_start__ = ADDR(.data);
        __data_end__ = __data_start__ + SIZEOF(.data);
                . = ALIGN(4);
        } >ram AT>osimage :data
 
        __data_src_start__ = LOADADDR(.data);
        __data_start__ = ADDR(.data);
        __data_end__ = __data_start__ + SIZEOF(.data);

+       __os_size__ = SIZEOF(.text) + SIZEOF(.data) + SIZEOF(.rodata);

        
        .bss : {
                __bss_start__ = .; 
        
        .bss : {
                __bss_start__ = .; 


@@ -60,7 +59,7 @@ SECTIONS
                *(.bss.*) 
                . = ALIGN(4);
                __bss_end__ = .;
                *(.bss.*) 
                . = ALIGN(4);
                __bss_end__ = .;

-       } >ram :bss
+       } >ram AT>ram :bss

 
        .commonarea (NOLOAD) : {
                *(.commonarea)
 
        .commonarea (NOLOAD) : {
                *(.commonarea)