Added undec to un-decimate data on the client side, so we can use all those sweet...

[proxmark3-svn] / armsrc / fpgaloader.c

diff --git a/armsrc/fpgaloader.c b/armsrc/fpgaloader.c
index a719f5edf2fa5f9906f54a067ac57fcf513cbd1f..077b378a918b438cb0dc625642d22a7543eaabbf 100644 (file)
--- a/armsrc/fpgaloader.c
+++ b/armsrc/fpgaloader.c
@@ -1,5 +1,6 @@
 //-----------------------------------------------------------------------------
 // Jonathan Westhues, April 2006
 //-----------------------------------------------------------------------------
 // Jonathan Westhues, April 2006

+// iZsh <izsh at fail0verflow.com>, 2014

 //
 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
 // at your option, any later version. See the LICENSE.txt file for the text of
 //
 // This code is licensed to you under the terms of the GNU GPL, version 2 or,
 // at your option, any later version. See the LICENSE.txt file for the text of


@@ -8,7 +9,6 @@
 // Routines to load the FPGA image, and then to configure the FPGA's major
 // mode once it is configured.
 //-----------------------------------------------------------------------------
 // Routines to load the FPGA image, and then to configure the FPGA's major
 // mode once it is configured.
 //-----------------------------------------------------------------------------

-

 #include "proxmark3.h"
 #include "apps.h"
 #include "util.h"
 #include "proxmark3.h"
 #include "apps.h"
 #include "util.h"


@@ -115,14 +115,12 @@ void FpgaSetupSsc(void)
        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 
        // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync
        AT91C_BASE_SSC->SSC_RCMR = SSC_CLOCK_MODE_SELECT(1) | SSC_CLOCK_MODE_START(1);
 
        // 8 bits per transfer, no loopback, MSB first, 1 transfer per sync

-       // pulse, no output sync, start on positive-going edge of sync
-       AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |
-               AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);
+       // pulse, no output sync
+       AT91C_BASE_SSC->SSC_RFMR = SSC_FRAME_MODE_BITS_IN_WORD(8) |     AT91C_SSC_MSBF | SSC_FRAME_MODE_WORDS_PER_TRANSFER(0);

 
        // clock comes from TK pin, no clock output, outputs change on falling
 
        // clock comes from TK pin, no clock output, outputs change on falling

-       // edge of TK, start on rising edge of TF
-       AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |
-               SSC_CLOCK_MODE_START(5);
+       // edge of TK, sample on rising edge of TK, start on positive-going edge of sync
+       AT91C_BASE_SSC->SSC_TCMR = SSC_CLOCK_MODE_SELECT(2) |   SSC_CLOCK_MODE_START(5);

 
        // tx framing is the same as the rx framing
        AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;
 
        // tx framing is the same as the rx framing
        AT91C_BASE_SSC->SSC_TFMR = AT91C_BASE_SSC->SSC_RFMR;


@@ -142,12 +140,12 @@ bool FpgaSetupSscDma(uint8_t *buf, int len)
         return false;
     }
 
         return false;
     }
 

-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
-       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;
-       AT91C_BASE_PDC_SSC->PDC_RCR = len;
-       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;
-       AT91C_BASE_PDC_SSC->PDC_RNCR = len;
-       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;        // Disable DMA Transfer
+       AT91C_BASE_PDC_SSC->PDC_RPR = (uint32_t) buf;           // transfer to this memory address
+       AT91C_BASE_PDC_SSC->PDC_RCR = len;                                      // transfer this many bytes
+       AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) buf;          // next transfer to same memory address
+       AT91C_BASE_PDC_SSC->PDC_RNCR = len;                                     // ... with same number of bytes
+       AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTEN;         // go!

     
     return true;
 }
     
     return true;
 }


@@ -254,7 +252,7 @@ static void DownloadFPGA(const char *FpgaImage, int FpgaImageLen, int byterevers
 
 static char *bitparse_headers_start;
 static char *bitparse_bitstream_end;
 
 static char *bitparse_headers_start;
 static char *bitparse_bitstream_end;

-static int bitparse_initialized;
+static int bitparse_initialized = 0;

 /* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
  * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
  * After that the format is 1 byte section type (ASCII character), 2 byte length
 /* Simple Xilinx .bit parser. The file starts with the fixed opaque byte sequence
  * 00 09 0f f0 0f f0 0f f0 0f f0 00 00 01
  * After that the format is 1 byte section type (ASCII character), 2 byte length


@@ -324,12 +322,28 @@ int bitparse_find_section(char section_name, char **section_start, unsigned int
 // Find out which FPGA image format is stored in flash, then call DownloadFPGA
 // with the right parameters to download the image
 //-----------------------------------------------------------------------------
 // Find out which FPGA image format is stored in flash, then call DownloadFPGA
 // with the right parameters to download the image
 //-----------------------------------------------------------------------------

-extern char _binary_fpga_bit_start, _binary_fpga_bit_end;
-void FpgaDownloadAndGo(void)
+extern char _binary_fpga_lf_bit_start, _binary_fpga_lf_bit_end;
+extern char _binary_fpga_hf_bit_start, _binary_fpga_hf_bit_end;
+void FpgaDownloadAndGo(int bitstream_version)

 {
 {

+       void *bit_start;
+       void *bit_end;
+
+       // check whether or not the bitstream is already loaded
+       if (FpgaGatherBitstreamVersion() == bitstream_version)
+               return;
+
+       if (bitstream_version == FPGA_BITSTREAM_LF) {
+               bit_start = &_binary_fpga_lf_bit_start;
+               bit_end = &_binary_fpga_lf_bit_end;
+       } else if (bitstream_version == FPGA_BITSTREAM_HF) {
+               bit_start = &_binary_fpga_hf_bit_start;
+               bit_end = &_binary_fpga_hf_bit_end;
+       } else
+               return;

        /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
         */
        /* Check for the new flash image format: Should have the .bit file at &_binary_fpga_bit_start
         */

-       if(bitparse_init(&_binary_fpga_bit_start, &_binary_fpga_bit_end)) {
+       if(bitparse_init(bit_start, bit_end)) {

                /* Successfully initialized the .bit parser. Find the 'e' section and
                 * send its contents to the FPGA.
                 */
                /* Successfully initialized the .bit parser. Find the 'e' section and
                 * send its contents to the FPGA.
                 */


@@ -353,6 +367,17 @@ void FpgaDownloadAndGo(void)
                DownloadFPGA((char*)0x102000, 10524*4, 1);
 }
 
                DownloadFPGA((char*)0x102000, 10524*4, 1);
 }
 

+int FpgaGatherBitstreamVersion()
+{
+       char temp[256];
+       FpgaGatherVersion(temp, sizeof (temp));
+       if (!memcmp("LF", temp, 2))
+               return FPGA_BITSTREAM_LF;
+       else if (!memcmp("HF", temp, 2))
+               return FPGA_BITSTREAM_HF;
+       return FPGA_BITSTREAM_ERR;
+}
+

 void FpgaGatherVersion(char *dst, int len)
 {
        char *fpga_info;
 void FpgaGatherVersion(char *dst, int len)
 {
        char *fpga_info;


@@ -361,13 +386,15 @@ void FpgaGatherVersion(char *dst, int len)
        if(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) {
                strncat(dst, "FPGA image: legacy image without version information", len-1);
        } else {
        if(!bitparse_find_section('e', &fpga_info, &fpga_info_len)) {
                strncat(dst, "FPGA image: legacy image without version information", len-1);
        } else {

-               strncat(dst, "FPGA image built", len-1);

                /* USB packets only have 48 bytes data payload, so be terse */
                /* USB packets only have 48 bytes data payload, so be terse */

-#if 0

                if(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
                if(bitparse_find_section('a', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {

-                       strncat(dst, " from ", len-1);
-                       strncat(dst, fpga_info, len-1);
+                       if (!memcmp("fpga_lf", fpga_info, 7))
+                               strncat(dst, "LF ", len-1);
+                       else if (!memcmp("fpga_hf", fpga_info, 7))
+                               strncat(dst, "HF ", len-1);

                }
                }

+               strncat(dst, "FPGA image built", len-1);
+#if 0

                if(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
                        strncat(dst, " for ", len-1);
                        strncat(dst, fpga_info, len-1);
                if(bitparse_find_section('b', &fpga_info, &fpga_info_len) && fpga_info[fpga_info_len-1] == 0 ) {
                        strncat(dst, " for ", len-1);
                        strncat(dst, fpga_info, len-1);