//-----------------------------------------------------------------------------
#include "iso14443b.h"
-#define RECEIVE_SAMPLES_TIMEOUT 50000
-#define ISO14443B_DMA_BUFFER_SIZE 256
+#ifndef FWT_TIMEOUT_14B
+// defaults to 2000ms
+# define FWT_TIMEOUT_14B 35312
+#endif
+#ifndef ISO14443B_DMA_BUFFER_SIZE
+# define ISO14443B_DMA_BUFFER_SIZE 256
+#endif
+#ifndef RECEIVE_MASK
+# define RECEIVE_MASK (ISO14443B_DMA_BUFFER_SIZE-1)
+#endif
// Guard Time (per 14443-2)
-#define TR0 0
+#ifndef TR0
+# define TR0 0
+#endif
+
// Synchronization time (per 14443-2)
-#define TR1 0
+#ifndef TR1
+# define TR1 0
+#endif
// Frame Delay Time PICC to PCD (per 14443-3 Amendment 1)
-#define TR2 0
+#ifndef TR2
+# define TR2 0
+#endif
// 4sample
#define SEND4STUFFBIT(x) ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);
+//#define SEND4STUFFBIT(x) ToSendStuffBit(x);
+ // iceman, this threshold value, what makes 8 a good amplituted for this IQ values?
+#ifndef SUBCARRIER_DETECT_THRESHOLD
+# define SUBCARRIER_DETECT_THRESHOLD 8
+#endif
+static void iso14b_set_timeout(uint32_t timeout);
+static void iso14b_set_maxframesize(uint16_t size);
static void switch_off(void);
// the block number for the ISO14443-4 PCB (used with APDUs)
static uint8_t pcb_blocknum = 0;
+static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
-static uint32_t iso14b_timeout = RECEIVE_SAMPLES_TIMEOUT;
-// param timeout is in ftw_
-void iso14b_set_timeout(uint32_t timeout) {
- // 9.4395us = 1etu.
- // clock is about 1.5 us
- iso14b_timeout = timeout;
- if(MF_DBGLEVEL >= 2) Dbprintf("ISO14443B Timeout set to %ld fwt", iso14b_timeout);
-}
-
-static void switch_off(void){
- if (MF_DBGLEVEL > 3) Dbprintf("switch_off");
- FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
- SpinDelay(100);
- FpgaDisableSscDma();
- set_tracing(FALSE);
- LEDsoff();
-}
//=============================================================================
// An ISO 14443 Type B tag. We listen for commands from the reader, using
// memset(Demod.output, 0x00, MAX_FRAME_SIZE);
}
+
+/*
+* 9.4395 us = 1 ETU and clock is about 1.5 us
+* 13560000Hz
+* 1000ms/s
+* timeout in ETUs (time to transfer 1 bit, 9.4395 us)
+*
+* Formula to calculate FWT (in ETUs) by timeout (in ms):
+* fwt = 13560000 * 1000 / (8*16) * timeout;
+* Sample: 3sec == 3000ms
+* 13560000 * 1000 / (8*16) * 3000 ==
+* 13560000000 / 384000 = 35312 FWT
+* @param timeout is in frame wait time, fwt, measured in ETUs
+*/
+static void iso14b_set_timeout(uint32_t timeout) {
+ #define MAX_TIMEOUT 40542464 // 13560000Hz * 1000ms / (2^32-1) * (8*16)
+ if(timeout > MAX_TIMEOUT)
+ timeout = MAX_TIMEOUT;
+
+ iso14b_timeout = timeout;
+ if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443B Timeout set to %ld fwt", iso14b_timeout);
+}
+static void iso14b_set_maxframesize(uint16_t size) {
+ if (size > 256)
+ size = MAX_FRAME_SIZE;
+
+ Uart.byteCntMax = size;
+ if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443B Max frame size set to %d bytes", Uart.byteCntMax);
+}
+static void switch_off(void){
+ if (MF_DBGLEVEL > 3) Dbprintf("switch_off");
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
+ SpinDelay(100);
+ FpgaDisableSscDma();
+ set_tracing(FALSE);
+ LEDsoff();
+}
+
void AppendCrc14443b(uint8_t* data, int len) {
ComputeCrc14443(CRC_14443_B, data, len, data+len, data+len+1);
}
* -TO VERIFY THIS BELOW-
* The mode FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK which we use to simulate tag
* works like this:
- * - A 1-bit input to the FPGA becomes 8 pulses at 847.5kHz (9.44µS)
- * - A 0-bit input to the FPGA becomes an unmodulated time of 9.44µS
- *
+ * - A 1-bit input to the FPGA becomes 8 pulses at 847.5kHz (1.18µS / pulse) == 9.44us
+ * - A 0-bit input to the FPGA becomes an unmodulated time of 1.18µS or does it become 8 nonpulses for 9.44us
*
+ * FPGA doesn't seem to work with ETU. It seems to work with pulse / duration instead.
*
* Card sends data ub 847.e kHz subcarrier
- * 848k = 9.44µS = 128 fc
- * 424k = 18.88µS = 256 fc
- * 212k = 37.76µS = 512 fc
- * 106k = 75.52µS = 1024 fc
+ * subcar |duration| FC division
+ * -------+--------+------------
+ * 106kHz | 9.44µS | FC/128
+ * 212kHz | 4.72µS | FC/64
+ * 424kHz | 2.36µS | FC/32
+ * 848kHz | 1.18µS | FC/16
+ * -------+--------+------------
*
* Reader data transmission:
* - no modulation ONES
* Card data transmission
* - TR1
* - SOF
- * - data (each bytes is: 1startbit,8bits, 1stopbit)
+ * - data (each bytes is: 1startbit, 8bits, 1stopbit)
* - CRC_B
* - EOF
*
*
*/
- // ToSendStuffBit, 40 calls
- // 1 ETU = 1startbit, 1stopbit, 8databits == 10bits.
- // 1 ETU = 10 * 4 == 40 stuffbits ( ETU_TAG_BIT )
int i,j;
uint8_t b;
// Send SOF.
// 10-11 ETU * 4times samples ZEROS
for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
+ //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
// 2-3 ETU * 4times samples ONES
for(i = 0; i < 3; i++) { SEND4STUFFBIT(1); }
+ //for(i = 0; i < 3; i++) { ToSendStuffBit(1); }
// data
for(i = 0; i < len; ++i) {
// Start bit
SEND4STUFFBIT(0);
+ //ToSendStuffBit(0);
// Data bits
b = cmd[i];
for(j = 0; j < 8; ++j) {
- if(b & 1) {
- SEND4STUFFBIT(1);
- } else {
- SEND4STUFFBIT(0);
- }
+ // if(b & 1) {
+ // SEND4STUFFBIT(1);
+ // //ToSendStuffBit(1);
+ // } else {
+ // SEND4STUFFBIT(0);
+ // //ToSendStuffBit(0);
+ // }
+ SEND4STUFFBIT( b & 1 );
b >>= 1;
}
// Stop bit
SEND4STUFFBIT(1);
+ //ToSendStuffBit(1);
// Extra Guard bit
// For PICC it ranges 0-18us (1etu = 9us)
SEND4STUFFBIT(1);
+ //ToSendStuffBit(1);
}
// Send EOF.
// 10-11 ETU * 4 sample rate = ZEROS
for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
+ //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
// why this?
for(i = 0; i < 40; i++) { SEND4STUFFBIT(1); }
+ //for(i = 0; i < 40; i++) { ToSendStuffBit(1); }
// Convert from last byte pos to length
++ToSendMax;
* false if we are still waiting for some more
*/
static RAMFUNC int Handle14443bReaderUartBit(uint8_t bit) {
- switch(Uart.state) {
+ switch (Uart.state) {
case STATE_UNSYNCD:
- if(!bit) {
+ if (!bit) {
// we went low, so this could be the beginning of an SOF
Uart.state = STATE_GOT_FALLING_EDGE_OF_SOF;
Uart.posCnt = 0;
case STATE_GOT_FALLING_EDGE_OF_SOF:
Uart.posCnt++;
- if(Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
- if(bit) {
- if(Uart.bitCnt > 9) {
+ if (Uart.posCnt == 2) { // sample every 4 1/fs in the middle of a bit
+ if (bit) {
+ if (Uart.bitCnt > 9) {
// we've seen enough consecutive
// zeros that it's a valid SOF
Uart.posCnt = 0;
Uart.state = STATE_AWAITING_START_BIT;
LED_A_ON(); // Indicate we got a valid SOF
} else {
- // didn't stay down long enough
- // before going high, error
+ // didn't stay down long enough before going high, error
Uart.state = STATE_UNSYNCD;
}
} else {
}
Uart.bitCnt++;
}
- if(Uart.posCnt >= 4) Uart.posCnt = 0;
- if(Uart.bitCnt > 12) {
- // Give up if we see too many zeros without
- // a one, too.
+ if (Uart.posCnt >= 4) Uart.posCnt = 0;
+ if (Uart.bitCnt > 12) {
+ // Give up if we see too many zeros without a one, too.
LED_A_OFF();
Uart.state = STATE_UNSYNCD;
}
case STATE_AWAITING_START_BIT:
Uart.posCnt++;
- if(bit) {
- if(Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
- // stayed high for too long between
- // characters, error
+ if (bit) {
+ if (Uart.posCnt > 50/2) { // max 57us between characters = 49 1/fs, max 3 etus after low phase of SOF = 24 1/fs
+ // stayed high for too long between characters, error
Uart.state = STATE_UNSYNCD;
}
} else {
case STATE_RECEIVING_DATA:
Uart.posCnt++;
- if(Uart.posCnt == 2) {
+ if (Uart.posCnt == 2) {
// time to sample a bit
Uart.shiftReg >>= 1;
- if(bit) {
+ if (bit) {
Uart.shiftReg |= 0x200;
}
Uart.bitCnt++;
}
- if(Uart.posCnt >= 4) {
+ if (Uart.posCnt >= 4) {
Uart.posCnt = 0;
}
- if(Uart.bitCnt == 10) {
- if((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
+ if (Uart.bitCnt == 10) {
+ if ((Uart.shiftReg & 0x200) && !(Uart.shiftReg & 0x001))
{
// this is a data byte, with correct
// start and stop bits
Uart.output[Uart.byteCnt] = (Uart.shiftReg >> 1) & 0xff;
Uart.byteCnt++;
- if(Uart.byteCnt >= Uart.byteCntMax) {
+ if (Uart.byteCnt >= Uart.byteCntMax) {
// Buffer overflowed, give up
LED_A_OFF();
Uart.state = STATE_UNSYNCD;
// this is an EOF byte
LED_A_OFF(); // Finished receiving
Uart.state = STATE_UNSYNCD;
- if (Uart.byteCnt != 0) {
- return TRUE;
- }
+ if (Uart.byteCnt != 0)
+ return TRUE;
+
} else {
// this is an error
LED_A_OFF();
Uart.state = STATE_UNSYNCD;
break;
}
-
return FALSE;
}
// Signal field is off with the appropriate LED
LED_D_OFF();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
-
+
StartCountSspClk();
+ volatile uint8_t b = 0;
+
+ // clear receiving shift register and holding register
+ // What does this loop do? Is it TR1?
+ for(uint8_t c = 0; c < 10;) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ ++c;
+ }
+ }
+
// Now run a `software UART' on the stream of incoming samples.
UartInit(received);
-
- uint8_t mask, b = 0;
+
+ uint8_t mask;
while( !BUTTON_PRESS() ) {
WDT_HIT();
return FALSE;
}
+void ClearFpgaShiftingRegisters(void){
-static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
+ volatile uint8_t b;
- // Signal field is off with the appropriate LED
- LED_D_OFF();
-
- // Modulate BPSK
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
-
- // 8 ETU / 8bits. 8/4= 2 etus.
- AT91C_BASE_SSC->SSC_THR = 0XFF;
+ // clear receiving shift register and holding register
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
- FpgaSetupSsc();
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
- // Transmit the response.
- for(uint16_t i = 0; i < len;) {
- if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
- AT91C_BASE_SSC->SSC_THR = response[i];
- ++i;
- }
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY)) {};
+
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
+
+ // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
+ for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ if (AT91C_BASE_SSC->SSC_RHR) break;
+ }
+
+ // Clear TXRDY:
+ //AT91C_BASE_SSC->SSC_THR = 0xFF;
+}
+
+void WaitForFpgaDelayQueueIsEmpty( uint16_t delay ){
+ // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
+ uint8_t fpga_queued_bits = delay >> 3; // twich /8 ?? >>3,
+ for (uint8_t i = 0; i <= fpga_queued_bits/8 + 1; ) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ i++;
+ }
+ }
+}
+
+static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
+
+ volatile uint32_t b;
+
+ // Signal field is off with the appropriate LED
+ LED_D_OFF();
+ //uint16_t fpgasendQueueDelay = 0;
+
+ // Modulate BPSK
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
+ SpinDelay(40);
+
+ ClearFpgaShiftingRegisters();
+
+ FpgaSetupSsc();
+
+ // Transmit the response.
+ for(uint16_t i = 0; i < len;) {
+ if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
+ AT91C_BASE_SSC->SSC_THR = response[++i];
}
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ b = AT91C_BASE_SSC->SSC_RHR;
+ (void)b;
+ }
+ }
+
+ //WaitForFpgaDelayQueueIsEmpty(fpgasendQueueDelay);
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
}
//-----------------------------------------------------------------------------
// Main loop of simulated tag: receive commands from reader, decide what
// ...PUPI/UID supplied from user. Adjust ATQB response accordingly
if ( pupi > 0 ) {
+ uint8_t len = sizeof(respATQB);
num_to_bytes(pupi, 4, respATQB+1);
- ComputeCrc14443(CRC_14443_B, respATQB, 12, respATQB+13, respATQB+14);
+ ComputeCrc14443(CRC_14443_B, respATQB, 12, &respATQB[len-2], &respATQB[len-1]);
}
// prepare "ATQB" tag answer (encoded):
// REQ or WUP request in ANY state
// WUP in HALTED state
if (len == 5 ) {
- if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE != SIM_HALTED) ||
- (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0) ){
-
- TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
- LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
+ if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE == SIM_HALTED) ||
+ receivedCmd[0] == ISO14443B_REQB ){
+ LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
cardSTATE = SIM_SELECTING;
- continue;
}
}
send halt response ( waiting for wupb )
*/
- switch(cardSTATE){
+ switch (cardSTATE) {
case SIM_NOFIELD:
case SIM_HALTED:
- case SIM_IDLE:{
+ case SIM_IDLE: {
LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
break;
}
case SIM_SELECTING: {
TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
- cardSTATE = SIM_IDLE;
+ cardSTATE = SIM_WORK;
break;
}
case SIM_HALTING: {
cardSTATE = SIM_HALTED;
break;
}
- case SIM_ACKNOWLEDGE:{
+ case SIM_ACKNOWLEDGE: {
TransmitFor14443b_AsTag( encodedOK, encodedOKLen );
LogTrace(respOK, sizeof(respOK), 0, 0, NULL, FALSE);
cardSTATE = SIM_IDLE;
break;
}
- case SIM_WORK:{
+ case SIM_WORK: {
if ( len == 7 && receivedCmd[0] == ISO14443B_HALT ) {
cardSTATE = SIM_HALTED;
} else if ( len == 11 && receivedCmd[0] == ISO14443B_ATTRIB ) {
}
++cmdsReceived;
+ // iceman, could add a switch to turn this on/off (if off, no logging?)
if(cmdsReceived > 1000) {
DbpString("14B Simulate, 1000 commands later...");
break;
* false if we are still waiting for some more
*
*/
-#ifndef SUBCARRIER_DETECT_THRESHOLD
-# define SUBCARRIER_DETECT_THRESHOLD 8
-#endif
-
static RAMFUNC int Handle14443bTagSamplesDemod(int ci, int cq) {
- int v=0;// , myI, myQ = 0;
+ int v = 0, myI = ABS(ci), myQ = ABS(cq);
+
// The soft decision on the bit uses an estimate of just the
// quadrant of the reference angle, not the exact angle.
#define MAKE_SOFT_DECISION() { \
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
-#define CHECK_FOR_SUBCARRIER() { \
+#define CHECK_FOR_SUBCARRIER_old() { \
if(ci < 0) { \
if(cq < 0) { /* ci < 0, cq < 0 */ \
if (cq < ci) { \
}
//note: couldn't we just use MAX(ABS(ci),ABS(cq)) + (MIN(ABS(ci),ABS(cq))/2) from common.h - marshmellow
-#define CHECK_FOR_SUBCARRIER_un() { \
- myI = ABS(ci); \
- myQ = ABS(cq); \
- v = MAX(myI,myQ) + (MIN(myI,myQ) >> 1); \
+#define CHECK_FOR_SUBCARRIER() { \
+ v = MAX(myI, myQ) + (MIN(myI, myQ) >> 1); \
}
switch(Demod.state) {
case DEMOD_UNSYNCD:
CHECK_FOR_SUBCARRIER();
-
+
// subcarrier detected
- if(v > SUBCARRIER_DETECT_THRESHOLD) {
+ if (v > SUBCARRIER_DETECT_THRESHOLD) {
Demod.state = DEMOD_PHASE_REF_TRAINING;
Demod.sumI = ci;
Demod.sumQ = cq;
break;
case DEMOD_PHASE_REF_TRAINING:
- if(Demod.posCount < 8) {
+ if (Demod.posCount < 8) {
CHECK_FOR_SUBCARRIER();
MAKE_SOFT_DECISION();
- if(v < 0) { // logic '0' detected
+ if (v < 0) { // logic '0' detected
Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
Demod.posCount = 0; // start of SOF sequence
} else {
// maximum length of TR1 = 200 1/fs
- if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
+ if(Demod.posCount > 26*2) Demod.state = DEMOD_UNSYNCD;
}
++Demod.posCount;
break;
MAKE_SOFT_DECISION();
- if(v > 0) {
+ if (v > 0) {
// low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
- if(Demod.posCount < 9*2) {
+ if (Demod.posCount < 8*2) {
Demod.state = DEMOD_UNSYNCD;
} else {
LED_C_ON(); // Got SOF
- Demod.startTime = GetCountSspClk();
+ //Demod.startTime = GetCountSspClk();
Demod.state = DEMOD_AWAITING_START_BIT;
Demod.posCount = 0;
Demod.len = 0;
}
} else {
// low phase of SOF too long (> 12 etu)
- if (Demod.posCount > 12*2) {
+ if (Demod.posCount > 14*2) {
Demod.state = DEMOD_UNSYNCD;
LED_C_OFF();
}
MAKE_SOFT_DECISION();
if (v > 0) {
- if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
+ if(Demod.posCount > 2*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
Demod.state = DEMOD_UNSYNCD;
LED_C_OFF();
}
Demod.thisBit += v;
Demod.shiftReg >>= 1;
- // logic '1'
- if(Demod.thisBit > 0) Demod.shiftReg |= 0x200;
+ // OR in a logic '1'
+ if (Demod.thisBit > 0) Demod.shiftReg |= 0x200;
++Demod.bitCount;
- if(Demod.bitCount == 10) {
+ // 1 start 8 data 1 stop = 10
+ if (Demod.bitCount == 10) {
uint16_t s = Demod.shiftReg;
// stop bit == '1', start bit == '0'
- if((s & 0x200) && !(s & 0x001)) {
- uint8_t b = (s >> 1);
- Demod.output[Demod.len] = b;
+ if ((s & 0x200) && (s & 0x001) == 0 ) {
+ // left shift to drop the startbit
+ Demod.output[Demod.len] = (s >> 1) & 0xFF;
++Demod.len;
Demod.state = DEMOD_AWAITING_START_BIT;
} else {
+ // this one is a bit hard, either its a correc byte or its unsynced.
Demod.state = DEMOD_UNSYNCD;
- Demod.endTime = GetCountSspClk();
+ //Demod.endTime = GetCountSspClk();
LED_C_OFF();
// This is EOF (start, stop and all data bits == '0'
- if(s == 0) return TRUE;
+ if (s == 0) return TRUE;
}
}
Demod.posCount = 0;
* quiet: set to 'TRUE' to disable debug output
*/
static void GetTagSamplesFor14443bDemod() {
- bool gotFrame = FALSE;
+ bool gotFrame = FALSE, finished = FALSE;
int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
- int max = 0, ci = 0, cq = 0, samples = 0;
+ int ci = 0, cq = 0;
uint32_t time_0 = 0, time_stop = 0;
BigBuf_free();
if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
return;
}
-
- time_0 = GetCountSspClk();
-
+
// And put the FPGA in the appropriate mode
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
-
- while( !BUTTON_PRESS() ) {
- WDT_HIT();
- int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
- if(behindBy > max) max = behindBy;
+ // get current clock
+ time_0 = GetCountSspClk();
+
+ // rx counter - dma counter? (how much?) & (mod) mask > 2. (since 2bytes at the time is read)
+ while ( !finished ) {
- // rx counter - dma counter? (how much?) & (mod) dma buff / 2. (since 2bytes at the time is read)
- while(((lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1)) > 2) {
+ LED_A_INV();
+ WDT_HIT();
- ci = upTo[0];
- cq = upTo[1];
- upTo += 2;
- samples += 2;
-
- // restart DMA buffer to receive again.
- if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
- upTo = dmaBuf;
- AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
- AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
- }
-
- lastRxCounter -= 2;
- if(lastRxCounter <= 0)
- lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
+ // LSB is a fpga signal bit.
+ ci = upTo[0] >> 1;
+ cq = upTo[1] >> 1;
+ upTo += 2;
+ lastRxCounter -= 2;
- // is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
- //gotFrame = Handle14443bTagSamplesDemod(ci & 0xfe, cq & 0xfe);
- gotFrame = Handle14443bTagSamplesDemod(ci, cq);
- if ( gotFrame ) break;
- LED_A_INV();
+ // restart DMA buffer to receive again.
+ if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
+ upTo = dmaBuf;
+ lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
+ AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
+ AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
}
+ // https://github.com/Proxmark/proxmark3/issues/103
+ gotFrame = Handle14443bTagSamplesDemod(ci, cq);
time_stop = GetCountSspClk() - time_0;
-
- if(time_stop > iso14b_timeout || gotFrame) break;
+
+ finished = (time_stop > iso14b_timeout || gotFrame);
}
FpgaDisableSscDma();
-
+
+ if ( upTo ) upTo = NULL;
+
if (MF_DBGLEVEL >= 3) {
- Dbprintf("max behindby = %d, samples = %d, gotFrame = %s, Demod.state = %d, Demod.len = %u",
- max,
- samples,
- (gotFrame) ? "true" : "false",
+ Dbprintf("Demod.state = %d, Demod.len = %u, PDC_RCR = %u",
Demod.state,
- Demod.len
+ Demod.len,
+ AT91C_BASE_PDC_SSC->PDC_RCR
);
}
+
+ // print the last batch of IQ values from FPGA
+ if (MF_DBGLEVEL == 4)
+ Dbhexdump(ISO14443B_DMA_BUFFER_SIZE, (uint8_t *)dmaBuf, FALSE);
+
if ( Demod.len > 0 )
- LogTrace(Demod.output, Demod.len, Demod.startTime, Demod.endTime, NULL, FALSE);
+ LogTrace(Demod.output, Demod.len, time_0, time_stop, NULL, FALSE);
}
//-----------------------------------------------------------------------------
static void TransmitFor14443b_AsReader(void) {
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
- SpinDelay(20);
-
- int c;
// we could been in following mode:
// FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ
// if its second call or more
+
+ // while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ // AT91C_BASE_SSC->SSC_THR = 0XFF;
+ // }
+
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
+ SpinDelay(40);
+ int c;
+ volatile uint32_t b;
+
// What does this loop do? Is it TR1?
- for(c = 0; c < 10;) {
+ // 0xFF = 8 bits of 1. 1 bit == 1Etu,..
+ // loop 10 * 8 = 80 ETU of delay, with a non modulated signal. why?
+ // 80*9 = 720us.
+ for(c = 0; c < 50;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = 0xFF;
++c;
}
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ b = AT91C_BASE_SSC->SSC_RHR;
+ (void)b;
+ }
}
-
+
// Send frame loop
for(c = 0; c < ToSendMax;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
- AT91C_BASE_SSC->SSC_THR = ToSend[c];
- ++c;
+ AT91C_BASE_SSC->SSC_THR = ToSend[c++];
}
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ b = AT91C_BASE_SSC->SSC_RHR;
+ (void)b;
+ }
}
+ //WaitForFpgaDelayQueueIsEmpty(delay);
+ // We should wait here for the FPGA to send all bits.
WDT_HIT();
}
// Code a layer 2 command (string of octets, including CRC) into ToSend[],
// so that it is ready to transmit to the tag using TransmitFor14443b().
//-----------------------------------------------------------------------------
-static void CodeIso14443bAsReader(const uint8_t *cmd, int len)
-{
+static void CodeIso14443bAsReader(const uint8_t *cmd, int len) {
/*
* Reader data transmission:
* - no modulation ONES
*
* 1 ETU == 1 BIT!
* TR0 - 8 ETUS minimum.
+ *
+ * QUESTION: how long is a 1 or 0 in pulses in the xcorr_848 mode?
+ * 1 "stuffbit" = 1ETU (9us)
*/
int i;
uint8_t b;
ToSendStuffBit(0);
// Data bits
b = cmd[i];
- if ( b & 1 ) ToSendStuffBit(1); else ToSendStuffBit(0);
- if ( (b>>1) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
- if ( (b>>2) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
- if ( (b>>3) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
- if ( (b>>4) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
- if ( (b>>5) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
- if ( (b>>6) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
- if ( (b>>7) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( b & 1 ) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( (b>>1) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( (b>>2) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( (b>>3) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( (b>>4) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( (b>>5) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( (b>>6) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+ // if ( (b>>7) & 1) ToSendStuffBit(1); else ToSendStuffBit(0);
+
+ ToSendStuffBit( b & 1);
+ ToSendStuffBit( (b>>1) & 1);
+ ToSendStuffBit( (b>>2) & 1);
+ ToSendStuffBit( (b>>3) & 1);
+ ToSendStuffBit( (b>>4) & 1);
+ ToSendStuffBit( (b>>5) & 1);
+ ToSendStuffBit( (b>>6) & 1);
+ ToSendStuffBit( (b>>7) & 1);
+
// Stop bit
ToSendStuffBit(1);
// EGT extra guard time
// Transition time. TR0 - guard time
// 8ETUS minum?
// Per specification, Subcarrier must be stopped no later than 2 ETUs after EOF.
- for(i = 0; i < 40 ; ++i) ToSendStuffBit(1);
+ // I'm guessing this is for the FPGA to be able to send all bits before we switch to listening mode
+ for(i = 0; i < 32 ; ++i) ToSendStuffBit(1);
// TR1 - Synchronization time
// Convert from last character reference to length
}
-/**
- Convenience function to encode, transmit and trace iso 14443b comms
- **/
+/*
+* Convenience function to encode, transmit and trace iso 14443b comms
+*/
static void CodeAndTransmit14443bAsReader(const uint8_t *cmd, int len) {
+
+ uint32_t time_start = GetCountSspClk();
CodeIso14443bAsReader(cmd, len);
-
- uint32_t time_start = GetCountSspClk();
TransmitFor14443b_AsReader();
-
+
if(trigger) LED_A_ON();
-
+
LogTrace(cmd, len, time_start, GetCountSspClk()-time_start, NULL, TRUE);
}
ComputeCrc14443(CRC_14443_B, Demod.output, Demod.len-2, &crc[0], &crc[1]);
if ( crc[0] != Demod.output[1] || crc[1] != Demod.output[2] )
return 3;
+
+ if (card) {
- // CID
- if (card) card->cid = Demod.output[0];
-
- uint8_t fwt = card->atqb[6]>>4;
- if ( fwt < 16 ){
- uint32_t fwt_time = (302 << fwt);
- iso14b_set_timeout( fwt_time);
+ // CID
+ card->cid = Demod.output[0];
+
+ // MAX FRAME
+ uint16_t maxFrame = card->atqb[5] >> 4;
+ if (maxFrame < 5) maxFrame = 8 * maxFrame + 16;
+ else if (maxFrame == 5) maxFrame = 64;
+ else if (maxFrame == 6) maxFrame = 96;
+ else if (maxFrame == 7) maxFrame = 128;
+ else if (maxFrame == 8) maxFrame = 256;
+ else maxFrame = 257;
+ iso14b_set_maxframesize(maxFrame);
+
+ // FWT
+ uint8_t fwt = card->atqb[6] >> 4;
+ if ( fwt < 16 ){
+ uint32_t fwt_time = (302 << fwt);
+ iso14b_set_timeout( fwt_time);
+ }
}
// reset PCB block number
pcb_blocknum = 0;
void RAMFUNC SnoopIso14443b(void) {
uint32_t time_0 = 0, time_start = 0, time_stop = 0;
-
+ int ci = 0, cq = 0;
+ int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
+
// We won't start recording the frames that we acquire until we trigger;
// a good trigger condition to get started is probably when we see a
// response from the tag.
- int triggered = TRUE; // TODO: set and evaluate trigger condition
- int ci, cq;
- int maxBehindBy = 0;
- //int behindBy = 0;
- int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
-
+ bool triggered = TRUE; // TODO: set and evaluate trigger condition
bool TagIsActive = FALSE;
bool ReaderIsActive = FALSE;
for(;;) {
WDT_HIT();
-
- int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
- if ( behindBy > maxBehindBy )
- maxBehindBy = behindBy;
-
- if ( behindBy < 2 ) continue;
-
ci = upTo[0];
cq = upTo[1];
- upTo += 2;
-
+ upTo += 2;
lastRxCounter -= 2;
if (upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
upTo = dmaBuf;
- lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
+ lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
- WDT_HIT();
-
- // TODO: understand whether we can increase/decrease as we want or not?
- if ( behindBy > ( 9 * ISO14443B_DMA_BUFFER_SIZE/10) ) {
- Dbprintf("blew circular buffer! behindBy=%d", behindBy);
- break;
- }
-
- if(!tracing) {
- DbpString("Trace full");
+
+ if (!tracing) {
+ if (MF_DBGLEVEL >= 2) DbpString("Trace full");
break;
}
- if(BUTTON_PRESS()) {
- DbpString("cancelled");
+ if (BUTTON_PRESS()) {
+ if (MF_DBGLEVEL >= 2) DbpString("cancelled");
break;
}
}
// no need to try decoding reader data if the tag is sending
if (Handle14443bReaderUartBit(ci & 0x01)) {
- time_stop = (GetCountSspClk()-time_0);
+ time_stop = GetCountSspClk() - time_0;
if (triggered)
LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
/* false-triggered by the commands from the reader. */
DemodReset();
} else {
- time_start = (GetCountSspClk()-time_0);
+ time_start = GetCountSspClk() - time_0;
}
if (Handle14443bReaderUartBit(cq & 0x01)) {
- time_stop = (GetCountSspClk()-time_0);
+ time_stop = GetCountSspClk() - time_0;
if (triggered)
LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
- /* And ready to receive another command. */
- UartReset();
- /* And also reset the demod code, which might have been */
- /* false-triggered by the commands from the reader. */
- DemodReset();
+ /* And ready to receive another command. */
+ UartReset();
+ /* And also reset the demod code, which might have been */
+ /* false-triggered by the commands from the reader. */
+ DemodReset();
} else {
- time_start = (GetCountSspClk()-time_0);
+ time_start = GetCountSspClk() - time_0;
}
ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
LED_A_OFF();
}
- if(!ReaderIsActive) {
+ if (!ReaderIsActive) {
// no need to try decoding tag data if the reader is sending - and we cannot afford the time
// is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
- if(Handle14443bTagSamplesDemod(ci & 0xFE, cq & 0xFE)) {
+ // LSB is a fpga signal bit.
+ if (Handle14443bTagSamplesDemod(ci >> 1, cq >> 1)) {
- time_stop = (GetCountSspClk()-time_0);
+ time_stop = GetCountSspClk() - time_0;
LogTrace(Demod.output, Demod.len, time_start, time_stop, NULL, FALSE);
// And ready to receive another response.
DemodReset();
} else {
- time_start = (GetCountSspClk()-time_0);
+ time_start = GetCountSspClk() - time_0;
}
TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
}
switch_off(); // Snoop
DbpString("Snoop statistics:");
- Dbprintf(" Max behind by: %i", maxBehindBy);
Dbprintf(" Uart State: %x ByteCount: %i ByteCountMax: %i", Uart.state, Uart.byteCnt, Uart.byteCntMax);
Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
// free mem refs.
- if ( dmaBuf ) dmaBuf = NULL;
- if ( upTo ) upTo = NULL;
+ if ( upTo ) upTo = NULL;
+
// Uart.byteCntMax should be set with ATQB value..
}
projects / proxmark3-svn / blobdiff