#include "string.h"
#include "iso14443crc.h"
#include "common.h"
-#define RECEIVE_SAMPLES_TIMEOUT 800000
+#define RECEIVE_SAMPLES_TIMEOUT 600000
#define ISO14443B_DMA_BUFFER_SIZE 256
ToSendStuffBit(0);
ToSendStuffBit(0);
}
- for(i = 0; i < 10; i++) {
+ for(i = 0; i < 2; i++) {
ToSendStuffBit(1);
ToSendStuffBit(1);
ToSendStuffBit(1);
if (tracing) LogTrace(resp, respLen, 0, 0, parity, FALSE);
}
FpgaDisableSscDma();
+ set_tracing(FALSE);
}
//=============================================================================
* false if we are still waiting for some more
*
*/
+ #define abs(x) ( ((x)<0) ? -(x) : (x) )
static RAMFUNC int Handle14443bSamplesDemod(int ci, int cq)
{
- int v;
- int ai, aq;
+ int v = 0;
+ int ai = abs(ci);
+ int aq = abs(cq);
+ int halfci = (ai >> 1);
+ int halfcq = (aq >> 1);
// The soft decision on the bit uses an estimate of just the
// quadrant of the reference angle, not the exact angle.
#define MAKE_SOFT_DECISION() { \
- v = (Demod.sumI > 0) ? ci : -ci;\
+ if(Demod.sumI > 0) { \
+ v = ci; \
+ } else { \
+ v = -ci; \
+ } \
if(Demod.sumQ > 0) { \
v += cq; \
} else { \
#define SUBCARRIER_DETECT_THRESHOLD 8
-// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
-/* #define CHECK_FOR_SUBCARRIER() { \
- v = ci; \
- if(v < 0) v = -v; \
- if(cq > 0) { \
- v += cq; \
- } else { \
- v -= cq; \
- } \
- }
- */
-
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
#define CHECK_FOR_SUBCARRIER() { \
- ai = (abs(ci) >> 1); \
- aq = (abs(cq) >> 1); \
- v = MAX(abs(ci), abs(cq)) + MIN(ai, aq); \
+ v = MAX(ai, aq) + MIN(halfci, halfcq); \
}
break;
case DEMOD_PHASE_REF_TRAINING:
- if(Demod.posCount < 10*2) {
+ if(Demod.posCount < 8) {
+ //if(Demod.posCount < 10*2) {
CHECK_FOR_SUBCARRIER();
if (v > SUBCARRIER_DETECT_THRESHOLD) {
// set the reference phase (will code a logic '1') by averaging over 32 1/fs.
case DEMOD_AWAITING_FALLING_EDGE_OF_SOF:
MAKE_SOFT_DECISION();
//Dbprintf("ICE: %d %d %d %d %d", v, Demod.sumI, Demod.sumQ, ci, cq );
- if(v < 0) { // logic '0' detected
+ if(v <= 0) { // logic '0' detected
Demod.state = DEMOD_GOT_FALLING_EDGE_OF_SOF;
Demod.posCount = 0; // start of SOF sequence
} else {
}
lastRxCounter -= 2;
if(lastRxCounter <= 0) {
- lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
+ lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
}
samples += 2;
// Signal field is on with the appropriate LED
LED_D_ON();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
+
+ //SpinDelay(100);
// Start the timer
//StartCountSspClk();
if (Demod.len == 0) {
DbpString("No response from tag");
+ set_tracing(FALSE);
return;
} else {
Dbprintf("Randomly generated Chip ID (+ 2 byte CRC): %02x %02x %02x",
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
if (Demod.len != 3) {
Dbprintf("Expected 3 bytes from tag, got %d", Demod.len);
+ set_tracing(FALSE);
return;
}
// Check the CRC of the answer:
ComputeCrc14443(CRC_14443_B, Demod.output, 1 , &cmd1[2], &cmd1[3]);
if(cmd1[2] != Demod.output[1] || cmd1[3] != Demod.output[2]) {
DbpString("CRC Error reading select response.");
+ set_tracing(FALSE);
return;
}
// Check response from the tag: should be the same UID as the command we just sent:
if (cmd1[1] != Demod.output[0]) {
Dbprintf("Bad response to SELECT from Tag, aborting: %02x %02x", cmd1[1], Demod.output[0]);
+ set_tracing(FALSE);
return;
}
GetSamplesFor14443bDemod(RECEIVE_SAMPLES_TIMEOUT, TRUE);
if (Demod.len != 10) {
Dbprintf("Expected 10 bytes from tag, got %d", Demod.len);
+ set_tracing(FALSE);
return;
}
// The check the CRC of the answer (use cmd1 as temporary variable):
}
i++;
}
+
+ set_tracing(FALSE);
}
if(!ReaderIsActive) { // no need to try decoding tag data if the reader is sending - and we cannot afford the time
// is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
- if(Handle14443bSamplesDemod(ci | 0x01, cq | 0x01)) {
+ if(Handle14443bSamplesDemod(ci & 0xfe, cq & 0xfe)) {
//Use samples as a time measurement
if(tracing)
}
TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
}
-
}
FpgaDisableSscDma();
LEDsoff();
+ set_tracing(FALSE);
+
AT91C_BASE_PDC_SSC->PDC_PTCR = AT91C_PDC_RXTDIS;
DbpString("Snoop statistics:");
Dbprintf(" Max behind by: %i", maxBehindBy);
if(!powerfield) {
FpgaWriteConfWord(FPGA_MAJOR_MODE_OFF);
FpgaDisableSscDma();
+ set_tracing(FALSE);
LED_D_OFF();
}
}