//-----------------------------------------------------------------------------
#include "iso14443b.h"
-#define RECEIVE_SAMPLES_TIMEOUT 50000
-#define ISO14443B_DMA_BUFFER_SIZE 256
+#ifndef FWT_TIMEOUT_14B
+# define FWT_TIMEOUT_14B 60000
+#endif
+#ifndef ISO14443B_DMA_BUFFER_SIZE
+# define ISO14443B_DMA_BUFFER_SIZE 256
+#endif
+#ifndef RECEIVE_MASK
+# define RECEIVE_MASK (ISO14443B_DMA_BUFFER_SIZE-1)
+#endif
// Guard Time (per 14443-2)
-#define TR0 0
+#ifndef TR0
+# define TR0 0
+#endif
+
// Synchronization time (per 14443-2)
-#define TR1 0
+#ifndef TR1
+# define TR1 0
+#endif
// Frame Delay Time PICC to PCD (per 14443-3 Amendment 1)
-#define TR2 0
+#ifndef TR2
+# define TR2 0
+#endif
+
+// 4sample
+#define SEND4STUFFBIT(x) ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);ToSendStuffBit(x);
+//#define SEND4STUFFBIT(x) ToSendStuffBit(x);
+
static void switch_off(void);
// the block number for the ISO14443-4 PCB (used with APDUs)
static uint8_t pcb_blocknum = 0;
-static uint32_t iso14b_timeout = RECEIVE_SAMPLES_TIMEOUT;
+static uint32_t iso14b_timeout = FWT_TIMEOUT_14B;
// param timeout is in ftw_
void iso14b_set_timeout(uint32_t timeout) {
// 9.4395us = 1etu.
// clock is about 1.5 us
iso14b_timeout = timeout;
- if(MF_DBGLEVEL >= 2) Dbprintf("ISO14443B Timeout set to %ld fwt", iso14b_timeout);
+ if(MF_DBGLEVEL >= 3) Dbprintf("ISO14443B Timeout set to %ld fwt", iso14b_timeout);
}
static void switch_off(void){
*
*/
- // ToSendStuffBit, 40 calls
- // 1 ETU = 1startbit, 1stopbit, 8databits == 10bits.
- // 1 ETU = 10 * 4 == 40 stuffbits ( ETU_TAG_BIT )
int i,j;
uint8_t b;
// Send SOF.
// 10-11 ETU * 4times samples ZEROS
- for(i = 0; i < 10; i++) {
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- }
+ for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
+ //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
// 2-3 ETU * 4times samples ONES
- for(i = 0; i < 3; i++) {
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- }
+ for(i = 0; i < 3; i++) { SEND4STUFFBIT(1); }
+ //for(i = 0; i < 3; i++) { ToSendStuffBit(1); }
// data
for(i = 0; i < len; ++i) {
// Start bit
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
+ SEND4STUFFBIT(0);
+ //ToSendStuffBit(0);
// Data bits
b = cmd[i];
for(j = 0; j < 8; ++j) {
- if(b & 1) {
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
+ if(b & 1) {
+ SEND4STUFFBIT(1);
+ //ToSendStuffBit(1);
} else {
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
+ SEND4STUFFBIT(0);
+ //ToSendStuffBit(0);
}
b >>= 1;
}
// Stop bit
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
+ SEND4STUFFBIT(1);
+ //ToSendStuffBit(1);
// Extra Guard bit
// For PICC it ranges 0-18us (1etu = 9us)
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
+ SEND4STUFFBIT(1);
+ //ToSendStuffBit(1);
}
// Send EOF.
// 10-11 ETU * 4 sample rate = ZEROS
- for(i = 0; i < 10; i++) {
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- ToSendStuffBit(0);
- }
+ for(i = 0; i < 10; i++) { SEND4STUFFBIT(0); }
+ //for(i = 0; i < 10; i++) { ToSendStuffBit(0); }
// why this?
- for(i = 0; i < 40; i++) {
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- ToSendStuffBit(1);
- }
+ for(i = 0; i < 40; i++) { SEND4STUFFBIT(1); }
+ //for(i = 0; i < 40; i++) { ToSendStuffBit(1); }
// Convert from last byte pos to length
++ToSendMax;
// Signal field is off with the appropriate LED
LED_D_OFF();
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_NO_MODULATION);
-
+
StartCountSspClk();
+ volatile uint8_t b;
+
+ // clear receiving shift register and holding register
+ // What does this loop do? Is it TR1?
+ for(uint8_t c = 0; c < 10;) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ ++c;
+ }
+ }
+
// Now run a `software UART' on the stream of incoming samples.
UartInit(received);
-
- uint8_t mask, b = 0;
+
+ b = 0;
+ uint8_t mask;
while( !BUTTON_PRESS() ) {
WDT_HIT();
return FALSE;
}
+void ClearFpgaShiftingRegisters(void){
-static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
+ volatile uint8_t b;
- // Signal field is off with the appropriate LED
- LED_D_OFF();
-
- // Modulate BPSK
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
+ // clear receiving shift register and holding register
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
+
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+
+ b = AT91C_BASE_SSC->SSC_RHR; (void) b;
+
- // 8 ETU / 8bits. 8/4= 2 etus.
- AT91C_BASE_SSC->SSC_THR = 0XFF;
+ // wait for the FPGA to signal fdt_indicator == 1 (the FPGA is ready to queue new data in its delay line)
+ for (uint8_t j = 0; j < 5; j++) { // allow timeout - better late than never
+ while(!(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_RXRDY));
+ if (AT91C_BASE_SSC->SSC_RHR) break;
+ }
+
+ // Clear TXRDY:
+ //AT91C_BASE_SSC->SSC_THR = 0xFF;
+}
+
+void WaitForFpgaDelayQueueIsEmpty( uint16_t delay ){
+ // Ensure that the FPGA Delay Queue is empty before we switch to TAGSIM_LISTEN again:
+ uint8_t fpga_queued_bits = delay >> 3; // twich /8 ?? >>3,
+ for (uint8_t i = 0; i <= fpga_queued_bits/8 + 1; ) {
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
+ i++;
+ }
+ }
+}
- FpgaSetupSsc();
+static void TransmitFor14443b_AsTag( uint8_t *response, uint16_t len) {
- // Transmit the response.
- for(uint16_t i = 0; i < len;) {
- if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
- AT91C_BASE_SSC->SSC_THR = response[i];
- ++i;
- }
+ volatile uint32_t b;
+
+ // Signal field is off with the appropriate LED
+ LED_D_OFF();
+ //uint16_t fpgasendQueueDelay = 0;
+
+ // Modulate BPSK
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_SIMULATOR | FPGA_HF_SIMULATOR_MODULATE_BPSK);
+ SpinDelay(40);
+
+ ClearFpgaShiftingRegisters();
+
+ FpgaSetupSsc();
+
+ // Transmit the response.
+ for(uint16_t i = 0; i < len;) {
+ if(AT91C_BASE_SSC->SSC_SR & AT91C_SSC_TXRDY) {
+ AT91C_BASE_SSC->SSC_THR = response[++i];
}
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ b = AT91C_BASE_SSC->SSC_RHR;
+ (void)b;
+ }
+ }
+
+ //WaitForFpgaDelayQueueIsEmpty(fpgasendQueueDelay);
+ AT91C_BASE_SSC->SSC_THR = 0xFF;
}
//-----------------------------------------------------------------------------
// Main loop of simulated tag: receive commands from reader, decide what
// response to send, and send it.
//-----------------------------------------------------------------------------
void SimulateIso14443bTag(uint32_t pupi) {
- // the only commands we understand is WUPB, AFI=0, Select All, N=1:
- static const uint8_t cmd1[] = { ISO14443B_REQB, 0x00, 0x08, 0x39, 0x73 }; // WUPB
- // ... and REQB, AFI=0, Normal Request, N=1:
- static const uint8_t cmd2[] = { ISO14443B_REQB, 0x00, 0x00, 0x71, 0xFF }; // REQB
- // ... and ATTRIB
- static const uint8_t cmd4[] = { ISO14443B_ATTRIB, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
- // ... if not PUPI/UID is supplied we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
- // supports only 106kBit/s in both directions, max frame size = 32Bytes,
- // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
- uint8_t response1[] = {
- 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19, 0x22,
- 0x00, 0x21, 0x85, 0x5e, 0xd7
- };
- // response to HLTB and ATTRIB
- static const uint8_t response2[] = {0x00, 0x78, 0xF0};
-
- // PUPI/UID supplied
- if ( pupi > 0 ) {
- uint8_t len = sizeof(response1);
- num_to_bytes(pupi, 4, response1+1);
- ComputeCrc14443(CRC_14443_B, response1, len-2, response1+len-2, response1+len-1);
- //print it..
- }
-
- uint16_t len, cmdsRecvd = 0;
- uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
-
- uint8_t *resp1Code;
- uint8_t *resp2Code;
- uint16_t resp1CodeLen, resp2CodeLen;
-
- // uint32_t time_0 = 0;
- // uint32_t t2r_time = 0;
- // uint32_t r2t_time = 0;
-
- int cardSTATE = MFEMUL_NOFIELD;
- int vHf = 0; // in mV
-
+ ///////////// setup device.
FpgaDownloadAndGo(FPGA_BITSTREAM_HF);
// allocate command receive buffer
// Set up the synchronous serial port
FpgaSetupSsc();
+ /////////////
- // prepare the (only one) tag answer:
- CodeIso14443bAsTag(response1, sizeof(response1));
- resp1Code = BigBuf_malloc(ToSendMax);
- resp1CodeLen = ToSendMax;
- memcpy(resp1Code, ToSend, ToSendMax);
+ uint16_t len, cmdsReceived = 0;
+ int cardSTATE = SIM_NOFIELD;
+ int vHf = 0; // in mV
+ // uint32_t time_0 = 0;
+ // uint32_t t2r_time = 0;
+ // uint32_t r2t_time = 0;
+ uint8_t *receivedCmd = BigBuf_malloc(MAX_FRAME_SIZE);
+ // the only commands we understand is WUPB, AFI=0, Select All, N=1:
+// static const uint8_t cmdWUPB[] = { ISO14443B_REQB, 0x00, 0x08, 0x39, 0x73 }; // WUPB
+ // ... and REQB, AFI=0, Normal Request, N=1:
+// static const uint8_t cmdREQB[] = { ISO14443B_REQB, 0x00, 0x00, 0x71, 0xFF }; // REQB
+ // ... and ATTRIB
+// static const uint8_t cmdATTRIB[] = { ISO14443B_ATTRIB, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; // ATTRIB
+
+ // ... if not PUPI/UID is supplied we always respond with ATQB, PUPI = 820de174, Application Data = 0x20381922,
+ // supports only 106kBit/s in both directions, max frame size = 32Bytes,
+ // supports ISO14443-4, FWI=8 (77ms), NAD supported, CID not supported:
+ uint8_t respATQB[] = { 0x50, 0x82, 0x0d, 0xe1, 0x74, 0x20, 0x38, 0x19,
+ 0x22, 0x00, 0x21, 0x85, 0x5e, 0xd7 };
+
+ // response to HLTB and ATTRIB
+ static const uint8_t respOK[] = {0x00, 0x78, 0xF0};
+
+ // ...PUPI/UID supplied from user. Adjust ATQB response accordingly
+ if ( pupi > 0 ) {
+ uint8_t len = sizeof(respATQB);
+ num_to_bytes(pupi, 4, respATQB+1);
+ ComputeCrc14443(CRC_14443_B, respATQB, 12, &respATQB[len-2], &respATQB[len-1]);
+ }
+
+ // prepare "ATQB" tag answer (encoded):
+ CodeIso14443bAsTag(respATQB, sizeof(respATQB));
+ uint8_t *encodedATQB = BigBuf_malloc(ToSendMax);
+ uint16_t encodedATQBLen = ToSendMax;
+ memcpy(encodedATQB, ToSend, ToSendMax);
+
- // prepare the (other) tag answer:
- CodeIso14443bAsTag(response2, sizeof(response2));
- resp2Code = BigBuf_malloc(ToSendMax);
- resp2CodeLen = ToSendMax;
- memcpy(resp2Code, ToSend, ToSendMax);
+ // prepare "OK" tag answer (encoded):
+ CodeIso14443bAsTag(respOK, sizeof(respOK));
+ uint8_t *encodedOK = BigBuf_malloc(ToSendMax);
+ uint16_t encodedOKLen = ToSendMax;
+ memcpy(encodedOK, ToSend, ToSendMax);
-
+ // Simulation loop
while (!BUTTON_PRESS() && !usb_poll_validate_length()) {
WDT_HIT();
// find reader field
- if (cardSTATE == MFEMUL_NOFIELD) {
+ if (cardSTATE == SIM_NOFIELD) {
vHf = (MAX_ADC_HF_VOLTAGE * AvgAdc(ADC_CHAN_HF)) >> 10;
- if ( vHf > MF_MINFIELDV )
- cardSTATE = MFEMUL_IDLE;
+ if ( vHf > MF_MINFIELDV ) {
+ cardSTATE = SIM_IDLE;
+ LED_A_ON();
+ }
}
- if (cardSTATE == MFEMUL_NOFIELD) continue;
+ if (cardSTATE == SIM_NOFIELD) continue;
-
+ // Get reader command
if (!GetIso14443bCommandFromReader(receivedCmd, &len)) {
- Dbprintf("button pressed, received %d commands", cmdsRecvd);
+ Dbprintf("button pressed, received %d commands", cmdsReceived);
break;
}
- // REQ or WUP request in ANY state and WUP in HALTED state
- if (len == 5 && (
- (receivedCmd[0] == ISO14443B_REQB && cardSTATE != MFEMUL_HALTED) ||
- receivedCmd[0] == ISO14443A_CMD_WUPA
- )
- ) {
- TransmitFor14443b_AsTag( resp1Code, resp1CodeLen );
- LogTrace(response1, sizeof(response1), 0, 0, NULL, FALSE);
- cardSTATE = MFEMUL_SELECT1;
- continue;
- }
-
- if ( (len == 5 && memcmp(receivedCmd, cmd1, len) == 0) ||
- (len == 5 && memcmp(receivedCmd, cmd2, len) == 0) ) {
- //WUPB && REQB
- cardSTATE = MFEMUL_SELECT1;
- } else if ( len == 7 && receivedCmd[0] == ISO14443B_HALT ) {
- cardSTATE = MFEMUL_HALTED;
- } else if ( len == sizeof(cmd4) && receivedCmd[0] == ISO14443B_ATTRIB ) {
- cardSTATE = MFEMUL_SELECT2;
- } else {
- // SLOT MARKER command?!?
- // ISO7816?!?
- Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsRecvd);
-
- // CRC Check
- uint8_t b1, b2;
- if (len >= 3){ // if crc exists
- ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
- if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1])
- DbpString("+++CRC fail");
- else
- DbpString("CRC passes");
+ // ISO14443-B protocol states:
+ // REQ or WUP request in ANY state
+ // WUP in HALTED state
+ if (len == 5 ) {
+ if ( (receivedCmd[0] == ISO14443B_REQB && (receivedCmd[2] & 0x8)== 0x8 && cardSTATE == SIM_HALTED) ||
+ receivedCmd[0] == ISO14443B_REQB ){
+ LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
+ cardSTATE = SIM_SELECTING;
}
- cardSTATE = MFEMUL_IDLE;
}
-
- switch(cardSTATE){
- case MFEMUL_NOFIELD:
- case MFEMUL_HALTED:
- case MFEMUL_IDLE:{
+
+ /*
+ * How should this flow go?
+ * REQB or WUPB
+ * send response ( waiting for Attrib)
+ * ATTRIB
+ * send response ( waiting for commands 7816)
+ * HALT
+ send halt response ( waiting for wupb )
+ */
+
+ switch (cardSTATE) {
+ case SIM_NOFIELD:
+ case SIM_HALTED:
+ case SIM_IDLE: {
LogTrace(receivedCmd, len, 0, 0, NULL, TRUE);
break;
}
- case MFEMUL_SELECT1:
- TransmitFor14443b_AsTag( resp1Code, resp1CodeLen );
- LogTrace(response1, sizeof(response1), 0, 0, NULL, FALSE);
- cardSTATE = MFEMUL_WORK;
+ case SIM_SELECTING: {
+ TransmitFor14443b_AsTag( encodedATQB, encodedATQBLen );
+ LogTrace(respATQB, sizeof(respATQB), 0, 0, NULL, FALSE);
+ cardSTATE = SIM_WORK;
+ break;
+ }
+ case SIM_HALTING: {
+ TransmitFor14443b_AsTag( encodedOK, encodedOKLen );
+ LogTrace(respOK, sizeof(respOK), 0, 0, NULL, FALSE);
+ cardSTATE = SIM_HALTED;
break;
- case MFEMUL_SELECT2:
- TransmitFor14443b_AsTag( resp2Code, resp2CodeLen );
- LogTrace(response2, sizeof(response2), 0, 0, NULL, FALSE);
- cardSTATE = MFEMUL_HALTED;
+ }
+ case SIM_ACKNOWLEDGE: {
+ TransmitFor14443b_AsTag( encodedOK, encodedOKLen );
+ LogTrace(respOK, sizeof(respOK), 0, 0, NULL, FALSE);
+ cardSTATE = SIM_IDLE;
break;
- case MFEMUL_WORK:
+ }
+ case SIM_WORK: {
+ if ( len == 7 && receivedCmd[0] == ISO14443B_HALT ) {
+ cardSTATE = SIM_HALTED;
+ } else if ( len == 11 && receivedCmd[0] == ISO14443B_ATTRIB ) {
+ cardSTATE = SIM_ACKNOWLEDGE;
+ } else {
+ // Todo:
+ // - SLOT MARKER
+ // - ISO7816
+ // - emulate with a memory dump
+ Dbprintf("new cmd from reader: len=%d, cmdsRecvd=%d", len, cmdsReceived);
+
+ // CRC Check
+ uint8_t b1, b2;
+ if (len >= 3){ // if crc exists
+ ComputeCrc14443(CRC_14443_B, receivedCmd, len-2, &b1, &b2);
+ if(b1 != receivedCmd[len-2] || b2 != receivedCmd[len-1])
+ DbpString("+++CRC fail");
+ else
+ DbpString("CRC passes");
+ }
+ cardSTATE = SIM_IDLE;
+ }
break;
+ }
+ default: break;
}
- ++cmdsRecvd;
- if(cmdsRecvd > 1000) {
+ ++cmdsReceived;
+ // iceman, could add a switch to turn this on/off (if off, no logging?)
+ if(cmdsReceived > 1000) {
DbpString("14B Simulate, 1000 commands later...");
break;
}
}
if (MF_DBGLEVEL >= 1) Dbprintf("Emulator stopped. Tracing: %d trace length: %d ", tracing, BigBuf_get_traceLen());
-
switch_off(); //simulate
}
* false if we are still waiting for some more
*
*/
+ // iceman, this threshold value, what makes 8 a good amplituted for this IQ values?
#ifndef SUBCARRIER_DETECT_THRESHOLD
-# define SUBCARRIER_DETECT_THRESHOLD 8
+# define SUBCARRIER_DETECT_THRESHOLD 6
#endif
static RAMFUNC int Handle14443bTagSamplesDemod(int ci, int cq) {
- int v=0;// , myI, myQ = 0;
+ int v = 0, myI = 0, myQ = 0;
// The soft decision on the bit uses an estimate of just the
// quadrant of the reference angle, not the exact angle.
#define MAKE_SOFT_DECISION() { \
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by abs(ci) + abs(cq)
// Subcarrier amplitude v = sqrt(ci^2 + cq^2), approximated here by max(abs(ci),abs(cq)) + 1/2*min(abs(ci),abs(cq)))
-#define CHECK_FOR_SUBCARRIER() { \
+#define CHECK_FOR_SUBCARRIER_old() { \
if(ci < 0) { \
if(cq < 0) { /* ci < 0, cq < 0 */ \
if (cq < ci) { \
}
//note: couldn't we just use MAX(ABS(ci),ABS(cq)) + (MIN(ABS(ci),ABS(cq))/2) from common.h - marshmellow
-#define CHECK_FOR_SUBCARRIER_un() { \
+#define CHECK_FOR_SUBCARRIER() { \
myI = ABS(ci); \
myQ = ABS(cq); \
- v = MAX(myI,myQ) + (MIN(myI,myQ) >> 1); \
+ v = MAX(myI, myQ) + (MIN(myI, myQ) >> 1); \
}
switch(Demod.state) {
Demod.posCount = 0; // start of SOF sequence
} else {
// maximum length of TR1 = 200 1/fs
- if(Demod.posCount > 25*2) Demod.state = DEMOD_UNSYNCD;
+ if(Demod.posCount > 26*2) Demod.state = DEMOD_UNSYNCD;
}
++Demod.posCount;
break;
if(v > 0) {
// low phase of SOF too short (< 9 etu). Note: spec is >= 10, but FPGA tends to "smear" edges
- if(Demod.posCount < 9*2) {
+ if(Demod.posCount < 8*2) {
Demod.state = DEMOD_UNSYNCD;
} else {
LED_C_ON(); // Got SOF
}
} else {
// low phase of SOF too long (> 12 etu)
- if (Demod.posCount > 12*2) {
+ if (Demod.posCount > 14*2) {
Demod.state = DEMOD_UNSYNCD;
LED_C_OFF();
}
MAKE_SOFT_DECISION();
if (v > 0) {
- if(Demod.posCount > 3*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
+ if(Demod.posCount > 2*2) { // max 19us between characters = 16 1/fs, max 3 etu after low phase of SOF = 24 1/fs
Demod.state = DEMOD_UNSYNCD;
LED_C_OFF();
}
Demod.shiftReg >>= 1;
// logic '1'
- if(Demod.thisBit > 0) Demod.shiftReg |= 0x200;
+ if (Demod.thisBit > 0) Demod.shiftReg |= 0x200;
++Demod.bitCount;
- if(Demod.bitCount == 10) {
+ // 1 start 8 data 1 stop = 10
+ if (Demod.bitCount == 10) {
uint16_t s = Demod.shiftReg;
* quiet: set to 'TRUE' to disable debug output
*/
static void GetTagSamplesFor14443bDemod() {
- bool gotFrame = FALSE;
+ bool gotFrame = FALSE, finished = FALSE;
int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
- int max = 0, ci = 0, cq = 0, samples = 0;
+ int ci = 0, cq = 0, samples = 0;
uint32_t time_0 = 0, time_stop = 0;
BigBuf_free();
if (MF_DBGLEVEL > 1) Dbprintf("FpgaSetupSscDma failed. Exiting");
return;
}
-
- time_0 = GetCountSspClk();
-
+
// And put the FPGA in the appropriate mode
FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ);
+
+ // get current clock
+ time_0 = GetCountSspClk();
- while( !BUTTON_PRESS() ) {
- WDT_HIT();
+ // rx counter - dma counter? (how much?) & (mod) mask > 2. (since 2bytes at the time is read)
+ while ( !finished ) {
- int behindBy = lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR;
- if(behindBy > max) max = behindBy;
+ LED_A_INV();
+ WDT_HIT();
- // rx counter - dma counter? (how much?) & (mod) dma buff / 2. (since 2bytes at the time is read)
- while(((lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1)) > 2) {
+ // LSB is a fpga signal bit.
+ ci = upTo[0] >> 1;
+ cq = upTo[1] >> 1;
+ upTo += 2;
+ samples += 2;
- ci = upTo[0];
- cq = upTo[1];
- upTo += 2;
- samples += 2;
-
- // restart DMA buffer to receive again.
- if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
- upTo = dmaBuf;
- AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
- AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
- }
-
- lastRxCounter -= 2;
- if(lastRxCounter <= 0)
- lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
+ lastRxCounter -= 2;
- // is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
- //gotFrame = Handle14443bTagSamplesDemod(ci & 0xfe, cq & 0xfe);
- gotFrame = Handle14443bTagSamplesDemod(ci, cq);
- if ( gotFrame ) break;
- LED_A_INV();
+ // restart DMA buffer to receive again.
+ if(upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
+ upTo = dmaBuf;
+ lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
+ AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) upTo;
+ AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
}
+ // https://github.com/Proxmark/proxmark3/issues/103
+ //gotFrame = Handle14443bTagSamplesDemod(ci & 0xfe, cq & 0xfe);
+ gotFrame = Handle14443bTagSamplesDemod(ci, cq);
time_stop = GetCountSspClk() - time_0;
-
- if(time_stop > iso14b_timeout || gotFrame) break;
+
+ finished = (time_stop > iso14b_timeout || gotFrame);
}
FpgaDisableSscDma();
-
+
+ if ( upTo ) upTo = NULL;
+
if (MF_DBGLEVEL >= 3) {
- Dbprintf("max behindby = %d, samples = %d, gotFrame = %s, Demod.state = %d, Demod.len = %u",
- max,
- samples,
- (gotFrame) ? "true" : "false",
+ Dbprintf("Demod.state = %d, Demod.len = %u, PDC_RCR = %u",
Demod.state,
- Demod.len
+ Demod.len,
+ AT91C_BASE_PDC_SSC->PDC_RCR
);
}
+
+ // print the last batch of IQ values from FPGA
+ if (MF_DBGLEVEL == 4)
+ Dbhexdump(ISO14443B_DMA_BUFFER_SIZE, (uint8_t *)dmaBuf, FALSE);
+
if ( Demod.len > 0 )
LogTrace(Demod.output, Demod.len, Demod.startTime, Demod.endTime, NULL, FALSE);
}
//-----------------------------------------------------------------------------
static void TransmitFor14443b_AsReader(void) {
- FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
- SpinDelay(20);
-
- int c;
// we could been in following mode:
// FPGA_MAJOR_MODE_HF_READER_RX_XCORR | FPGA_HF_READER_RX_XCORR_848_KHZ
// if its second call or more
+
+ // while(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
+ // AT91C_BASE_SSC->SSC_THR = 0XFF;
+ // }
+
+ FpgaWriteConfWord(FPGA_MAJOR_MODE_HF_READER_TX | FPGA_HF_READER_TX_SHALLOW_MOD);
+ SpinDelay(40);
+ int c;
+ volatile uint32_t b;
+
// What does this loop do? Is it TR1?
- for(c = 0; c < 10;) {
+ // 0xFF = 8 bits of 1. 1 bit == 1Etu,..
+ // loop 10 * 8 = 80 ETU of delay, with a non modulated signal. why?
+ // 80*9 = 720us.
+ for(c = 0; c < 50;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
AT91C_BASE_SSC->SSC_THR = 0xFF;
++c;
}
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ b = AT91C_BASE_SSC->SSC_RHR;
+ (void)b;
+ }
}
-
+
// Send frame loop
for(c = 0; c < ToSendMax;) {
if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_TXRDY)) {
- AT91C_BASE_SSC->SSC_THR = ToSend[c];
- ++c;
+ AT91C_BASE_SSC->SSC_THR = ToSend[c++];
}
+ if(AT91C_BASE_SSC->SSC_SR & (AT91C_SSC_RXRDY)) {
+ b = AT91C_BASE_SSC->SSC_RHR;
+ (void)b;
+ }
}
+ //WaitForFpgaDelayQueueIsEmpty(delay);
+ // We should wait here for the FPGA to send all bits.
WDT_HIT();
}
*
* 1 ETU == 1 BIT!
* TR0 - 8 ETUS minimum.
+ *
+ * QUESTION: how long is a 1 or 0 in pulses in the xcorr_848 mode?
+ * 1 "stuffbit" = 1ETU (9us)
*/
int i;
uint8_t b;
// Transition time. TR0 - guard time
// 8ETUS minum?
// Per specification, Subcarrier must be stopped no later than 2 ETUs after EOF.
- for(i = 0; i < 40 ; ++i) ToSendStuffBit(1);
+ // I'm guessing this is for the FPGA to be able to send all bits before we switch to listening mode
+ for(i = 0; i < 32 ; ++i) ToSendStuffBit(1);
// TR1 - Synchronization time
// Convert from last character reference to length
return 3;
// CID
- if (card) card->cid = Demod.output[0];
-
- uint8_t fwt = card->atqb[6]>>4;
- if ( fwt < 16 ){
- uint32_t fwt_time = (302 << fwt);
- iso14b_set_timeout( fwt_time);
+ if (card) {
+ card->cid = Demod.output[0];
+ uint8_t fwt = card->atqb[6] >> 4;
+ if ( fwt < 16 ){
+ uint32_t fwt_time = (302 << fwt);
+ iso14b_set_timeout( fwt_time);
+ }
}
// reset PCB block number
pcb_blocknum = 0;
void RAMFUNC SnoopIso14443b(void) {
uint32_t time_0 = 0, time_start = 0, time_stop = 0;
-
+ int ci = 0, cq = 0;
+ int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
+
// We won't start recording the frames that we acquire until we trigger;
// a good trigger condition to get started is probably when we see a
// response from the tag.
- int triggered = TRUE; // TODO: set and evaluate trigger condition
- int ci, cq;
- int maxBehindBy = 0;
- //int behindBy = 0;
- int lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
-
+ bool triggered = TRUE; // TODO: set and evaluate trigger condition
bool TagIsActive = FALSE;
bool ReaderIsActive = FALSE;
for(;;) {
WDT_HIT();
-
- int behindBy = (lastRxCounter - AT91C_BASE_PDC_SSC->PDC_RCR) & (ISO14443B_DMA_BUFFER_SIZE-1);
- if ( behindBy > maxBehindBy )
- maxBehindBy = behindBy;
-
- if ( behindBy < 2 ) continue;
-
ci = upTo[0];
cq = upTo[1];
- upTo += 2;
-
+ upTo += 2;
lastRxCounter -= 2;
if (upTo >= dmaBuf + ISO14443B_DMA_BUFFER_SIZE) {
upTo = dmaBuf;
- lastRxCounter += ISO14443B_DMA_BUFFER_SIZE;
+ lastRxCounter = ISO14443B_DMA_BUFFER_SIZE;
AT91C_BASE_PDC_SSC->PDC_RNPR = (uint32_t) dmaBuf;
AT91C_BASE_PDC_SSC->PDC_RNCR = ISO14443B_DMA_BUFFER_SIZE;
- WDT_HIT();
-
- // TODO: understand whether we can increase/decrease as we want or not?
- if ( behindBy > ( 9 * ISO14443B_DMA_BUFFER_SIZE/10) ) {
- Dbprintf("blew circular buffer! behindBy=%d", behindBy);
- break;
- }
-
- if(!tracing) {
- DbpString("Trace full");
+
+ if (!tracing) {
+ if (MF_DBGLEVEL >= 2) DbpString("Trace full");
break;
}
- if(BUTTON_PRESS()) {
- DbpString("cancelled");
+ if (BUTTON_PRESS()) {
+ if (MF_DBGLEVEL >= 2) DbpString("cancelled");
break;
}
}
// no need to try decoding reader data if the tag is sending
if (Handle14443bReaderUartBit(ci & 0x01)) {
- time_stop = (GetCountSspClk()-time_0);
+ time_stop = GetCountSspClk() - time_0;
if (triggered)
LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
/* false-triggered by the commands from the reader. */
DemodReset();
} else {
- time_start = (GetCountSspClk()-time_0);
+ time_start = GetCountSspClk() - time_0;
}
if (Handle14443bReaderUartBit(cq & 0x01)) {
- time_stop = (GetCountSspClk()-time_0);
+ time_stop = GetCountSspClk() - time_0;
if (triggered)
LogTrace(Uart.output, Uart.byteCnt, time_start, time_stop, NULL, TRUE);
/* false-triggered by the commands from the reader. */
DemodReset();
} else {
- time_start = (GetCountSspClk()-time_0);
+ time_start = GetCountSspClk() - time_0;
}
ReaderIsActive = (Uart.state > STATE_GOT_FALLING_EDGE_OF_SOF);
LED_A_OFF();
}
- if(!ReaderIsActive) {
+ if (!ReaderIsActive) {
// no need to try decoding tag data if the reader is sending - and we cannot afford the time
// is this | 0x01 the error? & 0xfe in https://github.com/Proxmark/proxmark3/issues/103
- if(Handle14443bTagSamplesDemod(ci & 0xFE, cq & 0xFE)) {
+ // LSB is a fpga signal bit.
+ if (Handle14443bTagSamplesDemod(ci >> 1, cq >> 1)) {
- time_stop = (GetCountSspClk()-time_0);
+ time_stop = GetCountSspClk() - time_0;
LogTrace(Demod.output, Demod.len, time_start, time_stop, NULL, FALSE);
// And ready to receive another response.
DemodReset();
} else {
- time_start = (GetCountSspClk()-time_0);
+ time_start = GetCountSspClk() - time_0;
}
TagIsActive = (Demod.state > DEMOD_GOT_FALLING_EDGE_OF_SOF);
}
switch_off(); // Snoop
DbpString("Snoop statistics:");
- Dbprintf(" Max behind by: %i", maxBehindBy);
Dbprintf(" Uart State: %x ByteCount: %i ByteCountMax: %i", Uart.state, Uart.byteCnt, Uart.byteCntMax);
Dbprintf(" Trace length: %i", BigBuf_get_traceLen());
// free mem refs.
- if ( dmaBuf ) dmaBuf = NULL;
- if ( upTo ) upTo = NULL;
+ if ( upTo ) upTo = NULL;
+
// Uart.byteCntMax should be set with ATQB value..
}
projects / proxmark3-svn / blobdiff